| blob | cbbb8878daa3a841d9247088c7c713d8bc169b29 |
1 /*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
27 / {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 model = "ARM RealView PB1176";
31 compatible = "arm,realview-pb1176";
33 chosen { };
35 aliases {
36 serial0 = &pb1176_serial0;
37 serial1 = &pb1176_serial1;
38 serial2 = &pb1176_serial2;
39 serial3 = &pb1176_serial3;
40 serial4 = &fpga_serial;
41 };
43 memory {
44 device_type = "memory";
45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
47 };
49 /* The voltage to the MMC card is hardwired at 3.3V */
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-boot-on;
56 };
58 veth: regulator-veth {
59 compatible = "regulator-fixed";
60 regulator-name = "veth";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-boot-on;
64 };
66 xtal24mhz: xtal24mhz@24M {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <24000000>;
70 };
72 timclk: timclk@1M {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75 clock-div = <24>;
76 clock-mult = <1>;
77 clocks = <&xtal24mhz>;
78 };
80 mclk: mclk@24M {
81 #clock-cells = <0>;
82 compatible = "fixed-factor-clock";
83 clock-div = <1>;
84 clock-mult = <1>;
85 clocks = <&xtal24mhz>;
86 };
88 kmiclk: kmiclk@24M {
89 #clock-cells = <0>;
90 compatible = "fixed-factor-clock";
91 clock-div = <1>;
92 clock-mult = <1>;
93 clocks = <&xtal24mhz>;
94 };
96 sspclk: sspclk@24M {
97 #clock-cells = <0>;
98 compatible = "fixed-factor-clock";
99 clock-div = <1>;
100 clock-mult = <1>;
101 clocks = <&xtal24mhz>;
102 };
104 uartclk: uartclk@24M {
105 #clock-cells = <0>;
106 compatible = "fixed-factor-clock";
107 clock-div = <1>;
108 clock-mult = <1>;
109 clocks = <&xtal24mhz>;
110 };
112 /* FIXME: this actually hangs off the PLL clocks */
113 pclk: pclk@0 {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <0>;
117 };
119 flash@30000000 {
120 compatible = "arm,versatile-flash", "cfi-flash";
121 reg = <0x30000000 0x4000000>;
122 bank-width = <4>;
123 };
125 fpga_flash@38000000 {
126 compatible = "arm,versatile-flash", "cfi-flash";
127 reg = <0x38000000 0x800000>;
128 bank-width = <4>;
129 };
131 /*
132 * The "secure flash" contains things like the boot
133 * monitor so we don't want people to accidentally
134 * screw this up. Mark the device tree node disabled
135 * by default.
136 */
137 secflash@3c000000 {
138 compatible = "arm,versatile-flash", "cfi-flash";
139 reg = <0x3c000000 0x4000000>;
140 bank-width = <4>;
141 status = "disabled";
142 };
144 /* SMSC 9118 ethernet with PHY and EEPROM */
145 ethernet@3a000000 {
146 compatible = "smsc,lan9118", "smsc,lan9115";
147 reg = <0x3a000000 0x10000>;
148 interrupt-parent = <&intc_fpga1176>;
149 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
150 phy-mode = "mii";
151 reg-io-width = <4>;
152 smsc,irq-active-high;
153 smsc,irq-push-pull;
154 vdd33a-supply = <&veth>;
155 vddvario-supply = <&veth>;
156 };
158 usb@3b000000 {
159 compatible = "nxp,usb-isp1761";
160 reg = <0x3b000000 0x20000>;
161 interrupt-parent = <&intc_fpga1176>;
162 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
163 port1-otg;
164 };
166 bridge {
167 compatible = "ti,ths8134a", "ti,ths8134";
168 #address-cells = <1>;
169 #size-cells = <0>;
171 ports {
172 #address-cells = <1>;
173 #size-cells = <0>;
175 port@0 {
176 reg = <0>;
178 vga_bridge_in: endpoint {
179 remote-endpoint = <&clcd_pads>;
180 };
181 };
183 port@1 {
184 reg = <1>;
186 vga_bridge_out: endpoint {
187 remote-endpoint = <&vga_con_in>;
188 };
189 };
190 };
191 };
193 vga {
194 compatible = "vga-connector";
196 port {
197 vga_con_in: endpoint {
198 remote-endpoint = <&vga_bridge_out>;
199 };
200 };
201 };
203 soc {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 compatible = "arm,realview-pb1176-soc", "simple-bus";
207 regmap = <&syscon>;
208 ranges;
210 syscon: syscon@10000000 {
211 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
212 reg = <0x10000000 0x1000>;
214 led@08.0 {
215 compatible = "register-bit-led";
216 offset = <0x08>;
217 mask = <0x01>;
218 label = "versatile:0";
219 linux,default-trigger = "heartbeat";
220 default-state = "on";
221 };
222 led@08.1 {
223 compatible = "register-bit-led";
224 offset = <0x08>;
225 mask = <0x02>;
226 label = "versatile:1";
227 linux,default-trigger = "mmc0";
228 default-state = "off";
229 };
230 led@08.2 {
231 compatible = "register-bit-led";
232 offset = <0x08>;
233 mask = <0x04>;
234 label = "versatile:2";
235 linux,default-trigger = "cpu0";
236 default-state = "off";
237 };
238 led@08.3 {
239 compatible = "register-bit-led";
240 offset = <0x08>;
241 mask = <0x08>;
242 label = "versatile:3";
243 default-state = "off";
244 };
245 led@08.4 {
246 compatible = "register-bit-led";
247 offset = <0x08>;
248 mask = <0x10>;
249 label = "versatile:4";
250 default-state = "off";
251 };
252 led@08.5 {
253 compatible = "register-bit-led";
254 offset = <0x08>;
255 mask = <0x20>;
256 label = "versatile:5";
257 default-state = "off";
258 };
259 led@08.6 {
260 compatible = "register-bit-led";
261 offset = <0x08>;
262 mask = <0x40>;
263 label = "versatile:6";
264 default-state = "off";
265 };
266 led@08.7 {
267 compatible = "register-bit-led";
268 offset = <0x08>;
269 mask = <0x80>;
270 label = "versatile:7";
271 default-state = "off";
272 };
273 oscclk0: osc0@0c {
274 compatible = "arm,syscon-icst307";
275 #clock-cells = <0>;
276 lock-offset = <0x20>;
277 vco-offset = <0x0C>;
278 clocks = <&xtal24mhz>;
279 };
280 oscclk1: osc1@10 {
281 compatible = "arm,syscon-icst307";
282 #clock-cells = <0>;
283 lock-offset = <0x20>;
284 vco-offset = <0x10>;
285 clocks = <&xtal24mhz>;
286 };
287 oscclk2: osc2@14 {
288 compatible = "arm,syscon-icst307";
289 #clock-cells = <0>;
290 lock-offset = <0x20>;
291 vco-offset = <0x14>;
292 clocks = <&xtal24mhz>;
293 };
294 oscclk3: osc3@18 {
295 compatible = "arm,syscon-icst307";
296 #clock-cells = <0>;
297 lock-offset = <0x20>;
298 vco-offset = <0x18>;
299 clocks = <&xtal24mhz>;
300 };
301 oscclk4: osc4@1c {
302 compatible = "arm,syscon-icst307";
303 #clock-cells = <0>;
304 lock-offset = <0x20>;
305 vco-offset = <0x1c>;
306 clocks = <&xtal24mhz>;
307 };
308 };
310 /* Primary DevChip GIC synthesized with the CPU */
311 intc_dc1176: interrupt-controller@10120000 {
312 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
313 #interrupt-cells = <3>;
314 #address-cells = <1>;
315 interrupt-controller;
316 reg = <0x10121000 0x1000>,
317 <0x10120000 0x100>;
318 };
320 L2: l2-cache {
321 compatible = "arm,l220-cache";
322 reg = <0x10110000 0x1000>;
323 interrupt-parent = <&intc_dc1176>;
324 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
325 cache-unified;
326 cache-level = <2>;
327 /*
328 * Override default cache size, sets and
329 * associativity as these may be erroneously set
330 * up by boot loader(s).
331 */
332 arm,override-auxreg;
333 cache-size = <131072>; // 128kB
334 cache-sets = <512>;
335 cache-line-size = <32>;
336 };
338 pmu {
339 compatible = "arm,arm1176-pmu";
340 interrupt-parent = <&intc_dc1176>;
341 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
342 };
344 timer01: timer@10104000 {
345 compatible = "arm,sp804", "arm,primecell";
346 reg = <0x10104000 0x1000>;
347 interrupt-parent = <&intc_dc1176>;
348 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&timclk>, <&timclk>, <&pclk>;
350 clock-names = "timer1", "timer2", "apb_pclk";
351 };
353 timer23: timer@10105000 {
354 compatible = "arm,sp804", "arm,primecell";
355 reg = <0x10105000 0x1000>;
356 interrupt-parent = <&intc_dc1176>;
357 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
358 arm,sp804-has-irq = <1>;
359 clocks = <&timclk>, <&timclk>, <&pclk>;
360 clock-names = "timer1", "timer2", "apb_pclk";
361 };
363 pb1176_rtc: rtc@10108000 {
364 compatible = "arm,pl031", "arm,primecell";
365 reg = <0x10108000 0x1000>;
366 interrupt-parent = <&intc_dc1176>;
367 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&pclk>;
369 clock-names = "apb_pclk";
370 };
372 pb1176_gpio0: gpio@1010a000 {
373 compatible = "arm,pl061", "arm,primecell";
374 reg = <0x1010a000 0x1000>;
375 gpio-controller;
376 interrupt-parent = <&intc_dc1176>;
377 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
378 #gpio-cells = <2>;
379 interrupt-controller;
380 #interrupt-cells = <2>;
381 clocks = <&pclk>;
382 clock-names = "apb_pclk";
383 };
385 pb1176_ssp: spi@1010b000 {
386 compatible = "arm,pl022", "arm,primecell";
387 reg = <0x1010b000 0x1000>;
388 interrupt-parent = <&intc_dc1176>;
389 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&sspclk>, <&pclk>;
391 clock-names = "SSPCLK", "apb_pclk";
392 };
394 pb1176_serial0: serial@1010c000 {
395 compatible = "arm,pl011", "arm,primecell";
396 reg = <0x1010c000 0x1000>;
397 interrupt-parent = <&intc_dc1176>;
398 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&uartclk>, <&pclk>;
400 clock-names = "uartclk", "apb_pclk";
401 };
403 pb1176_serial1: serial@1010d000 {
404 compatible = "arm,pl011", "arm,primecell";
405 reg = <0x1010d000 0x1000>;
406 interrupt-parent = <&intc_dc1176>;
407 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&uartclk>, <&pclk>;
409 clock-names = "uartclk", "apb_pclk";
410 };
412 pb1176_serial2: serial@1010e000 {
413 compatible = "arm,pl011", "arm,primecell";
414 reg = <0x1010e000 0x1000>;
415 interrupt-parent = <&intc_dc1176>;
416 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&uartclk>, <&pclk>;
418 clock-names = "uartclk", "apb_pclk";
419 };
421 pb1176_serial3: serial@1010f000 {
422 compatible = "arm,pl011", "arm,primecell";
423 reg = <0x1010f000 0x1000>;
424 interrupt-parent = <&intc_dc1176>;
425 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&uartclk>, <&pclk>;
427 clock-names = "uartclk", "apb_pclk";
428 };
430 /* Direct-mapped development chip ROM */
431 pb1176_rom@10200000 {
432 compatible = "direct-mapped";
433 reg = <0x10200000 0x4000>;
434 bank-width = <1>;
435 };
437 clcd@10112000 {
438 compatible = "arm,pl111", "arm,primecell";
439 reg = <0x10112000 0x1000>;
440 interrupt-parent = <&intc_dc1176>;
441 interrupt-names = "combined";
442 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&oscclk0>, <&pclk>;
444 clock-names = "clcdclk", "apb_pclk";
445 /* 1024x768 16bpp @65MHz works fine */
446 max-memory-bandwidth = <95000000>;
448 port {
449 clcd_pads: endpoint {
450 remote-endpoint = <&vga_bridge_in>;
451 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
452 };
453 };
454 };
455 };
457 /* These peripherals are inside the FPGA rather than the DevChip */
458 fpga {
459 #address-cells = <1>;
460 #size-cells = <1>;
461 compatible = "simple-bus";
462 ranges;
464 i2c0: i2c@10002000 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 compatible = "arm,versatile-i2c";
468 reg = <0x10002000 0x1000>;
470 rtc@68 {
471 compatible = "dallas,ds1338";
472 reg = <0x68>;
473 };
474 };
476 fpga_aaci: aaci@10004000 {
477 compatible = "arm,pl041", "arm,primecell";
478 reg = <0x10004000 0x1000>;
479 interrupt-parent = <&intc_fpga1176>;
480 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&pclk>;
482 clock-names = "apb_pclk";
483 };
485 fpga_mci: mmcsd@10005000 {
486 compatible = "arm,pl18x", "arm,primecell";
487 reg = <0x10005000 0x1000>;
488 interrupt-parent = <&intc_fpga1176>;
489 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
490 <0 2 IRQ_TYPE_LEVEL_HIGH>;
491 /* Due to frequent FIFO overruns, use just 500 kHz */
492 max-frequency = <500000>;
493 bus-width = <4>;
494 cap-sd-highspeed;
495 cap-mmc-highspeed;
496 clocks = <&mclk>, <&pclk>;
497 clock-names = "mclk", "apb_pclk";
498 vmmc-supply = <&vmmc>;
499 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
500 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
501 };
503 fpga_kmi0: kmi@10006000 {
504 compatible = "arm,pl050", "arm,primecell";
505 reg = <0x10006000 0x1000>;
506 interrupt-parent = <&intc_fpga1176>;
507 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&kmiclk>, <&pclk>;
509 clock-names = "KMIREFCLK", "apb_pclk";
510 };
512 fpga_kmi1: kmi@10007000 {
513 compatible = "arm,pl050", "arm,primecell";
514 reg = <0x10007000 0x1000>;
515 interrupt-parent = <&intc_fpga1176>;
516 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&kmiclk>, <&pclk>;
518 clock-names = "KMIREFCLK", "apb_pclk";
519 };
521 fpga_charlcd: charlcd@10008000 {
522 compatible = "arm,versatile-lcd";
523 reg = <0x10008000 0x1000>;
524 interrupt-parent = <&intc_fpga1176>;
525 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&pclk>;
527 clock-names = "apb_pclk";
528 };
530 fpga_serial: serial@10009000 {
531 compatible = "arm,pl011", "arm,primecell";
532 reg = <0x10009000 0x1000>;
533 interrupt-parent = <&intc_fpga1176>;
534 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&uartclk>, <&pclk>;
536 clock-names = "uartclk", "apb_pclk";
537 };
539 /* This GIC on the board is cascaded off the DevChip GIC */
540 intc_fpga1176: interrupt-controller@10040000 {
541 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
542 #interrupt-cells = <3>;
543 #address-cells = <1>;
544 interrupt-controller;
545 reg = <0x10041000 0x1000>,
546 <0x10040000 0x100>;
547 interrupt-parent = <&intc_dc1176>;
548 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
549 };
551 fpga_gpio0: gpio@10014000 {
552 compatible = "arm,pl061", "arm,primecell";
553 reg = <0x10014000 0x1000>;
554 gpio-controller;
555 interrupt-parent = <&intc_fpga1176>;
556 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
557 #gpio-cells = <2>;
558 interrupt-controller;
559 #interrupt-cells = <2>;
560 clocks = <&pclk>;
561 clock-names = "apb_pclk";
562 };
564 fpga_gpio1: gpio@10015000 {
565 compatible = "arm,pl061", "arm,primecell";
566 reg = <0x10015000 0x1000>;
567 gpio-controller;
568 interrupt-parent = <&intc_fpga1176>;
569 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
570 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 clocks = <&pclk>;
574 clock-names = "apb_pclk";
575 };
577 fpga_rtc: rtc@10017000 {
578 compatible = "arm,pl031", "arm,primecell";
579 reg = <0x10017000 0x1000>;
580 interrupt-parent = <&intc_fpga1176>;
581 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&pclk>;
583 clock-names = "apb_pclk";
584 };
585 };
586 };