| blob | 96c18703e4717d513810dcc6f7ff3ad561ae7d63 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 38x family of SoCs.
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 */
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 38x family SoC";
22 compatible = "marvell,armada380";
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 };
31 pmu {
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
34 };
36 soc {
37 compatible = "marvell,armada380-mbus", "simple-bus";
38 #address-cells = <2>;
39 #size-cells = <1>;
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
45 bootrom {
46 compatible = "marvell,bootrom";
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
48 };
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
106 L2: cache-controller@8000 {
107 compatible = "arm,pl310-cache";
108 reg = <0x8000 0x1000>;
109 cache-unified;
110 cache-level = <2>;
111 arm,double-linefill-incr = <0>;
112 arm,double-linefill-wrap = <0>;
113 arm,double-linefill = <0>;
114 prefetch-data = <1>;
115 };
117 scu@c000 {
118 compatible = "arm,cortex-a9-scu";
119 reg = <0xc000 0x58>;
120 };
122 timer@c200 {
123 compatible = "arm,cortex-a9-global-timer";
124 reg = <0xc200 0x20>;
125 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
126 clocks = <&coreclk 2>;
127 };
129 timer@c600 {
130 compatible = "arm,cortex-a9-twd-timer";
131 reg = <0xc600 0x20>;
132 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
133 clocks = <&coreclk 2>;
134 };
136 gic: interrupt-controller@d000 {
137 compatible = "arm,cortex-a9-gic";
138 #interrupt-cells = <3>;
139 #size-cells = <0>;
140 interrupt-controller;
141 reg = <0xd000 0x1000>,
142 <0xc100 0x100>;
143 };
145 i2c0: i2c@11000 {
146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
147 reg = <0x11000 0x20>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
151 timeout-ms = <1000>;
152 clocks = <&coreclk 0>;
153 status = "disabled";
154 };
156 i2c1: i2c@11100 {
157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
158 reg = <0x11100 0x20>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
162 timeout-ms = <1000>;
163 clocks = <&coreclk 0>;
164 status = "disabled";
165 };
167 uart0: serial@12000 {
168 compatible = "marvell,armada-38x-uart";
169 reg = <0x12000 0x100>;
170 reg-shift = <2>;
171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
172 reg-io-width = <1>;
173 clocks = <&coreclk 0>;
174 status = "disabled";
175 };
177 uart1: serial@12100 {
178 compatible = "marvell,armada-38x-uart";
179 reg = <0x12100 0x100>;
180 reg-shift = <2>;
181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
182 reg-io-width = <1>;
183 clocks = <&coreclk 0>;
184 status = "disabled";
185 };
187 pinctrl: pinctrl@18000 {
188 reg = <0x18000 0x20>;
190 ge0_rgmii_pins: ge-rgmii-pins-0 {
191 marvell,pins = "mpp6", "mpp7", "mpp8",
192 "mpp9", "mpp10", "mpp11",
193 "mpp12", "mpp13", "mpp14",
194 "mpp15", "mpp16", "mpp17";
195 marvell,function = "ge0";
196 };
198 ge1_rgmii_pins: ge-rgmii-pins-1 {
199 marvell,pins = "mpp21", "mpp27", "mpp28",
200 "mpp29", "mpp30", "mpp31",
201 "mpp32", "mpp37", "mpp38",
202 "mpp39", "mpp40", "mpp41";
203 marvell,function = "ge1";
204 };
206 i2c0_pins: i2c-pins-0 {
207 marvell,pins = "mpp2", "mpp3";
208 marvell,function = "i2c0";
209 };
211 mdio_pins: mdio-pins {
212 marvell,pins = "mpp4", "mpp5";
213 marvell,function = "ge";
214 };
216 ref_clk0_pins: ref-clk-pins-0 {
217 marvell,pins = "mpp45";
218 marvell,function = "ref";
219 };
221 ref_clk1_pins: ref-clk-pins-1 {
222 marvell,pins = "mpp46";
223 marvell,function = "ref";
224 };
226 spi0_pins: spi-pins-0 {
227 marvell,pins = "mpp22", "mpp23", "mpp24",
228 "mpp25";
229 marvell,function = "spi0";
230 };
232 spi1_pins: spi-pins-1 {
233 marvell,pins = "mpp56", "mpp57", "mpp58",
234 "mpp59";
235 marvell,function = "spi1";
236 };
238 nand_pins: nand-pins {
239 marvell,pins = "mpp22", "mpp34", "mpp23",
240 "mpp33", "mpp38", "mpp28",
241 "mpp40", "mpp42", "mpp35",
242 "mpp36", "mpp25", "mpp30",
243 "mpp32";
244 marvell,function = "dev";
245 };
247 nand_rb: nand-rb {
248 marvell,pins = "mpp41";
249 marvell,function = "nand";
250 };
252 uart0_pins: uart-pins-0 {
253 marvell,pins = "mpp0", "mpp1";
254 marvell,function = "ua0";
255 };
257 uart1_pins: uart-pins-1 {
258 marvell,pins = "mpp19", "mpp20";
259 marvell,function = "ua1";
260 };
262 sdhci_pins: sdhci-pins {
263 marvell,pins = "mpp48", "mpp49", "mpp50",
264 "mpp52", "mpp53", "mpp54",
265 "mpp55", "mpp57", "mpp58",
266 "mpp59";
267 marvell,function = "sd0";
268 };
270 sata0_pins: sata-pins-0 {
271 marvell,pins = "mpp20";
272 marvell,function = "sata0";
273 };
275 sata1_pins: sata-pins-1 {
276 marvell,pins = "mpp19";
277 marvell,function = "sata1";
278 };
280 sata2_pins: sata-pins-2 {
281 marvell,pins = "mpp47";
282 marvell,function = "sata2";
283 };
285 sata3_pins: sata-pins-3 {
286 marvell,pins = "mpp44";
287 marvell,function = "sata3";
288 };
289 };
291 gpio0: gpio@18100 {
292 compatible = "marvell,armada-370-gpio",
293 "marvell,orion-gpio";
294 reg = <0x18100 0x40>, <0x181c0 0x08>;
295 reg-names = "gpio", "pwm";
296 ngpios = <32>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 #pwm-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&coreclk 0>;
307 };
309 gpio1: gpio@18140 {
310 compatible = "marvell,armada-370-gpio",
311 "marvell,orion-gpio";
312 reg = <0x18140 0x40>, <0x181c8 0x08>;
313 reg-names = "gpio", "pwm";
314 ngpios = <28>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 #pwm-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&coreclk 0>;
325 };
327 systemc: system-controller@18200 {
328 compatible = "marvell,armada-380-system-controller",
329 "marvell,armada-370-xp-system-controller";
330 reg = <0x18200 0x100>;
331 };
333 gateclk: clock-gating-control@18220 {
334 compatible = "marvell,armada-380-gating-clock";
335 reg = <0x18220 0x4>;
336 clocks = <&coreclk 0>;
337 #clock-cells = <1>;
338 };
340 comphy: phy@18300 {
341 compatible = "marvell,armada-380-comphy";
342 reg = <0x18300 0x100>;
343 #address-cells = <1>;
344 #size-cells = <0>;
346 comphy0: phy@0 {
347 reg = <0>;
348 #phy-cells = <1>;
349 };
351 comphy1: phy@1 {
352 reg = <1>;
353 #phy-cells = <1>;
354 };
356 comphy2: phy@2 {
357 reg = <2>;
358 #phy-cells = <1>;
359 };
361 comphy3: phy@3 {
362 reg = <3>;
363 #phy-cells = <1>;
364 };
366 comphy4: phy@4 {
367 reg = <4>;
368 #phy-cells = <1>;
369 };
371 comphy5: phy@5 {
372 reg = <5>;
373 #phy-cells = <1>;
374 };
375 };
377 coreclk: mvebu-sar@18600 {
378 compatible = "marvell,armada-380-core-clock";
379 reg = <0x18600 0x04>;
380 #clock-cells = <1>;
381 };
383 mbusc: mbus-controller@20000 {
384 compatible = "marvell,mbus-controller";
385 reg = <0x20000 0x100>, <0x20180 0x20>,
386 <0x20250 0x8>;
387 };
389 mpic: interrupt-controller@20a00 {
390 compatible = "marvell,mpic";
391 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
392 #interrupt-cells = <1>;
393 #size-cells = <1>;
394 interrupt-controller;
395 msi-controller;
396 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
397 };
399 timer: timer@20300 {
400 compatible = "marvell,armada-380-timer",
401 "marvell,armada-xp-timer";
402 reg = <0x20300 0x30>, <0x21040 0x30>;
403 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
404 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
405 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
406 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
407 <&mpic 5>,
408 <&mpic 6>;
409 clocks = <&coreclk 2>, <&refclk>;
410 clock-names = "nbclk", "fixed";
411 };
413 watchdog: watchdog@20300 {
414 compatible = "marvell,armada-380-wdt";
415 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
416 clocks = <&coreclk 2>, <&refclk>;
417 clock-names = "nbclk", "fixed";
418 };
420 cpurst: cpurst@20800 {
421 compatible = "marvell,armada-370-cpu-reset";
422 reg = <0x20800 0x10>;
423 };
425 mpcore-soc-ctrl@20d20 {
426 compatible = "marvell,armada-380-mpcore-soc-ctrl";
427 reg = <0x20d20 0x6c>;
428 };
430 coherencyfab: coherency-fabric@21010 {
431 compatible = "marvell,armada-380-coherency-fabric";
432 reg = <0x21010 0x1c>;
433 };
435 pmsu: pmsu@22000 {
436 compatible = "marvell,armada-380-pmsu";
437 reg = <0x22000 0x1000>;
438 };
440 /*
441 * As a special exception to the "order by
442 * register address" rule, the eth0 node is
443 * placed here to ensure that it gets
444 * registered as the first interface, since
445 * the network subsystem doesn't allow naming
446 * interfaces using DT aliases. Without this,
447 * the ordering of interfaces is different
448 * from the one used in U-Boot and the
449 * labeling of interfaces on the boards, which
450 * is very confusing for users.
451 */
452 eth0: ethernet@70000 {
453 compatible = "marvell,armada-370-neta";
454 reg = <0x70000 0x4000>;
455 interrupts-extended = <&mpic 8>;
456 clocks = <&gateclk 4>;
457 tx-csum-limit = <9800>;
458 status = "disabled";
459 };
461 eth1: ethernet@30000 {
462 compatible = "marvell,armada-370-neta";
463 reg = <0x30000 0x4000>;
464 interrupts-extended = <&mpic 10>;
465 clocks = <&gateclk 3>;
466 status = "disabled";
467 };
469 eth2: ethernet@34000 {
470 compatible = "marvell,armada-370-neta";
471 reg = <0x34000 0x4000>;
472 interrupts-extended = <&mpic 12>;
473 clocks = <&gateclk 2>;
474 status = "disabled";
475 };
477 usb0: usb@58000 {
478 compatible = "marvell,orion-ehci";
479 reg = <0x58000 0x500>;
480 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&gateclk 18>;
482 status = "disabled";
483 };
485 xor0: xor@60800 {
486 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
487 reg = <0x60800 0x100
488 0x60a00 0x100>;
489 clocks = <&gateclk 22>;
490 status = "okay";
492 xor00 {
493 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
494 dmacap,memcpy;
495 dmacap,xor;
496 };
497 xor01 {
498 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
499 dmacap,memcpy;
500 dmacap,xor;
501 dmacap,memset;
502 };
503 };
505 xor1: xor@60900 {
506 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
507 reg = <0x60900 0x100
508 0x60b00 0x100>;
509 clocks = <&gateclk 28>;
510 status = "okay";
512 xor10 {
513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
514 dmacap,memcpy;
515 dmacap,xor;
516 };
517 xor11 {
518 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
519 dmacap,memcpy;
520 dmacap,xor;
521 dmacap,memset;
522 };
523 };
525 mdio: mdio@72004 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "marvell,orion-mdio";
529 reg = <0x72004 0x4>;
530 clocks = <&gateclk 4>;
531 };
533 cesa: crypto@90000 {
534 compatible = "marvell,armada-38x-crypto";
535 reg = <0x90000 0x10000>;
536 reg-names = "regs";
537 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&gateclk 23>, <&gateclk 21>,
540 <&gateclk 14>, <&gateclk 16>;
541 clock-names = "cesa0", "cesa1",
542 "cesaz0", "cesaz1";
543 marvell,crypto-srams = <&crypto_sram0>,
544 <&crypto_sram1>;
545 marvell,crypto-sram-size = <0x800>;
546 };
548 rtc: rtc@a3800 {
549 compatible = "marvell,armada-380-rtc";
550 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
551 reg-names = "rtc", "rtc-soc";
552 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
553 };
555 ahci0: sata@a8000 {
556 compatible = "marvell,armada-380-ahci";
557 reg = <0xa8000 0x2000>;
558 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&gateclk 15>;
560 status = "disabled";
561 };
563 bm: bm@c8000 {
564 compatible = "marvell,armada-380-neta-bm";
565 reg = <0xc8000 0xac>;
566 clocks = <&gateclk 13>;
567 internal-mem = <&bm_bppi>;
568 status = "disabled";
569 };
571 ahci1: sata@e0000 {
572 compatible = "marvell,armada-380-ahci";
573 reg = <0xe0000 0x2000>;
574 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&gateclk 30>;
576 status = "disabled";
577 };
579 coredivclk: clock@e4250 {
580 compatible = "marvell,armada-380-corediv-clock";
581 reg = <0xe4250 0xc>;
582 #clock-cells = <1>;
583 clocks = <&mainpll>;
584 clock-output-names = "nand";
585 };
587 thermal: thermal@e8078 {
588 compatible = "marvell,armada380-thermal";
589 reg = <0xe4078 0x4>, <0xe4070 0x8>;
590 status = "okay";
591 };
593 nand_controller: nand-controller@d0000 {
594 compatible = "marvell,armada370-nand-controller";
595 reg = <0xd0000 0x54>;
596 #address-cells = <1>;
597 #size-cells = <0>;
598 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&coredivclk 0>;
600 status = "disabled";
601 };
603 sdhci: sdhci@d8000 {
604 compatible = "marvell,armada-380-sdhci";
605 reg-names = "sdhci", "mbus", "conf-sdio3";
606 reg = <0xd8000 0x1000>,
607 <0xdc000 0x100>,
608 <0x18454 0x4>;
609 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&gateclk 17>;
611 mrvl,clk-delay-cycles = <0x1F>;
612 status = "disabled";
613 };
615 usb3_0: usb3@f0000 {
616 compatible = "marvell,armada-380-xhci";
617 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
618 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&gateclk 9>;
620 status = "disabled";
621 };
623 usb3_1: usb3@f8000 {
624 compatible = "marvell,armada-380-xhci";
625 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
626 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&gateclk 10>;
628 status = "disabled";
629 };
630 };
632 crypto_sram0: sa-sram0 {
633 compatible = "mmio-sram";
634 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
635 clocks = <&gateclk 23>;
636 #address-cells = <1>;
637 #size-cells = <1>;
638 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
639 };
641 crypto_sram1: sa-sram1 {
642 compatible = "mmio-sram";
643 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
644 clocks = <&gateclk 21>;
645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
648 };
650 bm_bppi: bm-bppi {
651 compatible = "mmio-sram";
652 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
653 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
654 #address-cells = <1>;
655 #size-cells = <1>;
656 clocks = <&gateclk 13>;
657 no-memory-wc;
658 status = "disabled";
659 };
661 spi0: spi@10600 {
662 compatible = "marvell,armada-380-spi",
663 "marvell,orion-spi";
664 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 cell-index = <0>;
668 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&coreclk 0>;
670 status = "disabled";
671 };
673 spi1: spi@10680 {
674 compatible = "marvell,armada-380-spi",
675 "marvell,orion-spi";
676 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 cell-index = <1>;
680 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&coreclk 0>;
682 status = "disabled";
683 };
684 };
686 clocks {
687 /* 1 GHz fixed main PLL */
688 mainpll: mainpll {
689 compatible = "fixed-clock";
690 #clock-cells = <0>;
691 clock-frequency = <1000000000>;
692 };
694 /* 25 MHz reference crystal */
695 refclk: oscillator {
696 compatible = "fixed-clock";
697 #clock-cells = <0>;
698 clock-frequency = <25000000>;
699 };
700 };
701 };