| blob | 3fb63d81f18edbe023f1405fd25418d64f279ea6 |
1 /*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clock/at91.h>
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Atmel AT91SAM9263 family SoC";
18 compatible = "atmel,at91sam9263";
19 interrupt-parent = <&aic>;
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 gpio4 = &pioE;
31 tcb0 = &tcb0;
32 i2c0 = &i2c0;
33 ssc0 = &ssc0;
34 ssc1 = &ssc1;
35 pwm0 = &pwm0;
36 };
38 cpus {
39 #address-cells = <0>;
40 #size-cells = <0>;
42 cpu {
43 compatible = "arm,arm926ej-s";
44 device_type = "cpu";
45 };
46 };
48 memory {
49 device_type = "memory";
50 reg = <0x20000000 0x08000000>;
51 };
53 clocks {
54 main_xtal: main_xtal {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
60 slow_xtal: slow_xtal {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
64 };
65 };
67 sram0: sram@300000 {
68 compatible = "mmio-sram";
69 reg = <0x00300000 0x14000>;
70 };
72 sram1: sram@500000 {
73 compatible = "mmio-sram";
74 reg = <0x00500000 0x4000>;
75 };
77 ahb {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
83 apb {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
89 aic: interrupt-controller@fffff000 {
90 #interrupt-cells = <3>;
91 compatible = "atmel,at91rm9200-aic";
92 interrupt-controller;
93 reg = <0xfffff000 0x200>;
94 atmel,external-irqs = <30 31>;
95 };
97 pmc: pmc@fffffc00 {
98 compatible = "atmel,at91sam9263-pmc", "syscon";
99 reg = <0xfffffc00 0x100>;
100 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
101 #clock-cells = <2>;
102 clocks = <&slow_xtal>, <&main_xtal>;
103 clock-names = "slow_xtal", "main_xtal";
104 };
106 ramc0: ramc@ffffe200 {
107 compatible = "atmel,at91sam9260-sdramc";
108 reg = <0xffffe200 0x200>;
109 };
111 smc0: smc@ffffe400 {
112 compatible = "atmel,at91sam9260-smc", "syscon";
113 reg = <0xffffe400 0x200>;
114 };
116 ramc1: ramc@ffffe800 {
117 compatible = "atmel,at91sam9260-sdramc";
118 reg = <0xffffe800 0x200>;
119 };
121 smc1: smc@ffffea00 {
122 compatible = "atmel,at91sam9260-smc", "syscon";
123 reg = <0xffffea00 0x200>;
124 };
126 matrix: matrix@ffffec00 {
127 compatible = "atmel,at91sam9263-matrix", "syscon";
128 reg = <0xffffec00 0x200>;
129 };
131 pit: timer@fffffd30 {
132 compatible = "atmel,at91sam9260-pit";
133 reg = <0xfffffd30 0xf>;
134 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
135 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
136 };
138 tcb0: timer@fff7c000 {
139 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
140 #address-cells = <1>;
141 #size-cells = <0>;
142 reg = <0xfff7c000 0x100>;
143 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
144 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
145 clock-names = "t0_clk", "slow_clk";
146 };
148 rstc@fffffd00 {
149 compatible = "atmel,at91sam9260-rstc";
150 reg = <0xfffffd00 0x10>;
151 clocks = <&slow_xtal>;
152 };
154 shdwc@fffffd10 {
155 compatible = "atmel,at91sam9260-shdwc";
156 reg = <0xfffffd10 0x10>;
157 clocks = <&slow_xtal>;
158 };
160 pinctrl@fffff200 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
164 ranges = <0xfffff200 0xfffff200 0xa00>;
166 atmel,mux-mask = <
167 /* A B */
168 0xfffffffb 0xffffe07f /* pioA */
169 0x0007ffff 0x39072fff /* pioB */
170 0xffffffff 0x3ffffff8 /* pioC */
171 0xfffffbff 0xffffffff /* pioD */
172 0xffe00fff 0xfbfcff00 /* pioE */
173 >;
175 /* shared pinctrl settings */
176 dbgu {
177 pinctrl_dbgu: dbgu-0 {
178 atmel,pins =
179 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
180 AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
181 };
182 };
184 usart0 {
185 pinctrl_usart0: usart0-0 {
186 atmel,pins =
187 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
188 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
189 };
191 pinctrl_usart0_rts: usart0_rts-0 {
192 atmel,pins =
193 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
194 };
196 pinctrl_usart0_cts: usart0_cts-0 {
197 atmel,pins =
198 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
199 };
200 };
202 usart1 {
203 pinctrl_usart1: usart1-0 {
204 atmel,pins =
205 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
206 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
207 };
209 pinctrl_usart1_rts: usart1_rts-0 {
210 atmel,pins =
211 <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
212 };
214 pinctrl_usart1_cts: usart1_cts-0 {
215 atmel,pins =
216 <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
217 };
218 };
220 usart2 {
221 pinctrl_usart2: usart2-0 {
222 atmel,pins =
223 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
224 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
225 };
227 pinctrl_usart2_rts: usart2_rts-0 {
228 atmel,pins =
229 <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
230 };
232 pinctrl_usart2_cts: usart2_cts-0 {
233 atmel,pins =
234 <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
235 };
236 };
238 nand {
239 pinctrl_nand_rb: nand-rb-0 {
240 atmel,pins =
241 <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
242 };
244 pinctrl_nand_cs: nand-cs-0 {
245 atmel,pins =
246 <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
247 };
248 };
250 macb {
251 pinctrl_macb_rmii: macb_rmii-0 {
252 atmel,pins =
253 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
254 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
255 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
256 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
257 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
258 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
259 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
260 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
261 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
262 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
263 };
265 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
266 atmel,pins =
267 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
268 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
269 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
270 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
271 AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
272 AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
273 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
274 AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
275 };
276 };
278 mmc0 {
279 pinctrl_mmc0_clk: mmc0_clk-0 {
280 atmel,pins =
281 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
282 };
284 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
285 atmel,pins =
286 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
287 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
288 };
290 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
291 atmel,pins =
292 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
293 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
294 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
295 };
297 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
298 atmel,pins =
299 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
300 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
301 };
303 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
304 atmel,pins =
305 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
306 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
307 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
308 };
309 };
311 mmc1 {
312 pinctrl_mmc1_clk: mmc1_clk-0 {
313 atmel,pins =
314 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
315 };
317 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
318 atmel,pins =
319 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
320 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
321 };
323 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
324 atmel,pins =
325 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
326 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
327 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
328 };
330 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
331 atmel,pins =
332 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
333 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
334 };
336 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
337 atmel,pins =
338 <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
339 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
340 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
341 };
342 };
344 ssc0 {
345 pinctrl_ssc0_tx: ssc0_tx-0 {
346 atmel,pins =
347 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
348 AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
349 AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
350 };
352 pinctrl_ssc0_rx: ssc0_rx-0 {
353 atmel,pins =
354 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
355 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
356 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
357 };
358 };
360 ssc1 {
361 pinctrl_ssc1_tx: ssc1_tx-0 {
362 atmel,pins =
363 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
364 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
365 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
366 };
368 pinctrl_ssc1_rx: ssc1_rx-0 {
369 atmel,pins =
370 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
371 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
372 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
373 };
374 };
376 spi0 {
377 pinctrl_spi0: spi0-0 {
378 atmel,pins =
379 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
380 AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
381 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
382 };
383 };
385 spi1 {
386 pinctrl_spi1: spi1-0 {
387 atmel,pins =
388 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
389 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
390 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
391 };
392 };
394 tcb0 {
395 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
396 atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
397 };
399 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
400 atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
401 };
403 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
404 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
405 };
407 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
408 atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
409 };
411 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
412 atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
413 };
415 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
416 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
417 };
419 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
420 atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
421 };
423 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
424 atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
425 };
427 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
428 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
429 };
430 };
432 fb {
433 pinctrl_fb: fb-0 {
434 atmel,pins =
435 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
436 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
437 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
438 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
439 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
440 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
441 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
442 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
443 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
444 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
445 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
446 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
447 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
448 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
449 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
450 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
451 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
452 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
453 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
454 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
455 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
456 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
457 };
458 };
460 can {
461 pinctrl_can_rx_tx: can_rx_tx {
462 atmel,pins =
463 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */
464 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
465 };
466 };
468 ac97 {
469 pinctrl_ac97: ac97-0 {
470 atmel,pins =
471 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
472 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */
473 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */
474 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */
475 };
476 };
478 pioA: gpio@fffff200 {
479 compatible = "atmel,at91rm9200-gpio";
480 reg = <0xfffff200 0x200>;
481 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
482 #gpio-cells = <2>;
483 gpio-controller;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
487 };
489 pioB: gpio@fffff400 {
490 compatible = "atmel,at91rm9200-gpio";
491 reg = <0xfffff400 0x200>;
492 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
493 #gpio-cells = <2>;
494 gpio-controller;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
498 };
500 pioC: gpio@fffff600 {
501 compatible = "atmel,at91rm9200-gpio";
502 reg = <0xfffff600 0x200>;
503 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
504 #gpio-cells = <2>;
505 gpio-controller;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
509 };
511 pioD: gpio@fffff800 {
512 compatible = "atmel,at91rm9200-gpio";
513 reg = <0xfffff800 0x200>;
514 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
515 #gpio-cells = <2>;
516 gpio-controller;
517 interrupt-controller;
518 #interrupt-cells = <2>;
519 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
520 };
522 pioE: gpio@fffffa00 {
523 compatible = "atmel,at91rm9200-gpio";
524 reg = <0xfffffa00 0x200>;
525 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
526 #gpio-cells = <2>;
527 gpio-controller;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
531 };
532 };
534 dbgu: serial@ffffee00 {
535 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
536 reg = <0xffffee00 0x200>;
537 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_dbgu>;
540 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
541 clock-names = "usart";
542 status = "disabled";
543 };
545 usart0: serial@fff8c000 {
546 compatible = "atmel,at91sam9260-usart";
547 reg = <0xfff8c000 0x200>;
548 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
549 atmel,use-dma-rx;
550 atmel,use-dma-tx;
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_usart0>;
553 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
554 clock-names = "usart";
555 status = "disabled";
556 };
558 usart1: serial@fff90000 {
559 compatible = "atmel,at91sam9260-usart";
560 reg = <0xfff90000 0x200>;
561 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
562 atmel,use-dma-rx;
563 atmel,use-dma-tx;
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_usart1>;
566 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
567 clock-names = "usart";
568 status = "disabled";
569 };
571 usart2: serial@fff94000 {
572 compatible = "atmel,at91sam9260-usart";
573 reg = <0xfff94000 0x200>;
574 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
575 atmel,use-dma-rx;
576 atmel,use-dma-tx;
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_usart2>;
579 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
580 clock-names = "usart";
581 status = "disabled";
582 };
584 ssc0: ssc@fff98000 {
585 compatible = "atmel,at91rm9200-ssc";
586 reg = <0xfff98000 0x4000>;
587 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
590 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
591 clock-names = "pclk";
592 status = "disabled";
593 };
595 ssc1: ssc@fff9c000 {
596 compatible = "atmel,at91rm9200-ssc";
597 reg = <0xfff9c000 0x4000>;
598 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
601 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
602 clock-names = "pclk";
603 status = "disabled";
604 };
606 ac97: sound@fffa0000 {
607 compatible = "atmel,at91sam9263-ac97c";
608 reg = <0xfffa0000 0x4000>;
609 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_ac97>;
612 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
613 clock-names = "ac97_clk";
614 status = "disabled";
615 };
617 macb0: ethernet@fffbc000 {
618 compatible = "cdns,at91sam9260-macb", "cdns,macb";
619 reg = <0xfffbc000 0x100>;
620 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_macb_rmii>;
623 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
624 clock-names = "hclk", "pclk";
625 status = "disabled";
626 };
628 usb1: gadget@fff78000 {
629 compatible = "atmel,at91sam9263-udc";
630 reg = <0xfff78000 0x4000>;
631 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
632 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>;
633 clock-names = "pclk", "hclk";
634 status = "disabled";
635 };
637 i2c0: i2c@fff88000 {
638 compatible = "atmel,at91sam9260-i2c";
639 reg = <0xfff88000 0x100>;
640 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
644 status = "disabled";
645 };
647 mmc0: mmc@fff80000 {
648 compatible = "atmel,hsmci";
649 reg = <0xfff80000 0x600>;
650 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
651 pinctrl-names = "default";
652 #address-cells = <1>;
653 #size-cells = <0>;
654 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
655 clock-names = "mci_clk";
656 status = "disabled";
657 };
659 mmc1: mmc@fff84000 {
660 compatible = "atmel,hsmci";
661 reg = <0xfff84000 0x600>;
662 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
663 pinctrl-names = "default";
664 #address-cells = <1>;
665 #size-cells = <0>;
666 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
667 clock-names = "mci_clk";
668 status = "disabled";
669 };
671 watchdog@fffffd40 {
672 compatible = "atmel,at91sam9260-wdt";
673 reg = <0xfffffd40 0x10>;
674 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
675 clocks = <&slow_xtal>;
676 atmel,watchdog-type = "hardware";
677 atmel,reset-type = "all";
678 atmel,dbg-halt;
679 status = "disabled";
680 };
682 spi0: spi@fffa4000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "atmel,at91rm9200-spi";
686 reg = <0xfffa4000 0x200>;
687 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pinctrl_spi0>;
690 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
691 clock-names = "spi_clk";
692 status = "disabled";
693 };
695 spi1: spi@fffa8000 {
696 #address-cells = <1>;
697 #size-cells = <0>;
698 compatible = "atmel,at91rm9200-spi";
699 reg = <0xfffa8000 0x200>;
700 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&pinctrl_spi1>;
703 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
704 clock-names = "spi_clk";
705 status = "disabled";
706 };
708 pwm0: pwm@fffb8000 {
709 compatible = "atmel,at91sam9rl-pwm";
710 reg = <0xfffb8000 0x300>;
711 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
712 #pwm-cells = <3>;
713 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
714 clock-names = "pwm_clk";
715 status = "disabled";
716 };
718 can: can@fffac000 {
719 compatible = "atmel,at91sam9263-can";
720 reg = <0xfffac000 0x300>;
721 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_can_rx_tx>;
724 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
725 clock-names = "can_clk";
726 };
728 rtc@fffffd20 {
729 compatible = "atmel,at91sam9260-rtt";
730 reg = <0xfffffd20 0x10>;
731 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
732 clocks = <&slow_xtal>;
733 status = "disabled";
734 };
736 rtc@fffffd50 {
737 compatible = "atmel,at91sam9260-rtt";
738 reg = <0xfffffd50 0x10>;
739 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
740 clocks = <&slow_xtal>;
741 status = "disabled";
742 };
744 gpbr: syscon@fffffd60 {
745 compatible = "atmel,at91sam9260-gpbr", "syscon";
746 reg = <0xfffffd60 0x50>;
747 status = "disabled";
748 };
749 };
751 fb0: fb@700000 {
752 compatible = "atmel,at91sam9263-lcdc";
753 reg = <0x00700000 0x1000>;
754 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&pinctrl_fb>;
757 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>;
758 clock-names = "lcdc_clk", "hclk";
759 status = "disabled";
760 };
762 usb0: ohci@a00000 {
763 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
764 reg = <0x00a00000 0x100000>;
765 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
766 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>;
767 clock-names = "ohci_clk", "hclk", "uhpck";
768 status = "disabled";
769 };
771 ebi0: ebi@10000000 {
772 compatible = "atmel,at91sam9263-ebi0";
773 #address-cells = <2>;
774 #size-cells = <1>;
775 atmel,smc = <&smc0>;
776 atmel,matrix = <&matrix>;
777 reg = <0x10000000 0x80000000>;
778 ranges = <0x0 0x0 0x10000000 0x10000000
779 0x1 0x0 0x20000000 0x10000000
780 0x2 0x0 0x30000000 0x10000000
781 0x3 0x0 0x40000000 0x10000000
782 0x4 0x0 0x50000000 0x10000000
783 0x5 0x0 0x60000000 0x10000000>;
784 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
785 status = "disabled";
787 nand_controller0: nand-controller {
788 compatible = "atmel,at91sam9260-nand-controller";
789 #address-cells = <2>;
790 #size-cells = <1>;
791 ranges;
792 status = "disabled";
793 };
794 };
796 ebi1: ebi@70000000 {
797 compatible = "atmel,at91sam9263-ebi1";
798 #address-cells = <2>;
799 #size-cells = <1>;
800 atmel,smc = <&smc1>;
801 atmel,matrix = <&matrix>;
802 reg = <0x80000000 0x20000000>;
803 ranges = <0x0 0x0 0x80000000 0x10000000
804 0x1 0x0 0x90000000 0x10000000>;
805 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
806 status = "disabled";
808 nand_controller1: nand-controller {
809 compatible = "atmel,at91sam9260-nand-controller";
810 #address-cells = <2>;
811 #size-cells = <1>;
812 ranges;
813 status = "disabled";
814 };
815 };
816 };
818 i2c-gpio-0 {
819 compatible = "i2c-gpio";
820 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
821 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
822 >;
823 i2c-gpio,sda-open-drain;
824 i2c-gpio,scl-open-drain;
825 i2c-gpio,delay-us = <2>; /* ~100 kHz */
826 #address-cells = <1>;
827 #size-cells = <0>;
828 status = "disabled";
829 };
830 };