| blob | 6925b30c22539d9bb24d931cb81df0ed818e8f28 |
1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 / {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
44 aliases {
45 serial0 = &uart0;
46 serial1 = &uart1;
47 ethernet0 = &amac0;
48 ethernet1 = &amac1;
49 ethernet2 = &amac2;
50 };
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
60 reg = <0x0>;
61 };
63 cpu1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a9";
66 next-level-cache = <&L2>;
67 enable-method = "brcm,bcm-nsp-smp";
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
70 };
71 };
73 pmu {
74 compatible = "arm,cortex-a9-pmu";
75 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
76 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-affinity = <&cpu0>, <&cpu1>;
78 };
80 mpcore {
81 compatible = "simple-bus";
82 ranges = <0x00000000 0x19000000 0x00023000>;
83 #address-cells = <1>;
84 #size-cells = <1>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
88 compatible = "brcm,nsp-armpll";
89 clocks = <&osc>;
90 reg = <0x00000 0x1000>;
91 };
93 timer@20200 {
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0x20200 0x100>;
96 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
97 clocks = <&periph_clk>;
98 };
100 twd-timer@20600 {
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0x20600 0x20>;
103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_EDGE_RISING)>;
105 clocks = <&periph_clk>;
106 };
108 twd-watchdog@20620 {
109 compatible = "arm,cortex-a9-twd-wdt";
110 reg = <0x20620 0x20>;
111 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
112 IRQ_TYPE_LEVEL_HIGH)>;
113 clocks = <&periph_clk>;
114 };
116 gic: interrupt-controller@21000 {
117 compatible = "arm,cortex-a9-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <0>;
120 interrupt-controller;
121 reg = <0x21000 0x1000>,
122 <0x20100 0x100>;
123 };
125 L2: l2-cache {
126 compatible = "arm,pl310-cache";
127 reg = <0x22000 0x1000>;
128 cache-unified;
129 cache-level = <2>;
130 };
131 };
133 clocks {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges;
138 osc: oscillator {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-frequency = <25000000>;
142 };
144 iprocmed: iprocmed {
145 #clock-cells = <0>;
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
148 clock-div = <2>;
149 clock-mult = <1>;
150 };
152 iprocslow: iprocslow {
153 #clock-cells = <0>;
154 compatible = "fixed-factor-clock";
155 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
156 clock-div = <4>;
157 clock-mult = <1>;
158 };
160 periph_clk: periph_clk {
161 #clock-cells = <0>;
162 compatible = "fixed-factor-clock";
163 clocks = <&a9pll>;
164 clock-div = <2>;
165 clock-mult = <1>;
166 };
167 };
169 axi {
170 compatible = "simple-bus";
171 ranges = <0x00000000 0x18000000 0x0011c40c>;
172 #address-cells = <1>;
173 #size-cells = <1>;
175 gpioa: gpio@20 {
176 compatible = "brcm,nsp-gpio-a";
177 reg = <0x0020 0x70>,
178 <0x3f1c4 0x1c>;
179 #gpio-cells = <2>;
180 gpio-controller;
181 ngpios = <32>;
182 interrupt-controller;
183 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
184 gpio-ranges = <&pinctrl 0 0 32>;
185 };
187 uart0: serial@300 {
188 compatible = "ns16550a";
189 reg = <0x0300 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&osc>;
192 status = "disabled";
193 };
195 uart1: serial@400 {
196 compatible = "ns16550a";
197 reg = <0x0400 0x100>;
198 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&osc>;
200 status = "disabled";
201 };
203 dma@20000 {
204 compatible = "arm,pl330", "arm,primecell";
205 reg = <0x20000 0x1000>;
206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&iprocslow>;
216 clock-names = "apb_pclk";
217 #dma-cells = <1>;
218 };
220 sdio: sdhci@21000 {
221 compatible = "brcm,sdhci-iproc-cygnus";
222 reg = <0x21000 0x100>;
223 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
224 sdhci,auto-cmd12;
225 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
226 dma-coherent;
227 status = "disabled";
228 };
230 amac0: ethernet@22000 {
231 compatible = "brcm,nsp-amac";
232 reg = <0x022000 0x1000>,
233 <0x110000 0x1000>;
234 reg-names = "amac_base", "idm_base";
235 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
236 dma-coherent;
237 status = "disabled";
238 };
240 amac1: ethernet@23000 {
241 compatible = "brcm,nsp-amac";
242 reg = <0x023000 0x1000>,
243 <0x111000 0x1000>;
244 reg-names = "amac_base", "idm_base";
245 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
246 dma-coherent;
247 status = "disabled";
248 };
250 amac2: ethernet@24000 {
251 compatible = "brcm,nsp-amac";
252 reg = <0x024000 0x1000>,
253 <0x112000 0x1000>;
254 reg-names = "amac_base", "idm_base";
255 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
256 dma-coherent;
257 status = "disabled";
258 };
260 mailbox: mailbox@25000 {
261 compatible = "brcm,iproc-fa2-mbox";
262 reg = <0x25000 0x445>;
263 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
264 #mbox-cells = <1>;
265 brcm,rx-status-len = <32>;
266 brcm,use-bcm-hdr;
267 dma-coherent;
268 };
270 nand: nand@26000 {
271 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
272 reg = <0x026000 0x600>,
273 <0x11b408 0x600>,
274 <0x026f00 0x20>;
275 reg-names = "nand", "iproc-idm", "iproc-ext";
276 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
278 #address-cells = <1>;
279 #size-cells = <0>;
281 brcm,nand-has-wp;
282 };
284 qspi: spi@27200 {
285 compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
286 reg = <0x027200 0x184>,
287 <0x027000 0x124>,
288 <0x11c408 0x004>,
289 <0x0273a0 0x01c>;
290 reg-names = "mspi", "bspi", "intr_regs",
291 "intr_status_reg";
292 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
299 interrupt-names = "spi_lr_fullness_reached",
300 "spi_lr_session_aborted",
301 "spi_lr_impatient",
302 "spi_lr_session_done",
303 "spi_lr_overhead",
304 "mspi_done",
305 "mspi_halted";
306 clocks = <&iprocmed>;
307 clock-names = "iprocmed";
308 num-cs = <2>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 };
313 xhci: usb@29000 {
314 compatible = "generic-xhci";
315 reg = <0x29000 0x1000>;
316 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
317 phys = <&usb3_phy>;
318 phy-names = "usb3-phy";
319 dma-coherent;
320 status = "disabled";
321 };
323 ehci0: usb@2a000 {
324 compatible = "generic-ehci";
325 reg = <0x2a000 0x100>;
326 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
327 dma-coherent;
328 status = "disabled";
329 };
331 ohci0: usb@2b000 {
332 compatible = "generic-ohci";
333 reg = <0x2b000 0x100>;
334 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
335 dma-coherent;
336 status = "disabled";
337 };
339 crypto@2f000 {
340 compatible = "brcm,spum-nsp-crypto";
341 reg = <0x2f000 0x900>;
342 mboxes = <&mailbox 0>;
343 };
345 gpiob: gpio@30000 {
346 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
347 reg = <0x30000 0x50>;
348 #gpio-cells = <2>;
349 gpio-controller;
350 ngpios = <4>;
351 interrupt-controller;
352 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
353 };
355 pwm: pwm@31000 {
356 compatible = "brcm,iproc-pwm";
357 reg = <0x31000 0x28>;
358 clocks = <&osc>;
359 #pwm-cells = <3>;
360 status = "disabled";
361 };
363 rng: rng@33000 {
364 compatible = "brcm,bcm-nsp-rng";
365 reg = <0x33000 0x14>;
366 };
368 ccbtimer0: timer@34000 {
369 compatible = "arm,sp804";
370 reg = <0x34000 0x1000>;
371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&iprocslow>;
374 clock-names = "apb_pclk";
375 };
377 ccbtimer1: timer@35000 {
378 compatible = "arm,sp804";
379 reg = <0x35000 0x1000>;
380 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&iprocslow>;
383 clock-names = "apb_pclk";
384 };
386 srab: srab@36000 {
387 compatible = "brcm,nsp-srab";
388 reg = <0x36000 0x1000>,
389 <0x3f308 0x8>,
390 <0x3f410 0xc>;
391 reg-names = "srab", "mux_config", "sgmii";
392 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-names = "link_state_p0",
406 "link_state_p1",
407 "link_state_p2",
408 "link_state_p3",
409 "link_state_p4",
410 "link_state_p5",
411 "link_state_p7",
412 "link_state_p8",
413 "phy",
414 "ts",
415 "imp_sleep_timer_p5",
416 "imp_sleep_timer_p7",
417 "imp_sleep_timer_p8";
418 #address-cells = <1>;
419 #size-cells = <0>;
421 status = "disabled";
423 /* ports are defined in board DTS */
424 };
426 i2c0: i2c@38000 {
427 compatible = "brcm,iproc-i2c";
428 reg = <0x38000 0x50>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
432 clock-frequency = <100000>;
433 dma-coherent;
434 status = "disabled";
435 };
437 watchdog@39000 {
438 compatible = "arm,sp805", "arm,primecell";
439 reg = <0x39000 0x1000>;
440 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&iprocslow>, <&iprocslow>;
442 clock-names = "wdogclk", "apb_pclk";
443 };
445 lcpll0: lcpll0@3f100 {
446 #clock-cells = <1>;
447 compatible = "brcm,nsp-lcpll0";
448 reg = <0x3f100 0x14>;
449 clocks = <&osc>;
450 clock-output-names = "lcpll0", "pcie_phy", "sdio",
451 "ddr_phy";
452 };
454 genpll: genpll@3f140 {
455 #clock-cells = <1>;
456 compatible = "brcm,nsp-genpll";
457 reg = <0x3f140 0x24>;
458 clocks = <&osc>;
459 clock-output-names = "genpll", "phy", "ethernetclk",
460 "usbclk", "iprocfast", "sata1",
461 "sata2";
462 };
464 pinctrl: pinctrl@3f1c0 {
465 compatible = "brcm,nsp-pinmux";
466 reg = <0x3f1c0 0x04>,
467 <0x30028 0x04>,
468 <0x3f408 0x04>;
469 };
471 thermal: thermal@3f2c0 {
472 compatible = "brcm,ns-thermal";
473 reg = <0x3f2c0 0x10>;
474 #thermal-sensor-cells = <0>;
475 };
477 sata_phy: sata_phy@40100 {
478 compatible = "brcm,iproc-nsp-sata-phy";
479 reg = <0x40100 0x340>;
480 reg-names = "phy";
481 #address-cells = <1>;
482 #size-cells = <0>;
484 sata_phy0: sata-phy@0 {
485 reg = <0>;
486 #phy-cells = <0>;
487 status = "disabled";
488 };
490 sata_phy1: sata-phy@1 {
491 reg = <1>;
492 #phy-cells = <0>;
493 status = "disabled";
494 };
495 };
497 sata: ahci@41000 {
498 compatible = "brcm,bcm-nsp-ahci";
499 reg-names = "ahci", "top-ctrl";
500 reg = <0x41000 0x1000>, <0x40020 0x1c>;
501 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
502 #address-cells = <1>;
503 #size-cells = <0>;
504 dma-coherent;
505 status = "disabled";
507 sata0: sata-port@0 {
508 reg = <0>;
509 phys = <&sata_phy0>;
510 phy-names = "sata-phy";
511 };
513 sata1: sata-port@1 {
514 reg = <1>;
515 phys = <&sata_phy1>;
516 phy-names = "sata-phy";
517 };
518 };
520 usb3_phy: usb3-phy@104000 {
521 compatible = "brcm,ns-bx-usb3-phy";
522 reg = <0x104000 0x1000>,
523 <0x032000 0x1000>;
524 reg-names = "dmp", "ccb-mii";
525 #phy-cells = <0>;
526 status = "disabled";
527 };
528 };
530 pcie0: pcie@18012000 {
531 compatible = "brcm,iproc-pcie";
532 reg = <0x18012000 0x1000>;
534 #interrupt-cells = <1>;
535 interrupt-map-mask = <0 0 0 0>;
536 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
538 linux,pci-domain = <0>;
540 bus-range = <0x00 0xff>;
542 #address-cells = <3>;
543 #size-cells = <2>;
544 device_type = "pci";
546 /* Note: The HW does not support I/O resources. So,
547 * only the memory resource range is being specified.
548 */
549 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
551 dma-coherent;
552 status = "disabled";
554 msi-parent = <&msi0>;
555 msi0: msi-controller {
556 compatible = "brcm,iproc-msi";
557 msi-controller;
558 interrupt-parent = <&gic>;
559 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
563 brcm,pcie-msi-inten;
564 };
565 };
567 pcie1: pcie@18013000 {
568 compatible = "brcm,iproc-pcie";
569 reg = <0x18013000 0x1000>;
571 #interrupt-cells = <1>;
572 interrupt-map-mask = <0 0 0 0>;
573 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
575 linux,pci-domain = <1>;
577 bus-range = <0x00 0xff>;
579 #address-cells = <3>;
580 #size-cells = <2>;
581 device_type = "pci";
583 /* Note: The HW does not support I/O resources. So,
584 * only the memory resource range is being specified.
585 */
586 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
588 dma-coherent;
589 status = "disabled";
591 msi-parent = <&msi1>;
592 msi1: msi-controller {
593 compatible = "brcm,iproc-msi";
594 msi-controller;
595 interrupt-parent = <&gic>;
596 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
600 brcm,pcie-msi-inten;
601 };
602 };
604 pcie2: pcie@18014000 {
605 compatible = "brcm,iproc-pcie";
606 reg = <0x18014000 0x1000>;
608 #interrupt-cells = <1>;
609 interrupt-map-mask = <0 0 0 0>;
610 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
612 linux,pci-domain = <2>;
614 bus-range = <0x00 0xff>;
616 #address-cells = <3>;
617 #size-cells = <2>;
618 device_type = "pci";
620 /* Note: The HW does not support I/O resources. So,
621 * only the memory resource range is being specified.
622 */
623 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
625 dma-coherent;
626 status = "disabled";
628 msi-parent = <&msi2>;
629 msi2: msi-controller {
630 compatible = "brcm,iproc-msi";
631 msi-controller;
632 interrupt-parent = <&gic>;
633 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
637 brcm,pcie-msi-inten;
638 };
639 };
641 thermal-zones {
642 cpu-thermal {
643 polling-delay-passive = <0>;
644 polling-delay = <1000>;
645 coefficients = <(-556) 418000>;
646 thermal-sensors = <&thermal>;
648 trips {
649 cpu-crit {
650 temperature = <125000>;
651 hysteresis = <0>;
652 type = "critical";
653 };
654 };
656 cooling-maps {
657 };
658 };
659 };
660 };