arch/arm/boot/dts/bcm2837.dtsi

   1 #include "bcm283x.dtsi"
   2
   3 / {
   4         compatible = "brcm,bcm2837";
   5
   6         soc {
   7                 ranges = <0x7e000000 0x3f000000 0x1000000>,
   8                          <0x40000000 0x40000000 0x00001000>;
   9                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
  10
  11                 local_intc: local_intc@40000000 {
  12                         compatible = "brcm,bcm2836-l1-intc";
  13                         reg = <0x40000000 0x100>;
  14                         interrupt-controller;
  15                         #interrupt-cells = <2>;
  16                         interrupt-parent = <&local_intc>;
  17                 };
  18         };
  19
  20         arm-pmu {
  21                 compatible = "arm,cortex-a53-pmu";
  22                 interrupt-parent = <&local_intc>;
  23                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  24         };
  25
  26         timer {
  27                 compatible = "arm,armv7-timer";
  28                 interrupt-parent = <&local_intc>;
  29                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
  30                              <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
  31                              <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
  32                              <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
  33                 always-on;
  34         };
  35
  36         cpus: cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0>;
  45                         enable-method = "spin-table";
  46                         cpu-release-addr = <0x0 0x000000d8>;
  47                 };
  48
  49                 cpu1: cpu@1 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a53";
  52                         reg = <1>;
  53                         enable-method = "spin-table";
  54                         cpu-release-addr = <0x0 0x000000e0>;
  55                 };
  56
  57                 cpu2: cpu@2 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53";
  60                         reg = <2>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x0 0x000000e8>;
  63                 };
  64
  65                 cpu3: cpu@3 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <3>;
  69                         enable-method = "spin-table";
  70                         cpu-release-addr = <0x0 0x000000f0>;
  71                 };
  72         };
  73 };
  74
  75 /* Make the BCM2835-style global interrupt controller be a child of the
  76  * CPU-local interrupt controller.
  77  */
  78 &intc {
  79         compatible = "brcm,bcm2836-armctrl-ic";
  80         reg = <0x7e00b200 0x200>;
  81         interrupt-parent = <&local_intc>;
  82         interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  83 };
  84
  85 &cpu_thermal {
  86         coefficients = <(-538)  412000>;
  87 };
  88
  89 /* enable thermal sensor with the correct compatible property set */
  90 &thermal {
  91         compatible = "brcm,bcm2837-thermal";
  92         status = "okay";
  93 };