arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for DRA7xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         atl_clkin0_ck: atl_clkin0_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,dra7-atl-clock";
  14                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  15         };
  16
  17         atl_clkin1_ck: atl_clkin1_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,dra7-atl-clock";
  20                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  21         };
  22
  23         atl_clkin2_ck: atl_clkin2_ck {
  24                 #clock-cells = <0>;
  25                 compatible = "ti,dra7-atl-clock";
  26                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  27         };
  28
  29         atl_clkin3_ck: atl_clkin3_ck {
  30                 #clock-cells = <0>;
  31                 compatible = "ti,dra7-atl-clock";
  32                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  33         };
  34
  35         hdmi_clkin_ck: hdmi_clkin_ck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <0>;
  39         };
  40
  41         mlb_clkin_ck: mlb_clkin_ck {
  42                 #clock-cells = <0>;
  43                 compatible = "fixed-clock";
  44                 clock-frequency = <0>;
  45         };
  46
  47         mlbp_clkin_ck: mlbp_clkin_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-clock";
  50                 clock-frequency = <0>;
  51         };
  52
  53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <100000000>;
  57         };
  58
  59         ref_clkin0_ck: ref_clkin0_ck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <0>;
  63         };
  64
  65         ref_clkin1_ck: ref_clkin1_ck {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <0>;
  69         };
  70
  71         ref_clkin2_ck: ref_clkin2_ck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <0>;
  75         };
  76
  77         ref_clkin3_ck: ref_clkin3_ck {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         rmii_clk_ck: rmii_clk_ck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <0>;
  87         };
  88
  89         sdvenc_clkin_ck: sdvenc_clkin_ck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <0>;
  93         };
  94
  95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99         };
 100
 101         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-clock";
 104                 clock-frequency = <32768>;
 105         };
 106
 107         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-factor-clock";
 110                 clocks = <&sys_clkin1>;
 111                 clock-mult = <1>;
 112                 clock-div = <610>;
 113         };
 114
 115         virt_12000000_ck: virt_12000000_ck {
 116                 #clock-cells = <0>;
 117                 compatible = "fixed-clock";
 118                 clock-frequency = <12000000>;
 119         };
 120
 121         virt_13000000_ck: virt_13000000_ck {
 122                 #clock-cells = <0>;
 123                 compatible = "fixed-clock";
 124                 clock-frequency = <13000000>;
 125         };
 126
 127         virt_16800000_ck: virt_16800000_ck {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-clock";
 130                 clock-frequency = <16800000>;
 131         };
 132
 133         virt_19200000_ck: virt_19200000_ck {
 134                 #clock-cells = <0>;
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <19200000>;
 137         };
 138
 139         virt_20000000_ck: virt_20000000_ck {
 140                 #clock-cells = <0>;
 141                 compatible = "fixed-clock";
 142                 clock-frequency = <20000000>;
 143         };
 144
 145         virt_26000000_ck: virt_26000000_ck {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-clock";
 148                 clock-frequency = <26000000>;
 149         };
 150
 151         virt_27000000_ck: virt_27000000_ck {
 152                 #clock-cells = <0>;
 153                 compatible = "fixed-clock";
 154                 clock-frequency = <27000000>;
 155         };
 156
 157         virt_38400000_ck: virt_38400000_ck {
 158                 #clock-cells = <0>;
 159                 compatible = "fixed-clock";
 160                 clock-frequency = <38400000>;
 161         };
 162
 163         sys_clkin2: sys_clkin2 {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-clock";
 166                 clock-frequency = <22579200>;
 167         };
 168
 169         usb_otg_clkin_ck: usb_otg_clkin_ck {
 170                 #clock-cells = <0>;
 171                 compatible = "fixed-clock";
 172                 clock-frequency = <0>;
 173         };
 174
 175         video1_clkin_ck: video1_clkin_ck {
 176                 #clock-cells = <0>;
 177                 compatible = "fixed-clock";
 178                 clock-frequency = <0>;
 179         };
 180
 181         video1_m2_clkin_ck: video1_m2_clkin_ck {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-clock";
 184                 clock-frequency = <0>;
 185         };
 186
 187         video2_clkin_ck: video2_clkin_ck {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-frequency = <0>;
 191         };
 192
 193         video2_m2_clkin_ck: video2_m2_clkin_ck {
 194                 #clock-cells = <0>;
 195                 compatible = "fixed-clock";
 196                 clock-frequency = <0>;
 197         };
 198
 199         dpll_abe_ck: dpll_abe_ck@1e0 {
 200                 #clock-cells = <0>;
 201                 compatible = "ti,omap4-dpll-m4xen-clock";
 202                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 203                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 204         };
 205
 206         dpll_abe_x2_ck: dpll_abe_x2_ck {
 207                 #clock-cells = <0>;
 208                 compatible = "ti,omap4-dpll-x2-clock";
 209                 clocks = <&dpll_abe_ck>;
 210         };
 211
 212         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 213                 #clock-cells = <0>;
 214                 compatible = "ti,divider-clock";
 215                 clocks = <&dpll_abe_x2_ck>;
 216                 ti,max-div = <31>;
 217                 ti,autoidle-shift = <8>;
 218                 reg = <0x01f0>;
 219                 ti,index-starts-at-one;
 220                 ti,invert-autoidle-bit;
 221         };
 222
 223         abe_clk: abe_clk@108 {
 224                 #clock-cells = <0>;
 225                 compatible = "ti,divider-clock";
 226                 clocks = <&dpll_abe_m2x2_ck>;
 227                 ti,max-div = <4>;
 228                 reg = <0x0108>;
 229                 ti,index-power-of-two;
 230         };
 231
 232         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 233                 #clock-cells = <0>;
 234                 compatible = "ti,divider-clock";
 235                 clocks = <&dpll_abe_ck>;
 236                 ti,max-div = <31>;
 237                 ti,autoidle-shift = <8>;
 238                 reg = <0x01f0>;
 239                 ti,index-starts-at-one;
 240                 ti,invert-autoidle-bit;
 241         };
 242
 243         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,divider-clock";
 246                 clocks = <&dpll_abe_x2_ck>;
 247                 ti,max-div = <31>;
 248                 ti,autoidle-shift = <8>;
 249                 reg = <0x01f4>;
 250                 ti,index-starts-at-one;
 251                 ti,invert-autoidle-bit;
 252         };
 253
 254         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 255                 #clock-cells = <0>;
 256                 compatible = "ti,mux-clock";
 257                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 258                 ti,bit-shift = <23>;
 259                 reg = <0x012c>;
 260         };
 261
 262         dpll_core_ck: dpll_core_ck@120 {
 263                 #clock-cells = <0>;
 264                 compatible = "ti,omap4-dpll-core-clock";
 265                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 266                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 267         };
 268
 269         dpll_core_x2_ck: dpll_core_x2_ck {
 270                 #clock-cells = <0>;
 271                 compatible = "ti,omap4-dpll-x2-clock";
 272                 clocks = <&dpll_core_ck>;
 273         };
 274
 275         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 276                 #clock-cells = <0>;
 277                 compatible = "ti,divider-clock";
 278                 clocks = <&dpll_core_x2_ck>;
 279                 ti,max-div = <63>;
 280                 ti,autoidle-shift = <8>;
 281                 reg = <0x013c>;
 282                 ti,index-starts-at-one;
 283                 ti,invert-autoidle-bit;
 284         };
 285
 286         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 287                 #clock-cells = <0>;
 288                 compatible = "fixed-factor-clock";
 289                 clocks = <&dpll_core_h12x2_ck>;
 290                 clock-mult = <1>;
 291                 clock-div = <1>;
 292         };
 293
 294         dpll_mpu_ck: dpll_mpu_ck@160 {
 295                 #clock-cells = <0>;
 296                 compatible = "ti,omap5-mpu-dpll-clock";
 297                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 298                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 299         };
 300
 301         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 302                 #clock-cells = <0>;
 303                 compatible = "ti,divider-clock";
 304                 clocks = <&dpll_mpu_ck>;
 305                 ti,max-div = <31>;
 306                 ti,autoidle-shift = <8>;
 307                 reg = <0x0170>;
 308                 ti,index-starts-at-one;
 309                 ti,invert-autoidle-bit;
 310         };
 311
 312         mpu_dclk_div: mpu_dclk_div {
 313                 #clock-cells = <0>;
 314                 compatible = "fixed-factor-clock";
 315                 clocks = <&dpll_mpu_m2_ck>;
 316                 clock-mult = <1>;
 317                 clock-div = <1>;
 318         };
 319
 320         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 321                 #clock-cells = <0>;
 322                 compatible = "fixed-factor-clock";
 323                 clocks = <&dpll_core_h12x2_ck>;
 324                 clock-mult = <1>;
 325                 clock-div = <1>;
 326         };
 327
 328         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 329                 #clock-cells = <0>;
 330                 compatible = "ti,mux-clock";
 331                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 332                 ti,bit-shift = <23>;
 333                 reg = <0x0240>;
 334         };
 335
 336         dpll_dsp_ck: dpll_dsp_ck@234 {
 337                 #clock-cells = <0>;
 338                 compatible = "ti,omap4-dpll-clock";
 339                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 340                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 341                 assigned-clocks = <&dpll_dsp_ck>;
 342                 assigned-clock-rates = <600000000>;
 343         };
 344
 345         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 346                 #clock-cells = <0>;
 347                 compatible = "ti,divider-clock";
 348                 clocks = <&dpll_dsp_ck>;
 349                 ti,max-div = <31>;
 350                 ti,autoidle-shift = <8>;
 351                 reg = <0x0244>;
 352                 ti,index-starts-at-one;
 353                 ti,invert-autoidle-bit;
 354                 assigned-clocks = <&dpll_dsp_m2_ck>;
 355                 assigned-clock-rates = <600000000>;
 356         };
 357
 358         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 359                 #clock-cells = <0>;
 360                 compatible = "fixed-factor-clock";
 361                 clocks = <&dpll_core_h12x2_ck>;
 362                 clock-mult = <1>;
 363                 clock-div = <1>;
 364         };
 365
 366         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 367                 #clock-cells = <0>;
 368                 compatible = "ti,mux-clock";
 369                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 370                 ti,bit-shift = <23>;
 371                 reg = <0x01ac>;
 372         };
 373
 374         dpll_iva_ck: dpll_iva_ck@1a0 {
 375                 #clock-cells = <0>;
 376                 compatible = "ti,omap4-dpll-clock";
 377                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 378                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 379                 assigned-clocks = <&dpll_iva_ck>;
 380                 assigned-clock-rates = <1165000000>;
 381         };
 382
 383         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 384                 #clock-cells = <0>;
 385                 compatible = "ti,divider-clock";
 386                 clocks = <&dpll_iva_ck>;
 387                 ti,max-div = <31>;
 388                 ti,autoidle-shift = <8>;
 389                 reg = <0x01b0>;
 390                 ti,index-starts-at-one;
 391                 ti,invert-autoidle-bit;
 392                 assigned-clocks = <&dpll_iva_m2_ck>;
 393                 assigned-clock-rates = <388333334>;
 394         };
 395
 396         iva_dclk: iva_dclk {
 397                 #clock-cells = <0>;
 398                 compatible = "fixed-factor-clock";
 399                 clocks = <&dpll_iva_m2_ck>;
 400                 clock-mult = <1>;
 401                 clock-div = <1>;
 402         };
 403
 404         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 405                 #clock-cells = <0>;
 406                 compatible = "ti,mux-clock";
 407                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 408                 ti,bit-shift = <23>;
 409                 reg = <0x02e4>;
 410         };
 411
 412         dpll_gpu_ck: dpll_gpu_ck@2d8 {
 413                 #clock-cells = <0>;
 414                 compatible = "ti,omap4-dpll-clock";
 415                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 416                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 417                 assigned-clocks = <&dpll_gpu_ck>;
 418                 assigned-clock-rates = <1277000000>;
 419         };
 420
 421         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 422                 #clock-cells = <0>;
 423                 compatible = "ti,divider-clock";
 424                 clocks = <&dpll_gpu_ck>;
 425                 ti,max-div = <31>;
 426                 ti,autoidle-shift = <8>;
 427                 reg = <0x02e8>;
 428                 ti,index-starts-at-one;
 429                 ti,invert-autoidle-bit;
 430                 assigned-clocks = <&dpll_gpu_m2_ck>;
 431                 assigned-clock-rates = <425666667>;
 432         };
 433
 434         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 435                 #clock-cells = <0>;
 436                 compatible = "ti,divider-clock";
 437                 clocks = <&dpll_core_ck>;
 438                 ti,max-div = <31>;
 439                 ti,autoidle-shift = <8>;
 440                 reg = <0x0130>;
 441                 ti,index-starts-at-one;
 442                 ti,invert-autoidle-bit;
 443         };
 444
 445         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 446                 #clock-cells = <0>;
 447                 compatible = "fixed-factor-clock";
 448                 clocks = <&dpll_core_m2_ck>;
 449                 clock-mult = <1>;
 450                 clock-div = <1>;
 451         };
 452
 453         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 454                 #clock-cells = <0>;
 455                 compatible = "ti,mux-clock";
 456                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 457                 ti,bit-shift = <23>;
 458                 reg = <0x021c>;
 459         };
 460
 461         dpll_ddr_ck: dpll_ddr_ck@210 {
 462                 #clock-cells = <0>;
 463                 compatible = "ti,omap4-dpll-clock";
 464                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 465                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 466         };
 467
 468         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 469                 #clock-cells = <0>;
 470                 compatible = "ti,divider-clock";
 471                 clocks = <&dpll_ddr_ck>;
 472                 ti,max-div = <31>;
 473                 ti,autoidle-shift = <8>;
 474                 reg = <0x0220>;
 475                 ti,index-starts-at-one;
 476                 ti,invert-autoidle-bit;
 477         };
 478
 479         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 480                 #clock-cells = <0>;
 481                 compatible = "ti,mux-clock";
 482                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 483                 ti,bit-shift = <23>;
 484                 reg = <0x02b4>;
 485         };
 486
 487         dpll_gmac_ck: dpll_gmac_ck@2a8 {
 488                 #clock-cells = <0>;
 489                 compatible = "ti,omap4-dpll-clock";
 490                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 491                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 492         };
 493
 494         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 495                 #clock-cells = <0>;
 496                 compatible = "ti,divider-clock";
 497                 clocks = <&dpll_gmac_ck>;
 498                 ti,max-div = <31>;
 499                 ti,autoidle-shift = <8>;
 500                 reg = <0x02b8>;
 501                 ti,index-starts-at-one;
 502                 ti,invert-autoidle-bit;
 503         };
 504
 505         video2_dclk_div: video2_dclk_div {
 506                 #clock-cells = <0>;
 507                 compatible = "fixed-factor-clock";
 508                 clocks = <&video2_m2_clkin_ck>;
 509                 clock-mult = <1>;
 510                 clock-div = <1>;
 511         };
 512
 513         video1_dclk_div: video1_dclk_div {
 514                 #clock-cells = <0>;
 515                 compatible = "fixed-factor-clock";
 516                 clocks = <&video1_m2_clkin_ck>;
 517                 clock-mult = <1>;
 518                 clock-div = <1>;
 519         };
 520
 521         hdmi_dclk_div: hdmi_dclk_div {
 522                 #clock-cells = <0>;
 523                 compatible = "fixed-factor-clock";
 524                 clocks = <&hdmi_clkin_ck>;
 525                 clock-mult = <1>;
 526                 clock-div = <1>;
 527         };
 528
 529         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 530                 #clock-cells = <0>;
 531                 compatible = "fixed-factor-clock";
 532                 clocks = <&dpll_abe_m3x2_ck>;
 533                 clock-mult = <1>;
 534                 clock-div = <2>;
 535         };
 536
 537         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 538                 #clock-cells = <0>;
 539                 compatible = "fixed-factor-clock";
 540                 clocks = <&dpll_abe_m3x2_ck>;
 541                 clock-mult = <1>;
 542                 clock-div = <3>;
 543         };
 544
 545         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 546                 #clock-cells = <0>;
 547                 compatible = "fixed-factor-clock";
 548                 clocks = <&dpll_core_h12x2_ck>;
 549                 clock-mult = <1>;
 550                 clock-div = <1>;
 551         };
 552
 553         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 554                 #clock-cells = <0>;
 555                 compatible = "ti,mux-clock";
 556                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 557                 ti,bit-shift = <23>;
 558                 reg = <0x0290>;
 559         };
 560
 561         dpll_eve_ck: dpll_eve_ck@284 {
 562                 #clock-cells = <0>;
 563                 compatible = "ti,omap4-dpll-clock";
 564                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 565                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 566         };
 567
 568         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 569                 #clock-cells = <0>;
 570                 compatible = "ti,divider-clock";
 571                 clocks = <&dpll_eve_ck>;
 572                 ti,max-div = <31>;
 573                 ti,autoidle-shift = <8>;
 574                 reg = <0x0294>;
 575                 ti,index-starts-at-one;
 576                 ti,invert-autoidle-bit;
 577         };
 578
 579         eve_dclk_div: eve_dclk_div {
 580                 #clock-cells = <0>;
 581                 compatible = "fixed-factor-clock";
 582                 clocks = <&dpll_eve_m2_ck>;
 583                 clock-mult = <1>;
 584                 clock-div = <1>;
 585         };
 586
 587         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 588                 #clock-cells = <0>;
 589                 compatible = "ti,divider-clock";
 590                 clocks = <&dpll_core_x2_ck>;
 591                 ti,max-div = <63>;
 592                 ti,autoidle-shift = <8>;
 593                 reg = <0x0140>;
 594                 ti,index-starts-at-one;
 595                 ti,invert-autoidle-bit;
 596         };
 597
 598         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 599                 #clock-cells = <0>;
 600                 compatible = "ti,divider-clock";
 601                 clocks = <&dpll_core_x2_ck>;
 602                 ti,max-div = <63>;
 603                 ti,autoidle-shift = <8>;
 604                 reg = <0x0144>;
 605                 ti,index-starts-at-one;
 606                 ti,invert-autoidle-bit;
 607         };
 608
 609         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 610                 #clock-cells = <0>;
 611                 compatible = "ti,divider-clock";
 612                 clocks = <&dpll_core_x2_ck>;
 613                 ti,max-div = <63>;
 614                 ti,autoidle-shift = <8>;
 615                 reg = <0x0154>;
 616                 ti,index-starts-at-one;
 617                 ti,invert-autoidle-bit;
 618         };
 619
 620         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 621                 #clock-cells = <0>;
 622                 compatible = "ti,divider-clock";
 623                 clocks = <&dpll_core_x2_ck>;
 624                 ti,max-div = <63>;
 625                 ti,autoidle-shift = <8>;
 626                 reg = <0x0158>;
 627                 ti,index-starts-at-one;
 628                 ti,invert-autoidle-bit;
 629         };
 630
 631         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 632                 #clock-cells = <0>;
 633                 compatible = "ti,divider-clock";
 634                 clocks = <&dpll_core_x2_ck>;
 635                 ti,max-div = <63>;
 636                 ti,autoidle-shift = <8>;
 637                 reg = <0x015c>;
 638                 ti,index-starts-at-one;
 639                 ti,invert-autoidle-bit;
 640         };
 641
 642         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 643                 #clock-cells = <0>;
 644                 compatible = "ti,omap4-dpll-x2-clock";
 645                 clocks = <&dpll_ddr_ck>;
 646         };
 647
 648         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 649                 #clock-cells = <0>;
 650                 compatible = "ti,divider-clock";
 651                 clocks = <&dpll_ddr_x2_ck>;
 652                 ti,max-div = <63>;
 653                 ti,autoidle-shift = <8>;
 654                 reg = <0x0228>;
 655                 ti,index-starts-at-one;
 656                 ti,invert-autoidle-bit;
 657         };
 658
 659         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 660                 #clock-cells = <0>;
 661                 compatible = "ti,omap4-dpll-x2-clock";
 662                 clocks = <&dpll_dsp_ck>;
 663         };
 664
 665         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 666                 #clock-cells = <0>;
 667                 compatible = "ti,divider-clock";
 668                 clocks = <&dpll_dsp_x2_ck>;
 669                 ti,max-div = <31>;
 670                 ti,autoidle-shift = <8>;
 671                 reg = <0x0248>;
 672                 ti,index-starts-at-one;
 673                 ti,invert-autoidle-bit;
 674                 assigned-clocks = <&dpll_dsp_m3x2_ck>;
 675                 assigned-clock-rates = <400000000>;
 676         };
 677
 678         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 679                 #clock-cells = <0>;
 680                 compatible = "ti,omap4-dpll-x2-clock";
 681                 clocks = <&dpll_gmac_ck>;
 682         };
 683
 684         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 685                 #clock-cells = <0>;
 686                 compatible = "ti,divider-clock";
 687                 clocks = <&dpll_gmac_x2_ck>;
 688                 ti,max-div = <63>;
 689                 ti,autoidle-shift = <8>;
 690                 reg = <0x02c0>;
 691                 ti,index-starts-at-one;
 692                 ti,invert-autoidle-bit;
 693         };
 694
 695         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 696                 #clock-cells = <0>;
 697                 compatible = "ti,divider-clock";
 698                 clocks = <&dpll_gmac_x2_ck>;
 699                 ti,max-div = <63>;
 700                 ti,autoidle-shift = <8>;
 701                 reg = <0x02c4>;
 702                 ti,index-starts-at-one;
 703                 ti,invert-autoidle-bit;
 704         };
 705
 706         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 707                 #clock-cells = <0>;
 708                 compatible = "ti,divider-clock";
 709                 clocks = <&dpll_gmac_x2_ck>;
 710                 ti,max-div = <63>;
 711                 ti,autoidle-shift = <8>;
 712                 reg = <0x02c8>;
 713                 ti,index-starts-at-one;
 714                 ti,invert-autoidle-bit;
 715         };
 716
 717         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 718                 #clock-cells = <0>;
 719                 compatible = "ti,divider-clock";
 720                 clocks = <&dpll_gmac_x2_ck>;
 721                 ti,max-div = <31>;
 722                 ti,autoidle-shift = <8>;
 723                 reg = <0x02bc>;
 724                 ti,index-starts-at-one;
 725                 ti,invert-autoidle-bit;
 726         };
 727
 728         gmii_m_clk_div: gmii_m_clk_div {
 729                 #clock-cells = <0>;
 730                 compatible = "fixed-factor-clock";
 731                 clocks = <&dpll_gmac_h11x2_ck>;
 732                 clock-mult = <1>;
 733                 clock-div = <2>;
 734         };
 735
 736         hdmi_clk2_div: hdmi_clk2_div {
 737                 #clock-cells = <0>;
 738                 compatible = "fixed-factor-clock";
 739                 clocks = <&hdmi_clkin_ck>;
 740                 clock-mult = <1>;
 741                 clock-div = <1>;
 742         };
 743
 744         hdmi_div_clk: hdmi_div_clk {
 745                 #clock-cells = <0>;
 746                 compatible = "fixed-factor-clock";
 747                 clocks = <&hdmi_clkin_ck>;
 748                 clock-mult = <1>;
 749                 clock-div = <1>;
 750         };
 751
 752         l3_iclk_div: l3_iclk_div@100 {
 753                 #clock-cells = <0>;
 754                 compatible = "ti,divider-clock";
 755                 ti,max-div = <2>;
 756                 ti,bit-shift = <4>;
 757                 reg = <0x0100>;
 758                 clocks = <&dpll_core_h12x2_ck>;
 759                 ti,index-power-of-two;
 760         };
 761
 762         l4_root_clk_div: l4_root_clk_div {
 763                 #clock-cells = <0>;
 764                 compatible = "fixed-factor-clock";
 765                 clocks = <&l3_iclk_div>;
 766                 clock-mult = <1>;
 767                 clock-div = <2>;
 768         };
 769
 770         video1_clk2_div: video1_clk2_div {
 771                 #clock-cells = <0>;
 772                 compatible = "fixed-factor-clock";
 773                 clocks = <&video1_clkin_ck>;
 774                 clock-mult = <1>;
 775                 clock-div = <1>;
 776         };
 777
 778         video1_div_clk: video1_div_clk {
 779                 #clock-cells = <0>;
 780                 compatible = "fixed-factor-clock";
 781                 clocks = <&video1_clkin_ck>;
 782                 clock-mult = <1>;
 783                 clock-div = <1>;
 784         };
 785
 786         video2_clk2_div: video2_clk2_div {
 787                 #clock-cells = <0>;
 788                 compatible = "fixed-factor-clock";
 789                 clocks = <&video2_clkin_ck>;
 790                 clock-mult = <1>;
 791                 clock-div = <1>;
 792         };
 793
 794         video2_div_clk: video2_div_clk {
 795                 #clock-cells = <0>;
 796                 compatible = "fixed-factor-clock";
 797                 clocks = <&video2_clkin_ck>;
 798                 clock-mult = <1>;
 799                 clock-div = <1>;
 800         };
 801
 802         ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 803                 #clock-cells = <0>;
 804                 compatible = "ti,mux-clock";
 805                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 806                 ti,bit-shift = <24>;
 807                 reg = <0x0520>;
 808                 assigned-clocks = <&ipu1_gfclk_mux>;
 809                 assigned-clock-parents = <&dpll_core_h22x2_ck>;
 810         };
 811
 812         dummy_ck: dummy_ck {
 813                 #clock-cells = <0>;
 814                 compatible = "fixed-clock";
 815                 clock-frequency = <0>;
 816         };
 817 };
 818 &prm_clocks {
 819         sys_clkin1: sys_clkin1@110 {
 820                 #clock-cells = <0>;
 821                 compatible = "ti,mux-clock";
 822                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 823                 reg = <0x0110>;
 824                 ti,index-starts-at-one;
 825         };
 826
 827         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 828                 #clock-cells = <0>;
 829                 compatible = "ti,mux-clock";
 830                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 831                 reg = <0x0118>;
 832         };
 833
 834         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 835                 #clock-cells = <0>;
 836                 compatible = "ti,mux-clock";
 837                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 838                 reg = <0x0114>;
 839         };
 840
 841         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 842                 #clock-cells = <0>;
 843                 compatible = "ti,mux-clock";
 844                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 845                 reg = <0x010c>;
 846         };
 847
 848         abe_24m_fclk: abe_24m_fclk@11c {
 849                 #clock-cells = <0>;
 850                 compatible = "ti,divider-clock";
 851                 clocks = <&dpll_abe_m2x2_ck>;
 852                 reg = <0x011c>;
 853                 ti,dividers = <8>, <16>;
 854         };
 855
 856         aess_fclk: aess_fclk@178 {
 857                 #clock-cells = <0>;
 858                 compatible = "ti,divider-clock";
 859                 clocks = <&abe_clk>;
 860                 reg = <0x0178>;
 861                 ti,max-div = <2>;
 862         };
 863
 864         abe_giclk_div: abe_giclk_div@174 {
 865                 #clock-cells = <0>;
 866                 compatible = "ti,divider-clock";
 867                 clocks = <&aess_fclk>;
 868                 reg = <0x0174>;
 869                 ti,max-div = <2>;
 870         };
 871
 872         abe_lp_clk_div: abe_lp_clk_div@1d8 {
 873                 #clock-cells = <0>;
 874                 compatible = "ti,divider-clock";
 875                 clocks = <&dpll_abe_m2x2_ck>;
 876                 reg = <0x01d8>;
 877                 ti,dividers = <16>, <32>;
 878         };
 879
 880         abe_sys_clk_div: abe_sys_clk_div@120 {
 881                 #clock-cells = <0>;
 882                 compatible = "ti,divider-clock";
 883                 clocks = <&sys_clkin1>;
 884                 reg = <0x0120>;
 885                 ti,max-div = <2>;
 886         };
 887
 888         adc_gfclk_mux: adc_gfclk_mux@1dc {
 889                 #clock-cells = <0>;
 890                 compatible = "ti,mux-clock";
 891                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 892                 reg = <0x01dc>;
 893         };
 894
 895         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 896                 #clock-cells = <0>;
 897                 compatible = "ti,divider-clock";
 898                 clocks = <&sys_clkin1>;
 899                 ti,max-div = <64>;
 900                 reg = <0x01c8>;
 901                 ti,index-power-of-two;
 902         };
 903
 904         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 905                 #clock-cells = <0>;
 906                 compatible = "ti,divider-clock";
 907                 clocks = <&sys_clkin2>;
 908                 ti,max-div = <64>;
 909                 reg = <0x01cc>;
 910                 ti,index-power-of-two;
 911         };
 912
 913         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 914                 #clock-cells = <0>;
 915                 compatible = "ti,divider-clock";
 916                 clocks = <&dpll_abe_m2_ck>;
 917                 ti,max-div = <64>;
 918                 reg = <0x01bc>;
 919                 ti,index-power-of-two;
 920         };
 921
 922         dsp_gclk_div: dsp_gclk_div@18c {
 923                 #clock-cells = <0>;
 924                 compatible = "ti,divider-clock";
 925                 clocks = <&dpll_dsp_m2_ck>;
 926                 ti,max-div = <64>;
 927                 reg = <0x018c>;
 928                 ti,index-power-of-two;
 929         };
 930
 931         gpu_dclk: gpu_dclk@1a0 {
 932                 #clock-cells = <0>;
 933                 compatible = "ti,divider-clock";
 934                 clocks = <&dpll_gpu_m2_ck>;
 935                 ti,max-div = <64>;
 936                 reg = <0x01a0>;
 937                 ti,index-power-of-two;
 938         };
 939
 940         emif_phy_dclk_div: emif_phy_dclk_div@190 {
 941                 #clock-cells = <0>;
 942                 compatible = "ti,divider-clock";
 943                 clocks = <&dpll_ddr_m2_ck>;
 944                 ti,max-div = <64>;
 945                 reg = <0x0190>;
 946                 ti,index-power-of-two;
 947         };
 948
 949         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 950                 #clock-cells = <0>;
 951                 compatible = "ti,divider-clock";
 952                 clocks = <&dpll_gmac_m2_ck>;
 953                 ti,max-div = <64>;
 954                 reg = <0x019c>;
 955                 ti,index-power-of-two;
 956         };
 957
 958         gmac_main_clk: gmac_main_clk {
 959                 #clock-cells = <0>;
 960                 compatible = "fixed-factor-clock";
 961                 clocks = <&gmac_250m_dclk_div>;
 962                 clock-mult = <1>;
 963                 clock-div = <2>;
 964         };
 965
 966         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 967                 #clock-cells = <0>;
 968                 compatible = "ti,divider-clock";
 969                 clocks = <&dpll_usb_m2_ck>;
 970                 ti,max-div = <64>;
 971                 reg = <0x01ac>;
 972                 ti,index-power-of-two;
 973         };
 974
 975         usb_otg_dclk_div: usb_otg_dclk_div@184 {
 976                 #clock-cells = <0>;
 977                 compatible = "ti,divider-clock";
 978                 clocks = <&usb_otg_clkin_ck>;
 979                 ti,max-div = <64>;
 980                 reg = <0x0184>;
 981                 ti,index-power-of-two;
 982         };
 983
 984         sata_dclk_div: sata_dclk_div@1c0 {
 985                 #clock-cells = <0>;
 986                 compatible = "ti,divider-clock";
 987                 clocks = <&sys_clkin1>;
 988                 ti,max-div = <64>;
 989                 reg = <0x01c0>;
 990                 ti,index-power-of-two;
 991         };
 992
 993         pcie2_dclk_div: pcie2_dclk_div@1b8 {
 994                 #clock-cells = <0>;
 995                 compatible = "ti,divider-clock";
 996                 clocks = <&dpll_pcie_ref_m2_ck>;
 997                 ti,max-div = <64>;
 998                 reg = <0x01b8>;
 999                 ti,index-power-of-two;
1000         };
1001
1002         pcie_dclk_div: pcie_dclk_div@1b4 {
1003                 #clock-cells = <0>;
1004                 compatible = "ti,divider-clock";
1005                 clocks = <&apll_pcie_m2_ck>;
1006                 ti,max-div = <64>;
1007                 reg = <0x01b4>;
1008                 ti,index-power-of-two;
1009         };
1010
1011         emu_dclk_div: emu_dclk_div@194 {
1012                 #clock-cells = <0>;
1013                 compatible = "ti,divider-clock";
1014                 clocks = <&sys_clkin1>;
1015                 ti,max-div = <64>;
1016                 reg = <0x0194>;
1017                 ti,index-power-of-two;
1018         };
1019
1020         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1021                 #clock-cells = <0>;
1022                 compatible = "ti,divider-clock";
1023                 clocks = <&secure_32k_clk_src_ck>;
1024                 ti,max-div = <64>;
1025                 reg = <0x01c4>;
1026                 ti,index-power-of-two;
1027         };
1028
1029         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1030                 #clock-cells = <0>;
1031                 compatible = "ti,mux-clock";
1032                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1033                 reg = <0x0158>;
1034         };
1035
1036         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1037                 #clock-cells = <0>;
1038                 compatible = "ti,mux-clock";
1039                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1040                 reg = <0x015c>;
1041         };
1042
1043         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1044                 #clock-cells = <0>;
1045                 compatible = "ti,mux-clock";
1046                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1047                 reg = <0x0160>;
1048         };
1049
1050         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1051                 #clock-cells = <0>;
1052                 compatible = "fixed-factor-clock";
1053                 clocks = <&sys_clkin1>;
1054                 clock-mult = <1>;
1055                 clock-div = <2>;
1056         };
1057
1058         eve_clk: eve_clk@180 {
1059                 #clock-cells = <0>;
1060                 compatible = "ti,mux-clock";
1061                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1062                 reg = <0x0180>;
1063         };
1064
1065         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1066                 #clock-cells = <0>;
1067                 compatible = "ti,mux-clock";
1068                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1069                 reg = <0x0164>;
1070         };
1071
1072         mlb_clk: mlb_clk@134 {
1073                 #clock-cells = <0>;
1074                 compatible = "ti,divider-clock";
1075                 clocks = <&mlb_clkin_ck>;
1076                 ti,max-div = <64>;
1077                 reg = <0x0134>;
1078                 ti,index-power-of-two;
1079         };
1080
1081         mlbp_clk: mlbp_clk@130 {
1082                 #clock-cells = <0>;
1083                 compatible = "ti,divider-clock";
1084                 clocks = <&mlbp_clkin_ck>;
1085                 ti,max-div = <64>;
1086                 reg = <0x0130>;
1087                 ti,index-power-of-two;
1088         };
1089
1090         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1091                 #clock-cells = <0>;
1092                 compatible = "ti,divider-clock";
1093                 clocks = <&dpll_abe_m2_ck>;
1094                 ti,max-div = <64>;
1095                 reg = <0x0138>;
1096                 ti,index-power-of-two;
1097         };
1098
1099         timer_sys_clk_div: timer_sys_clk_div@144 {
1100                 #clock-cells = <0>;
1101                 compatible = "ti,divider-clock";
1102                 clocks = <&sys_clkin1>;
1103                 reg = <0x0144>;
1104                 ti,max-div = <2>;
1105         };
1106
1107         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1108                 #clock-cells = <0>;
1109                 compatible = "ti,mux-clock";
1110                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1111                 reg = <0x0168>;
1112         };
1113
1114         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1115                 #clock-cells = <0>;
1116                 compatible = "ti,mux-clock";
1117                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1118                 reg = <0x016c>;
1119         };
1120
1121         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1122                 #clock-cells = <0>;
1123                 compatible = "ti,mux-clock";
1124                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1125                 reg = <0x0108>;
1126         };
1127 };
1128
1129 &cm_core_clocks {
1130         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1131                 #clock-cells = <0>;
1132                 compatible = "ti,omap4-dpll-clock";
1133                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1134                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1135         };
1136
1137         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1138                 #clock-cells = <0>;
1139                 compatible = "ti,divider-clock";
1140                 clocks = <&dpll_pcie_ref_ck>;
1141                 ti,max-div = <31>;
1142                 ti,autoidle-shift = <8>;
1143                 reg = <0x0210>;
1144                 ti,index-starts-at-one;
1145                 ti,invert-autoidle-bit;
1146         };
1147
1148         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1149                 compatible = "ti,mux-clock";
1150                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1151                 #clock-cells = <0>;
1152                 reg = <0x021c 0x4>;
1153                 ti,bit-shift = <7>;
1154         };
1155
1156         apll_pcie_ck: apll_pcie_ck@21c {
1157                 #clock-cells = <0>;
1158                 compatible = "ti,dra7-apll-clock";
1159                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1160                 reg = <0x021c>, <0x0220>;
1161         };
1162
1163         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1164                 compatible = "ti,divider-clock";
1165                 clocks = <&apll_pcie_ck>;
1166                 #clock-cells = <0>;
1167                 reg = <0x021c>;
1168                 ti,dividers = <2>, <1>;
1169                 ti,bit-shift = <8>;
1170                 ti,max-div = <2>;
1171         };
1172
1173         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1174                 #clock-cells = <0>;
1175                 compatible = "fixed-factor-clock";
1176                 clocks = <&apll_pcie_ck>;
1177                 clock-mult = <1>;
1178                 clock-div = <1>;
1179         };
1180
1181         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1182                 #clock-cells = <0>;
1183                 compatible = "fixed-factor-clock";
1184                 clocks = <&apll_pcie_ck>;
1185                 clock-mult = <1>;
1186                 clock-div = <1>;
1187         };
1188
1189         apll_pcie_m2_ck: apll_pcie_m2_ck {
1190                 #clock-cells = <0>;
1191                 compatible = "fixed-factor-clock";
1192                 clocks = <&apll_pcie_ck>;
1193                 clock-mult = <1>;
1194                 clock-div = <1>;
1195         };
1196
1197         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1198                 #clock-cells = <0>;
1199                 compatible = "ti,mux-clock";
1200                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1201                 ti,bit-shift = <23>;
1202                 reg = <0x014c>;
1203         };
1204
1205         dpll_per_ck: dpll_per_ck@140 {
1206                 #clock-cells = <0>;
1207                 compatible = "ti,omap4-dpll-clock";
1208                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1209                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1210         };
1211
1212         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1213                 #clock-cells = <0>;
1214                 compatible = "ti,divider-clock";
1215                 clocks = <&dpll_per_ck>;
1216                 ti,max-div = <31>;
1217                 ti,autoidle-shift = <8>;
1218                 reg = <0x0150>;
1219                 ti,index-starts-at-one;
1220                 ti,invert-autoidle-bit;
1221         };
1222
1223         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1224                 #clock-cells = <0>;
1225                 compatible = "fixed-factor-clock";
1226                 clocks = <&dpll_per_m2_ck>;
1227                 clock-mult = <1>;
1228                 clock-div = <1>;
1229         };
1230
1231         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1232                 #clock-cells = <0>;
1233                 compatible = "ti,mux-clock";
1234                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1235                 ti,bit-shift = <23>;
1236                 reg = <0x018c>;
1237         };
1238
1239         dpll_usb_ck: dpll_usb_ck@180 {
1240                 #clock-cells = <0>;
1241                 compatible = "ti,omap4-dpll-j-type-clock";
1242                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1243                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1244         };
1245
1246         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1247                 #clock-cells = <0>;
1248                 compatible = "ti,divider-clock";
1249                 clocks = <&dpll_usb_ck>;
1250                 ti,max-div = <127>;
1251                 ti,autoidle-shift = <8>;
1252                 reg = <0x0190>;
1253                 ti,index-starts-at-one;
1254                 ti,invert-autoidle-bit;
1255         };
1256
1257         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1258                 #clock-cells = <0>;
1259                 compatible = "ti,divider-clock";
1260                 clocks = <&dpll_pcie_ref_ck>;
1261                 ti,max-div = <127>;
1262                 ti,autoidle-shift = <8>;
1263                 reg = <0x0210>;
1264                 ti,index-starts-at-one;
1265                 ti,invert-autoidle-bit;
1266         };
1267
1268         dpll_per_x2_ck: dpll_per_x2_ck {
1269                 #clock-cells = <0>;
1270                 compatible = "ti,omap4-dpll-x2-clock";
1271                 clocks = <&dpll_per_ck>;
1272         };
1273
1274         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1275                 #clock-cells = <0>;
1276                 compatible = "ti,divider-clock";
1277                 clocks = <&dpll_per_x2_ck>;
1278                 ti,max-div = <63>;
1279                 ti,autoidle-shift = <8>;
1280                 reg = <0x0158>;
1281                 ti,index-starts-at-one;
1282                 ti,invert-autoidle-bit;
1283         };
1284
1285         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1286                 #clock-cells = <0>;
1287                 compatible = "ti,divider-clock";
1288                 clocks = <&dpll_per_x2_ck>;
1289                 ti,max-div = <63>;
1290                 ti,autoidle-shift = <8>;
1291                 reg = <0x015c>;
1292                 ti,index-starts-at-one;
1293                 ti,invert-autoidle-bit;
1294         };
1295
1296         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1297                 #clock-cells = <0>;
1298                 compatible = "ti,divider-clock";
1299                 clocks = <&dpll_per_x2_ck>;
1300                 ti,max-div = <63>;
1301                 ti,autoidle-shift = <8>;
1302                 reg = <0x0160>;
1303                 ti,index-starts-at-one;
1304                 ti,invert-autoidle-bit;
1305         };
1306
1307         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1308                 #clock-cells = <0>;
1309                 compatible = "ti,divider-clock";
1310                 clocks = <&dpll_per_x2_ck>;
1311                 ti,max-div = <63>;
1312                 ti,autoidle-shift = <8>;
1313                 reg = <0x0164>;
1314                 ti,index-starts-at-one;
1315                 ti,invert-autoidle-bit;
1316         };
1317
1318         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1319                 #clock-cells = <0>;
1320                 compatible = "ti,divider-clock";
1321                 clocks = <&dpll_per_x2_ck>;
1322                 ti,max-div = <31>;
1323                 ti,autoidle-shift = <8>;
1324                 reg = <0x0150>;
1325                 ti,index-starts-at-one;
1326                 ti,invert-autoidle-bit;
1327         };
1328
1329         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1330                 #clock-cells = <0>;
1331                 compatible = "fixed-factor-clock";
1332                 clocks = <&dpll_usb_ck>;
1333                 clock-mult = <1>;
1334                 clock-div = <1>;
1335         };
1336
1337         func_128m_clk: func_128m_clk {
1338                 #clock-cells = <0>;
1339                 compatible = "fixed-factor-clock";
1340                 clocks = <&dpll_per_h11x2_ck>;
1341                 clock-mult = <1>;
1342                 clock-div = <2>;
1343         };
1344
1345         func_12m_fclk: func_12m_fclk {
1346                 #clock-cells = <0>;
1347                 compatible = "fixed-factor-clock";
1348                 clocks = <&dpll_per_m2x2_ck>;
1349                 clock-mult = <1>;
1350                 clock-div = <16>;
1351         };
1352
1353         func_24m_clk: func_24m_clk {
1354                 #clock-cells = <0>;
1355                 compatible = "fixed-factor-clock";
1356                 clocks = <&dpll_per_m2_ck>;
1357                 clock-mult = <1>;
1358                 clock-div = <4>;
1359         };
1360
1361         func_48m_fclk: func_48m_fclk {
1362                 #clock-cells = <0>;
1363                 compatible = "fixed-factor-clock";
1364                 clocks = <&dpll_per_m2x2_ck>;
1365                 clock-mult = <1>;
1366                 clock-div = <4>;
1367         };
1368
1369         func_96m_fclk: func_96m_fclk {
1370                 #clock-cells = <0>;
1371                 compatible = "fixed-factor-clock";
1372                 clocks = <&dpll_per_m2x2_ck>;
1373                 clock-mult = <1>;
1374                 clock-div = <2>;
1375         };
1376
1377         l3init_60m_fclk: l3init_60m_fclk@104 {
1378                 #clock-cells = <0>;
1379                 compatible = "ti,divider-clock";
1380                 clocks = <&dpll_usb_m2_ck>;
1381                 reg = <0x0104>;
1382                 ti,dividers = <1>, <8>;
1383         };
1384
1385         clkout2_clk: clkout2_clk@6b0 {
1386                 #clock-cells = <0>;
1387                 compatible = "ti,gate-clock";
1388                 clocks = <&clkoutmux2_clk_mux>;
1389                 ti,bit-shift = <8>;
1390                 reg = <0x06b0>;
1391         };
1392
1393         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1394                 #clock-cells = <0>;
1395                 compatible = "ti,gate-clock";
1396                 clocks = <&dpll_usb_clkdcoldo>;
1397                 ti,bit-shift = <8>;
1398                 reg = <0x06c0>;
1399         };
1400
1401         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1402                 #clock-cells = <0>;
1403                 compatible = "ti,gate-clock";
1404                 clocks = <&sys_32k_ck>;
1405                 ti,bit-shift = <8>;
1406                 reg = <0x0640>;
1407         };
1408
1409         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1410                 #clock-cells = <0>;
1411                 compatible = "ti,gate-clock";
1412                 clocks = <&sys_32k_ck>;
1413                 ti,bit-shift = <8>;
1414                 reg = <0x0688>;
1415         };
1416
1417         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1418                 #clock-cells = <0>;
1419                 compatible = "ti,gate-clock";
1420                 clocks = <&sys_32k_ck>;
1421                 ti,bit-shift = <8>;
1422                 reg = <0x0698>;
1423         };
1424
1425         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1426                 #clock-cells = <0>;
1427                 compatible = "ti,mux-clock";
1428                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1429                 ti,bit-shift = <24>;
1430                 reg = <0x1220>;
1431                 assigned-clocks = <&gpu_core_gclk_mux>;
1432                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1433         };
1434
1435         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1436                 #clock-cells = <0>;
1437                 compatible = "ti,mux-clock";
1438                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1439                 ti,bit-shift = <26>;
1440                 reg = <0x1220>;
1441                 assigned-clocks = <&gpu_hyd_gclk_mux>;
1442                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1443         };
1444
1445         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1446                 #clock-cells = <0>;
1447                 compatible = "ti,divider-clock";
1448                 clocks = <&wkupaon_iclk_mux>;
1449                 ti,bit-shift = <24>;
1450                 reg = <0x0e50>;
1451                 ti,dividers = <8>, <16>, <32>;
1452         };
1453
1454         vip1_gclk_mux: vip1_gclk_mux@1020 {
1455                 #clock-cells = <0>;
1456                 compatible = "ti,mux-clock";
1457                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1458                 ti,bit-shift = <24>;
1459                 reg = <0x1020>;
1460         };
1461
1462         vip2_gclk_mux: vip2_gclk_mux@1028 {
1463                 #clock-cells = <0>;
1464                 compatible = "ti,mux-clock";
1465                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1466                 ti,bit-shift = <24>;
1467                 reg = <0x1028>;
1468         };
1469
1470         vip3_gclk_mux: vip3_gclk_mux@1030 {
1471                 #clock-cells = <0>;
1472                 compatible = "ti,mux-clock";
1473                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1474                 ti,bit-shift = <24>;
1475                 reg = <0x1030>;
1476         };
1477 };
1478
1479 &cm_core_clockdomains {
1480         coreaon_clkdm: coreaon_clkdm {
1481                 compatible = "ti,clockdomain";
1482                 clocks = <&dpll_usb_ck>;
1483         };
1484 };
1485
1486 &scm_conf_clocks {
1487         dss_deshdcp_clk: dss_deshdcp_clk@558 {
1488                 #clock-cells = <0>;
1489                 compatible = "ti,gate-clock";
1490                 clocks = <&l3_iclk_div>;
1491                 ti,bit-shift = <0>;
1492                 reg = <0x558>;
1493         };
1494
1495        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
1496                 #clock-cells = <0>;
1497                 compatible = "ti,gate-clock";
1498                 clocks = <&l4_root_clk_div>;
1499                 ti,bit-shift = <20>;
1500                 reg = <0x0558>;
1501         };
1502
1503         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
1504                 #clock-cells = <0>;
1505                 compatible = "ti,gate-clock";
1506                 clocks = <&l4_root_clk_div>;
1507                 ti,bit-shift = <21>;
1508                 reg = <0x0558>;
1509         };
1510
1511         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
1512                 #clock-cells = <0>;
1513                 compatible = "ti,gate-clock";
1514                 clocks = <&l4_root_clk_div>;
1515                 ti,bit-shift = <22>;
1516                 reg = <0x0558>;
1517         };
1518
1519         sys_32k_ck: sys_32k_ck {
1520                 #clock-cells = <0>;
1521                 compatible = "ti,mux-clock";
1522                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1523                 ti,bit-shift = <8>;
1524                 reg = <0x6c4>;
1525         };
1526 };
1527
1528 &cm_core_aon {
1529         mpu_cm: mpu-cm@300 {
1530                 compatible = "ti,omap4-cm";
1531                 reg = <0x300 0x100>;
1532                 #address-cells = <1>;
1533                 #size-cells = <1>;
1534                 ranges = <0 0x300 0x100>;
1535
1536                 mpu_clkctrl: mpu-clkctrl@20 {
1537                         compatible = "ti,clkctrl";
1538                         reg = <0x20 0x4>;
1539                         #clock-cells = <2>;
1540                 };
1541
1542         };
1543
1544         dsp1_cm: dsp1-cm@400 {
1545                 compatible = "ti,omap4-cm";
1546                 reg = <0x400 0x100>;
1547                 #address-cells = <1>;
1548                 #size-cells = <1>;
1549                 ranges = <0 0x400 0x100>;
1550
1551                 dsp1_clkctrl: dsp1-clkctrl@20 {
1552                         compatible = "ti,clkctrl";
1553                         reg = <0x20 0x4>;
1554                         #clock-cells = <2>;
1555                 };
1556
1557         };
1558
1559         ipu_cm: ipu-cm@500 {
1560                 compatible = "ti,omap4-cm";
1561                 reg = <0x500 0x100>;
1562                 #address-cells = <1>;
1563                 #size-cells = <1>;
1564                 ranges = <0 0x500 0x100>;
1565
1566                 ipu1_clkctrl: ipu1-clkctrl@20 {
1567                         compatible = "ti,clkctrl";
1568                         reg = <0x20 0x4>;
1569                         #clock-cells = <2>;
1570                 };
1571
1572                 ipu_clkctrl: ipu-clkctrl@50 {
1573                         compatible = "ti,clkctrl";
1574                         reg = <0x50 0x34>;
1575                         #clock-cells = <2>;
1576                 };
1577
1578         };
1579
1580         dsp2_cm: dsp2-cm@600 {
1581                 compatible = "ti,omap4-cm";
1582                 reg = <0x600 0x100>;
1583                 #address-cells = <1>;
1584                 #size-cells = <1>;
1585                 ranges = <0 0x600 0x100>;
1586
1587                 dsp2_clkctrl: dsp2-clkctrl@20 {
1588                         compatible = "ti,clkctrl";
1589                         reg = <0x20 0x4>;
1590                         #clock-cells = <2>;
1591                 };
1592
1593         };
1594
1595         rtc_cm: rtc-cm@700 {
1596                 compatible = "ti,omap4-cm";
1597                 reg = <0x700 0x100>;
1598                 #address-cells = <1>;
1599                 #size-cells = <1>;
1600                 ranges = <0 0x700 0x100>;
1601
1602                 rtc_clkctrl: rtc-clkctrl@20 {
1603                         compatible = "ti,clkctrl";
1604                         reg = <0x20 0x28>;
1605                         #clock-cells = <2>;
1606                 };
1607         };
1608
1609 };
1610
1611 &cm_core {
1612         coreaon_cm: coreaon-cm@600 {
1613                 compatible = "ti,omap4-cm";
1614                 reg = <0x600 0x100>;
1615                 #address-cells = <1>;
1616                 #size-cells = <1>;
1617                 ranges = <0 0x600 0x100>;
1618
1619                 coreaon_clkctrl: coreaon-clkctrl@20 {
1620                         compatible = "ti,clkctrl";
1621                         reg = <0x20 0x1c>;
1622                         #clock-cells = <2>;
1623                 };
1624         };
1625
1626         l3main1_cm: l3main1-cm@700 {
1627                 compatible = "ti,omap4-cm";
1628                 reg = <0x700 0x100>;
1629                 #address-cells = <1>;
1630                 #size-cells = <1>;
1631                 ranges = <0 0x700 0x100>;
1632
1633                 l3main1_clkctrl: l3main1-clkctrl@20 {
1634                         compatible = "ti,clkctrl";
1635                         reg = <0x20 0x74>;
1636                         #clock-cells = <2>;
1637                 };
1638
1639         };
1640
1641         ipu2_cm: ipu2-cm@900 {
1642                 compatible = "ti,omap4-cm";
1643                 reg = <0x900 0x100>;
1644                 #address-cells = <1>;
1645                 #size-cells = <1>;
1646                 ranges = <0 0x900 0x100>;
1647
1648                 ipu2_clkctrl: ipu2-clkctrl@20 {
1649                         compatible = "ti,clkctrl";
1650                         reg = <0x20 0x4>;
1651                         #clock-cells = <2>;
1652                 };
1653
1654         };
1655
1656         dma_cm: dma-cm@a00 {
1657                 compatible = "ti,omap4-cm";
1658                 reg = <0xa00 0x100>;
1659                 #address-cells = <1>;
1660                 #size-cells = <1>;
1661                 ranges = <0 0xa00 0x100>;
1662
1663                 dma_clkctrl: dma-clkctrl@20 {
1664                         compatible = "ti,clkctrl";
1665                         reg = <0x20 0x4>;
1666                         #clock-cells = <2>;
1667                 };
1668         };
1669
1670         emif_cm: emif-cm@b00 {
1671                 compatible = "ti,omap4-cm";
1672                 reg = <0xb00 0x100>;
1673                 #address-cells = <1>;
1674                 #size-cells = <1>;
1675                 ranges = <0 0xb00 0x100>;
1676
1677                 emif_clkctrl: emif-clkctrl@20 {
1678                         compatible = "ti,clkctrl";
1679                         reg = <0x20 0x4>;
1680                         #clock-cells = <2>;
1681                 };
1682         };
1683
1684         atl_cm: atl-cm@c00 {
1685                 compatible = "ti,omap4-cm";
1686                 reg = <0xc00 0x100>;
1687                 #address-cells = <1>;
1688                 #size-cells = <1>;
1689                 ranges = <0 0xc00 0x100>;
1690
1691                 atl_clkctrl: atl-clkctrl@0 {
1692                         compatible = "ti,clkctrl";
1693                         reg = <0x0 0x4>;
1694                         #clock-cells = <2>;
1695                 };
1696         };
1697
1698         l4cfg_cm: l4cfg-cm@d00 {
1699                 compatible = "ti,omap4-cm";
1700                 reg = <0xd00 0x100>;
1701                 #address-cells = <1>;
1702                 #size-cells = <1>;
1703                 ranges = <0 0xd00 0x100>;
1704
1705                 l4cfg_clkctrl: l4cfg-clkctrl@20 {
1706                         compatible = "ti,clkctrl";
1707                         reg = <0x20 0x84>;
1708                         #clock-cells = <2>;
1709                 };
1710         };
1711
1712         l3instr_cm: l3instr-cm@e00 {
1713                 compatible = "ti,omap4-cm";
1714                 reg = <0xe00 0x100>;
1715                 #address-cells = <1>;
1716                 #size-cells = <1>;
1717                 ranges = <0 0xe00 0x100>;
1718
1719                 l3instr_clkctrl: l3instr-clkctrl@20 {
1720                         compatible = "ti,clkctrl";
1721                         reg = <0x20 0xc>;
1722                         #clock-cells = <2>;
1723                 };
1724         };
1725
1726         dss_cm: dss-cm@1100 {
1727                 compatible = "ti,omap4-cm";
1728                 reg = <0x1100 0x100>;
1729                 #address-cells = <1>;
1730                 #size-cells = <1>;
1731                 ranges = <0 0x1100 0x100>;
1732
1733                 dss_clkctrl: dss-clkctrl@20 {
1734                         compatible = "ti,clkctrl";
1735                         reg = <0x20 0x14>;
1736                         #clock-cells = <2>;
1737                 };
1738         };
1739
1740         l3init_cm: l3init-cm@1300 {
1741                 compatible = "ti,omap4-cm";
1742                 reg = <0x1300 0x100>;
1743                 #address-cells = <1>;
1744                 #size-cells = <1>;
1745                 ranges = <0 0x1300 0x100>;
1746
1747                 l3init_clkctrl: l3init-clkctrl@20 {
1748                         compatible = "ti,clkctrl";
1749                         reg = <0x20 0x6c>, <0xe0 0x14>;
1750                         #clock-cells = <2>;
1751                 };
1752
1753                 pcie_clkctrl: pcie-clkctrl@b0 {
1754                         compatible = "ti,clkctrl";
1755                         reg = <0xb0 0xc>;
1756                         #clock-cells = <2>;
1757                 };
1758
1759                 gmac_clkctrl: gmac-clkctrl@d0 {
1760                         compatible = "ti,clkctrl";
1761                         reg = <0xd0 0x4>;
1762                         #clock-cells = <2>;
1763                 };
1764
1765         };
1766
1767         l4per_cm: l4per-cm@1700 {
1768                 compatible = "ti,omap4-cm";
1769                 reg = <0x1700 0x300>;
1770                 #address-cells = <1>;
1771                 #size-cells = <1>;
1772                 ranges = <0 0x1700 0x300>;
1773
1774                 l4per_clkctrl: l4per-clkctrl@28 {
1775                         compatible = "ti,clkctrl";
1776                         reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
1777                         #clock-cells = <2>;
1778
1779                         assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
1780                         assigned-clock-parents = <&abe_24m_fclk>;
1781                 };
1782
1783                 l4sec_clkctrl: l4sec-clkctrl@1a0 {
1784                         compatible = "ti,clkctrl";
1785                         reg = <0x1a0 0x2c>;
1786                         #clock-cells = <2>;
1787                 };
1788
1789                 l4per2_clkctrl: l4per2-clkctrl@c {
1790                         compatible = "ti,clkctrl";
1791                         reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
1792                         #clock-cells = <2>;
1793                 };
1794
1795                 l4per3_clkctrl: l4per3-clkctrl@14 {
1796                         compatible = "ti,clkctrl";
1797                         reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1798                         #clock-cells = <2>;
1799                 };
1800         };
1801
1802 };
1803
1804 &prm {
1805         wkupaon_cm: wkupaon-cm@1800 {
1806                 compatible = "ti,omap4-cm";
1807                 reg = <0x1800 0x100>;
1808                 #address-cells = <1>;
1809                 #size-cells = <1>;
1810                 ranges = <0 0x1800 0x100>;
1811
1812                 wkupaon_clkctrl: wkupaon-clkctrl@20 {
1813                         compatible = "ti,clkctrl";
1814                         reg = <0x20 0x6c>;
1815                         #clock-cells = <2>;
1816                 };
1817         };
1818 };