| blob | 80986b97dfe5e18ee3ad3aae7c3fb619328fe681 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
22 / {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clocks = <&clock CLK_ARM_CLK>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <1>;
66 clocks = <&clock CLK_ARM_CLK>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
70 };
71 };
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
75 opp-shared;
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <140000>;
81 };
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <937500>;
85 clock-latency-ns = <140000>;
86 };
87 opp-400000000 {
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <950000>;
90 clock-latency-ns = <140000>;
91 };
92 opp-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <975000>;
95 clock-latency-ns = <140000>;
96 };
97 opp-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <140000>;
101 };
102 opp-700000000 {
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <1012500>;
105 clock-latency-ns = <140000>;
106 };
107 opp-800000000 {
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1025000>;
110 clock-latency-ns = <140000>;
111 };
112 opp-900000000 {
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1050000>;
115 clock-latency-ns = <140000>;
116 };
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1075000>;
120 clock-latency-ns = <140000>;
121 opp-suspend;
122 };
123 opp-1100000000 {
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1100000>;
126 clock-latency-ns = <140000>;
127 };
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1125000>;
131 clock-latency-ns = <140000>;
132 };
133 opp-1300000000 {
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1150000>;
136 clock-latency-ns = <140000>;
137 };
138 opp-1400000000 {
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1200000>;
141 clock-latency-ns = <140000>;
142 };
143 opp-1500000000 {
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1225000>;
146 clock-latency-ns = <140000>;
147 };
148 opp-1600000000 {
149 opp-hz = /bits/ 64 <1600000000>;
150 opp-microvolt = <1250000>;
151 clock-latency-ns = <140000>;
152 };
153 opp-1700000000 {
154 opp-hz = /bits/ 64 <1700000000>;
155 opp-microvolt = <1300000>;
156 clock-latency-ns = <140000>;
157 };
158 };
160 soc: soc {
161 sysram@2020000 {
162 compatible = "mmio-sram";
163 reg = <0x02020000 0x30000>;
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x02020000 0x30000>;
168 smp-sysram@0 {
169 compatible = "samsung,exynos4210-sysram";
170 reg = <0x0 0x1000>;
171 };
173 smp-sysram@2f000 {
174 compatible = "samsung,exynos4210-sysram-ns";
175 reg = <0x2f000 0x1000>;
176 };
177 };
179 pd_gsc: power-domain@10044000 {
180 compatible = "samsung,exynos4210-pd";
181 reg = <0x10044000 0x20>;
182 #power-domain-cells = <0>;
183 label = "GSC";
184 };
186 pd_mfc: power-domain@10044040 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10044040 0x20>;
189 #power-domain-cells = <0>;
190 label = "MFC";
191 };
193 pd_g3d: power-domain@10044060 {
194 compatible = "samsung,exynos4210-pd";
195 reg = <0x10044060 0x20>;
196 #power-domain-cells = <0>;
197 label = "G3D";
198 };
200 pd_disp1: power-domain@100440a0 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x100440A0 0x20>;
203 #power-domain-cells = <0>;
204 label = "DISP1";
205 };
207 pd_mau: power-domain@100440c0 {
208 compatible = "samsung,exynos4210-pd";
209 reg = <0x100440C0 0x20>;
210 #power-domain-cells = <0>;
211 label = "MAU";
212 };
214 clock: clock-controller@10010000 {
215 compatible = "samsung,exynos5250-clock";
216 reg = <0x10010000 0x30000>;
217 #clock-cells = <1>;
218 };
220 clock_audss: audss-clock-controller@3810000 {
221 compatible = "samsung,exynos5250-audss-clock";
222 reg = <0x03810000 0x0C>;
223 #clock-cells = <1>;
224 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
225 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
226 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
227 power-domains = <&pd_mau>;
228 };
230 timer {
231 compatible = "arm,armv7-timer";
232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
236 /*
237 * Unfortunately we need this since some versions
238 * of U-Boot on Exynos don't set the CNTFRQ register,
239 * so we need the value from DT.
240 */
241 clock-frequency = <24000000>;
242 };
244 mct@101c0000 {
245 compatible = "samsung,exynos4210-mct";
246 reg = <0x101C0000 0x800>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 interrupt-parent = <&mct_map>;
250 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
251 <4 0>, <5 0>;
252 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
253 clock-names = "fin_pll", "mct";
255 mct_map: mct-map {
256 #interrupt-cells = <2>;
257 #address-cells = <0>;
258 #size-cells = <0>;
259 interrupt-map = <0x0 0 &combiner 23 3>,
260 <0x1 0 &combiner 23 4>,
261 <0x2 0 &combiner 25 2>,
262 <0x3 0 &combiner 25 3>,
263 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
264 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
265 };
266 };
268 pmu {
269 compatible = "arm,cortex-a15-pmu";
270 interrupt-parent = <&combiner>;
271 interrupts = <1 2>, <22 4>;
272 };
274 pinctrl_0: pinctrl@11400000 {
275 compatible = "samsung,exynos5250-pinctrl";
276 reg = <0x11400000 0x1000>;
277 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
279 wakup_eint: wakeup-interrupt-controller {
280 compatible = "samsung,exynos4210-wakeup-eint";
281 interrupt-parent = <&gic>;
282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
283 };
284 };
286 pinctrl_1: pinctrl@13400000 {
287 compatible = "samsung,exynos5250-pinctrl";
288 reg = <0x13400000 0x1000>;
289 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
290 };
292 pinctrl_2: pinctrl@10d10000 {
293 compatible = "samsung,exynos5250-pinctrl";
294 reg = <0x10d10000 0x1000>;
295 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
296 };
298 pinctrl_3: pinctrl@3860000 {
299 compatible = "samsung,exynos5250-pinctrl";
300 reg = <0x03860000 0x1000>;
301 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
302 power-domains = <&pd_mau>;
303 };
305 pmu_system_controller: system-controller@10040000 {
306 compatible = "samsung,exynos5250-pmu", "syscon";
307 reg = <0x10040000 0x5000>;
308 clock-names = "clkout16";
309 clocks = <&clock CLK_FIN_PLL>;
310 #clock-cells = <1>;
311 interrupt-controller;
312 #interrupt-cells = <3>;
313 interrupt-parent = <&gic>;
314 };
316 watchdog@101d0000 {
317 compatible = "samsung,exynos5250-wdt";
318 reg = <0x101D0000 0x100>;
319 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clock CLK_WDT>;
321 clock-names = "watchdog";
322 samsung,syscon-phandle = <&pmu_system_controller>;
323 };
325 mfc: codec@11000000 {
326 compatible = "samsung,mfc-v6";
327 reg = <0x11000000 0x10000>;
328 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
329 power-domains = <&pd_mfc>;
330 clocks = <&clock CLK_MFC>;
331 clock-names = "mfc";
332 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
333 iommu-names = "left", "right";
334 };
336 rotator: rotator@11c00000 {
337 compatible = "samsung,exynos5250-rotator";
338 reg = <0x11C00000 0x64>;
339 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&clock CLK_ROTATOR>;
341 clock-names = "rotator";
342 iommus = <&sysmmu_rotator>;
343 };
345 tmu: tmu@10060000 {
346 compatible = "samsung,exynos5250-tmu";
347 reg = <0x10060000 0x100>;
348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clock CLK_TMU>;
350 clock-names = "tmu_apbif";
351 #thermal-sensor-cells = <0>;
352 };
354 sata: sata@122f0000 {
355 compatible = "snps,dwc-ahci";
356 samsung,sata-freq = <66>;
357 reg = <0x122F0000 0x1ff>;
358 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
360 clock-names = "sata", "sclk_sata";
361 phys = <&sata_phy>;
362 phy-names = "sata-phy";
363 status = "disabled";
364 };
366 sata_phy: sata-phy@12170000 {
367 compatible = "samsung,exynos5250-sata-phy";
368 reg = <0x12170000 0x1ff>;
369 clocks = <&clock CLK_SATA_PHYCTRL>;
370 clock-names = "sata_phyctrl";
371 #phy-cells = <0>;
372 samsung,syscon-phandle = <&pmu_system_controller>;
373 status = "disabled";
374 };
376 /* i2c_0-3 are defined in exynos5.dtsi */
377 i2c_4: i2c@12ca0000 {
378 compatible = "samsung,s3c2440-i2c";
379 reg = <0x12CA0000 0x100>;
380 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 clocks = <&clock CLK_I2C4>;
384 clock-names = "i2c";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c4_bus>;
387 status = "disabled";
388 };
390 i2c_5: i2c@12cb0000 {
391 compatible = "samsung,s3c2440-i2c";
392 reg = <0x12CB0000 0x100>;
393 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 clocks = <&clock CLK_I2C5>;
397 clock-names = "i2c";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c5_bus>;
400 status = "disabled";
401 };
403 i2c_6: i2c@12cc0000 {
404 compatible = "samsung,s3c2440-i2c";
405 reg = <0x12CC0000 0x100>;
406 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 clocks = <&clock CLK_I2C6>;
410 clock-names = "i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c6_bus>;
413 status = "disabled";
414 };
416 i2c_7: i2c@12cd0000 {
417 compatible = "samsung,s3c2440-i2c";
418 reg = <0x12CD0000 0x100>;
419 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 clocks = <&clock CLK_I2C7>;
423 clock-names = "i2c";
424 pinctrl-names = "default";
425 pinctrl-0 = <&i2c7_bus>;
426 status = "disabled";
427 };
429 i2c_8: i2c@12ce0000 {
430 compatible = "samsung,s3c2440-hdmiphy-i2c";
431 reg = <0x12CE0000 0x1000>;
432 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 clocks = <&clock CLK_I2C_HDMI>;
436 clock-names = "i2c";
437 status = "disabled";
439 hdmiphy: hdmiphy@38 {
440 compatible = "samsung,exynos4212-hdmiphy";
441 reg = <0x38>;
442 };
443 };
445 i2c_9: i2c@121d0000 {
446 compatible = "samsung,exynos5-sata-phy-i2c";
447 reg = <0x121D0000 0x100>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 clocks = <&clock CLK_SATA_PHYI2C>;
451 clock-names = "i2c";
452 status = "disabled";
453 };
455 spi_0: spi@12d20000 {
456 compatible = "samsung,exynos4210-spi";
457 status = "disabled";
458 reg = <0x12d20000 0x100>;
459 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
460 dmas = <&pdma0 5
461 &pdma0 4>;
462 dma-names = "tx", "rx";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
466 clock-names = "spi", "spi_busclk0";
467 pinctrl-names = "default";
468 pinctrl-0 = <&spi0_bus>;
469 };
471 spi_1: spi@12d30000 {
472 compatible = "samsung,exynos4210-spi";
473 status = "disabled";
474 reg = <0x12d30000 0x100>;
475 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
476 dmas = <&pdma1 5
477 &pdma1 4>;
478 dma-names = "tx", "rx";
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
482 clock-names = "spi", "spi_busclk0";
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi1_bus>;
485 };
487 spi_2: spi@12d40000 {
488 compatible = "samsung,exynos4210-spi";
489 status = "disabled";
490 reg = <0x12d40000 0x100>;
491 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
492 dmas = <&pdma0 7
493 &pdma0 6>;
494 dma-names = "tx", "rx";
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
498 clock-names = "spi", "spi_busclk0";
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi2_bus>;
501 };
503 mmc_0: mmc@12200000 {
504 compatible = "samsung,exynos5250-dw-mshc";
505 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 reg = <0x12200000 0x1000>;
509 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
510 clock-names = "biu", "ciu";
511 fifo-depth = <0x80>;
512 status = "disabled";
513 };
515 mmc_1: mmc@12210000 {
516 compatible = "samsung,exynos5250-dw-mshc";
517 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x12210000 0x1000>;
521 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
522 clock-names = "biu", "ciu";
523 fifo-depth = <0x80>;
524 status = "disabled";
525 };
527 mmc_2: mmc@12220000 {
528 compatible = "samsung,exynos5250-dw-mshc";
529 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x12220000 0x1000>;
533 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
534 clock-names = "biu", "ciu";
535 fifo-depth = <0x80>;
536 status = "disabled";
537 };
539 mmc_3: mmc@12230000 {
540 compatible = "samsung,exynos5250-dw-mshc";
541 reg = <0x12230000 0x1000>;
542 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
546 clock-names = "biu", "ciu";
547 fifo-depth = <0x80>;
548 status = "disabled";
549 };
551 i2s0: i2s@3830000 {
552 compatible = "samsung,s5pv210-i2s";
553 status = "disabled";
554 reg = <0x03830000 0x100>;
555 dmas = <&pdma0 10
556 &pdma0 9
557 &pdma0 8>;
558 dma-names = "tx", "rx", "tx-sec";
559 clocks = <&clock_audss EXYNOS_I2S_BUS>,
560 <&clock_audss EXYNOS_I2S_BUS>,
561 <&clock_audss EXYNOS_SCLK_I2S>;
562 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
563 samsung,idma-addr = <0x03000000>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2s0_bus>;
566 power-domains = <&pd_mau>;
567 #clock-cells = <1>;
568 #sound-dai-cells = <1>;
569 };
571 i2s1: i2s@12d60000 {
572 compatible = "samsung,s3c6410-i2s";
573 status = "disabled";
574 reg = <0x12D60000 0x100>;
575 dmas = <&pdma1 12
576 &pdma1 11>;
577 dma-names = "tx", "rx";
578 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
579 clock-names = "iis", "i2s_opclk0";
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2s1_bus>;
582 power-domains = <&pd_mau>;
583 #sound-dai-cells = <1>;
584 };
586 i2s2: i2s@12d70000 {
587 compatible = "samsung,s3c6410-i2s";
588 status = "disabled";
589 reg = <0x12D70000 0x100>;
590 dmas = <&pdma0 12
591 &pdma0 11>;
592 dma-names = "tx", "rx";
593 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
594 clock-names = "iis", "i2s_opclk0";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2s2_bus>;
597 power-domains = <&pd_mau>;
598 #sound-dai-cells = <1>;
599 };
601 usb_dwc3 {
602 compatible = "samsung,exynos5250-dwusb3";
603 clocks = <&clock CLK_USB3>;
604 clock-names = "usbdrd30";
605 #address-cells = <1>;
606 #size-cells = <1>;
607 ranges;
609 usbdrd_dwc3: dwc3@12000000 {
610 compatible = "synopsys,dwc3";
611 reg = <0x12000000 0x10000>;
612 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
613 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
614 phy-names = "usb2-phy", "usb3-phy";
615 };
616 };
618 usbdrd_phy: phy@12100000 {
619 compatible = "samsung,exynos5250-usbdrd-phy";
620 reg = <0x12100000 0x100>;
621 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
622 clock-names = "phy", "ref";
623 samsung,pmu-syscon = <&pmu_system_controller>;
624 #phy-cells = <1>;
625 };
627 ehci: usb@12110000 {
628 compatible = "samsung,exynos4210-ehci";
629 reg = <0x12110000 0x100>;
630 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clock CLK_USB2>;
633 clock-names = "usbhost";
634 #address-cells = <1>;
635 #size-cells = <0>;
636 port@0 {
637 reg = <0>;
638 phys = <&usb2_phy_gen 1>;
639 };
640 };
642 ohci: usb@12120000 {
643 compatible = "samsung,exynos4210-ohci";
644 reg = <0x12120000 0x100>;
645 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&clock CLK_USB2>;
648 clock-names = "usbhost";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 port@0 {
652 reg = <0>;
653 phys = <&usb2_phy_gen 1>;
654 };
655 };
657 usb2_phy_gen: phy@12130000 {
658 compatible = "samsung,exynos5250-usb2-phy";
659 reg = <0x12130000 0x100>;
660 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
661 clock-names = "phy", "ref";
662 #phy-cells = <1>;
663 samsung,sysreg-phandle = <&sysreg_system_controller>;
664 samsung,pmureg-phandle = <&pmu_system_controller>;
665 };
667 amba {
668 #address-cells = <1>;
669 #size-cells = <1>;
670 compatible = "simple-bus";
671 interrupt-parent = <&gic>;
672 ranges;
674 pdma0: pdma@121a0000 {
675 compatible = "arm,pl330", "arm,primecell";
676 reg = <0x121A0000 0x1000>;
677 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clock CLK_PDMA0>;
679 clock-names = "apb_pclk";
680 #dma-cells = <1>;
681 #dma-channels = <8>;
682 #dma-requests = <32>;
683 };
685 pdma1: pdma@121b0000 {
686 compatible = "arm,pl330", "arm,primecell";
687 reg = <0x121B0000 0x1000>;
688 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clock CLK_PDMA1>;
690 clock-names = "apb_pclk";
691 #dma-cells = <1>;
692 #dma-channels = <8>;
693 #dma-requests = <32>;
694 };
696 mdma0: mdma@10800000 {
697 compatible = "arm,pl330", "arm,primecell";
698 reg = <0x10800000 0x1000>;
699 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clock CLK_MDMA0>;
701 clock-names = "apb_pclk";
702 #dma-cells = <1>;
703 #dma-channels = <8>;
704 #dma-requests = <1>;
705 };
707 mdma1: mdma@11c10000 {
708 compatible = "arm,pl330", "arm,primecell";
709 reg = <0x11C10000 0x1000>;
710 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clock CLK_MDMA1>;
712 clock-names = "apb_pclk";
713 #dma-cells = <1>;
714 #dma-channels = <8>;
715 #dma-requests = <1>;
716 };
717 };
719 gsc_0: gsc@13e00000 {
720 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
721 reg = <0x13e00000 0x1000>;
722 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
723 power-domains = <&pd_gsc>;
724 clocks = <&clock CLK_GSCL0>;
725 clock-names = "gscl";
726 iommus = <&sysmmu_gsc0>;
727 };
729 gsc_1: gsc@13e10000 {
730 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
731 reg = <0x13e10000 0x1000>;
732 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
733 power-domains = <&pd_gsc>;
734 clocks = <&clock CLK_GSCL1>;
735 clock-names = "gscl";
736 iommus = <&sysmmu_gsc1>;
737 };
739 gsc_2: gsc@13e20000 {
740 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
741 reg = <0x13e20000 0x1000>;
742 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
743 power-domains = <&pd_gsc>;
744 clocks = <&clock CLK_GSCL2>;
745 clock-names = "gscl";
746 iommus = <&sysmmu_gsc2>;
747 };
749 gsc_3: gsc@13e30000 {
750 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
751 reg = <0x13e30000 0x1000>;
752 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
753 power-domains = <&pd_gsc>;
754 clocks = <&clock CLK_GSCL3>;
755 clock-names = "gscl";
756 iommus = <&sysmmu_gsc3>;
757 };
759 hdmi: hdmi@14530000 {
760 compatible = "samsung,exynos4212-hdmi";
761 reg = <0x14530000 0x70000>;
762 power-domains = <&pd_disp1>;
763 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
765 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
766 <&clock CLK_MOUT_HDMI>;
767 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
768 "sclk_hdmiphy", "mout_hdmi";
769 samsung,syscon-phandle = <&pmu_system_controller>;
770 phy = <&hdmiphy>;
771 #sound-dai-cells = <0>;
772 status = "disabled";
773 };
775 hdmicec: cec@101b0000 {
776 compatible = "samsung,s5p-cec";
777 reg = <0x101B0000 0x200>;
778 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clock CLK_HDMI_CEC>;
780 clock-names = "hdmicec";
781 samsung,syscon-phandle = <&pmu_system_controller>;
782 hdmi-phandle = <&hdmi>;
783 pinctrl-names = "default";
784 pinctrl-0 = <&hdmi_cec>;
785 status = "disabled";
786 };
788 mixer: mixer@14450000 {
789 compatible = "samsung,exynos5250-mixer";
790 reg = <0x14450000 0x10000>;
791 power-domains = <&pd_disp1>;
792 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
794 <&clock CLK_SCLK_HDMI>;
795 clock-names = "mixer", "hdmi", "sclk_hdmi";
796 iommus = <&sysmmu_tv>;
797 status = "disabled";
798 };
800 dp_phy: video-phy {
801 compatible = "samsung,exynos5250-dp-video-phy";
802 samsung,pmu-syscon = <&pmu_system_controller>;
803 #phy-cells = <0>;
804 };
806 mipi_phy: video-phy@10040710 {
807 compatible = "samsung,s5pv210-mipi-video-phy";
808 reg = <0x10040710 0x100>;
809 #phy-cells = <1>;
810 syscon = <&pmu_system_controller>;
811 };
813 dsi_0: dsi@14500000 {
814 compatible = "samsung,exynos4210-mipi-dsi";
815 reg = <0x14500000 0x10000>;
816 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
817 samsung,power-domain = <&pd_disp1>;
818 phys = <&mipi_phy 3>;
819 phy-names = "dsim";
820 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
821 clock-names = "bus_clk", "sclk_mipi";
822 status = "disabled";
823 #address-cells = <1>;
824 #size-cells = <0>;
825 };
827 adc: adc@12d10000 {
828 compatible = "samsung,exynos-adc-v1";
829 reg = <0x12D10000 0x100>;
830 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clock CLK_ADC>;
832 clock-names = "adc";
833 #io-channel-cells = <1>;
834 io-channel-ranges;
835 samsung,syscon-phandle = <&pmu_system_controller>;
836 status = "disabled";
837 };
839 sysmmu_g2d: sysmmu@10a60000 {
840 compatible = "samsung,exynos-sysmmu";
841 reg = <0x10A60000 0x1000>;
842 interrupt-parent = <&combiner>;
843 interrupts = <24 5>;
844 clock-names = "sysmmu", "master";
845 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
846 #iommu-cells = <0>;
847 };
849 sysmmu_mfc_r: sysmmu@11200000 {
850 compatible = "samsung,exynos-sysmmu";
851 reg = <0x11200000 0x1000>;
852 interrupt-parent = <&combiner>;
853 interrupts = <6 2>;
854 power-domains = <&pd_mfc>;
855 clock-names = "sysmmu", "master";
856 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
857 #iommu-cells = <0>;
858 };
860 sysmmu_mfc_l: sysmmu@11210000 {
861 compatible = "samsung,exynos-sysmmu";
862 reg = <0x11210000 0x1000>;
863 interrupt-parent = <&combiner>;
864 interrupts = <8 5>;
865 power-domains = <&pd_mfc>;
866 clock-names = "sysmmu", "master";
867 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
868 #iommu-cells = <0>;
869 };
871 sysmmu_rotator: sysmmu@11d40000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x11D40000 0x1000>;
874 interrupt-parent = <&combiner>;
875 interrupts = <4 0>;
876 clock-names = "sysmmu", "master";
877 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
878 #iommu-cells = <0>;
879 };
881 sysmmu_jpeg: sysmmu@11f20000 {
882 compatible = "samsung,exynos-sysmmu";
883 reg = <0x11F20000 0x1000>;
884 interrupt-parent = <&combiner>;
885 interrupts = <4 2>;
886 power-domains = <&pd_gsc>;
887 clock-names = "sysmmu", "master";
888 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
889 #iommu-cells = <0>;
890 };
892 sysmmu_fimc_isp: sysmmu@13260000 {
893 compatible = "samsung,exynos-sysmmu";
894 reg = <0x13260000 0x1000>;
895 interrupt-parent = <&combiner>;
896 interrupts = <10 6>;
897 clock-names = "sysmmu";
898 clocks = <&clock CLK_SMMU_FIMC_ISP>;
899 #iommu-cells = <0>;
900 };
902 sysmmu_fimc_drc: sysmmu@13270000 {
903 compatible = "samsung,exynos-sysmmu";
904 reg = <0x13270000 0x1000>;
905 interrupt-parent = <&combiner>;
906 interrupts = <11 6>;
907 clock-names = "sysmmu";
908 clocks = <&clock CLK_SMMU_FIMC_DRC>;
909 #iommu-cells = <0>;
910 };
912 sysmmu_fimc_fd: sysmmu@132a0000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x132A0000 0x1000>;
915 interrupt-parent = <&combiner>;
916 interrupts = <5 0>;
917 clock-names = "sysmmu";
918 clocks = <&clock CLK_SMMU_FIMC_FD>;
919 #iommu-cells = <0>;
920 };
922 sysmmu_fimc_scc: sysmmu@13280000 {
923 compatible = "samsung,exynos-sysmmu";
924 reg = <0x13280000 0x1000>;
925 interrupt-parent = <&combiner>;
926 interrupts = <5 2>;
927 clock-names = "sysmmu";
928 clocks = <&clock CLK_SMMU_FIMC_SCC>;
929 #iommu-cells = <0>;
930 };
932 sysmmu_fimc_scp: sysmmu@13290000 {
933 compatible = "samsung,exynos-sysmmu";
934 reg = <0x13290000 0x1000>;
935 interrupt-parent = <&combiner>;
936 interrupts = <3 6>;
937 clock-names = "sysmmu";
938 clocks = <&clock CLK_SMMU_FIMC_SCP>;
939 #iommu-cells = <0>;
940 };
942 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
943 compatible = "samsung,exynos-sysmmu";
944 reg = <0x132B0000 0x1000>;
945 interrupt-parent = <&combiner>;
946 interrupts = <5 4>;
947 clock-names = "sysmmu";
948 clocks = <&clock CLK_SMMU_FIMC_MCU>;
949 #iommu-cells = <0>;
950 };
952 sysmmu_fimc_odc: sysmmu@132c0000 {
953 compatible = "samsung,exynos-sysmmu";
954 reg = <0x132C0000 0x1000>;
955 interrupt-parent = <&combiner>;
956 interrupts = <11 0>;
957 clock-names = "sysmmu";
958 clocks = <&clock CLK_SMMU_FIMC_ODC>;
959 #iommu-cells = <0>;
960 };
962 sysmmu_fimc_dis0: sysmmu@132d0000 {
963 compatible = "samsung,exynos-sysmmu";
964 reg = <0x132D0000 0x1000>;
965 interrupt-parent = <&combiner>;
966 interrupts = <10 4>;
967 clock-names = "sysmmu";
968 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
969 #iommu-cells = <0>;
970 };
972 sysmmu_fimc_dis1: sysmmu@132e0000 {
973 compatible = "samsung,exynos-sysmmu";
974 reg = <0x132E0000 0x1000>;
975 interrupt-parent = <&combiner>;
976 interrupts = <9 4>;
977 clock-names = "sysmmu";
978 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
979 #iommu-cells = <0>;
980 };
982 sysmmu_fimc_3dnr: sysmmu@132f0000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x132F0000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <5 6>;
987 clock-names = "sysmmu";
988 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
989 #iommu-cells = <0>;
990 };
992 sysmmu_fimc_lite0: sysmmu@13c40000 {
993 compatible = "samsung,exynos-sysmmu";
994 reg = <0x13C40000 0x1000>;
995 interrupt-parent = <&combiner>;
996 interrupts = <3 4>;
997 power-domains = <&pd_gsc>;
998 clock-names = "sysmmu", "master";
999 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1000 #iommu-cells = <0>;
1001 };
1003 sysmmu_fimc_lite1: sysmmu@13c50000 {
1004 compatible = "samsung,exynos-sysmmu";
1005 reg = <0x13C50000 0x1000>;
1006 interrupt-parent = <&combiner>;
1007 interrupts = <24 1>;
1008 power-domains = <&pd_gsc>;
1009 clock-names = "sysmmu", "master";
1010 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1011 #iommu-cells = <0>;
1012 };
1014 sysmmu_gsc0: sysmmu@13e80000 {
1015 compatible = "samsung,exynos-sysmmu";
1016 reg = <0x13E80000 0x1000>;
1017 interrupt-parent = <&combiner>;
1018 interrupts = <2 0>;
1019 power-domains = <&pd_gsc>;
1020 clock-names = "sysmmu", "master";
1021 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1022 #iommu-cells = <0>;
1023 };
1025 sysmmu_gsc1: sysmmu@13e90000 {
1026 compatible = "samsung,exynos-sysmmu";
1027 reg = <0x13E90000 0x1000>;
1028 interrupt-parent = <&combiner>;
1029 interrupts = <2 2>;
1030 power-domains = <&pd_gsc>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1033 #iommu-cells = <0>;
1034 };
1036 sysmmu_gsc2: sysmmu@13ea0000 {
1037 compatible = "samsung,exynos-sysmmu";
1038 reg = <0x13EA0000 0x1000>;
1039 interrupt-parent = <&combiner>;
1040 interrupts = <2 4>;
1041 power-domains = <&pd_gsc>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1044 #iommu-cells = <0>;
1045 };
1047 sysmmu_gsc3: sysmmu@13eb0000 {
1048 compatible = "samsung,exynos-sysmmu";
1049 reg = <0x13EB0000 0x1000>;
1050 interrupt-parent = <&combiner>;
1051 interrupts = <2 6>;
1052 power-domains = <&pd_gsc>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1055 #iommu-cells = <0>;
1056 };
1058 sysmmu_fimd1: sysmmu@14640000 {
1059 compatible = "samsung,exynos-sysmmu";
1060 reg = <0x14640000 0x1000>;
1061 interrupt-parent = <&combiner>;
1062 interrupts = <3 2>;
1063 power-domains = <&pd_disp1>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1066 #iommu-cells = <0>;
1067 };
1069 sysmmu_tv: sysmmu@14650000 {
1070 compatible = "samsung,exynos-sysmmu";
1071 reg = <0x14650000 0x1000>;
1072 interrupt-parent = <&combiner>;
1073 interrupts = <7 4>;
1074 power-domains = <&pd_disp1>;
1075 clock-names = "sysmmu", "master";
1076 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1077 #iommu-cells = <0>;
1078 };
1079 };
1081 thermal-zones {
1082 cpu_thermal: cpu-thermal {
1083 polling-delay-passive = <0>;
1084 polling-delay = <0>;
1085 thermal-sensors = <&tmu 0>;
1087 cooling-maps {
1088 map0 {
1089 /* Corresponds to 800MHz at freq_table */
1090 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1091 };
1092 map1 {
1093 /* Corresponds to 200MHz at freq_table */
1094 cooling-device = <&cpu0 15 15>,
1095 <&cpu1 15 15>;
1096 };
1097 };
1098 };
1099 };
1100 };
1102 &dp {
1103 power-domains = <&pd_disp1>;
1104 clocks = <&clock CLK_DP>;
1105 clock-names = "dp";
1106 phys = <&dp_phy>;
1107 phy-names = "dp";
1108 };
1110 &fimd {
1111 power-domains = <&pd_disp1>;
1112 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1113 clock-names = "sclk_fimd", "fimd";
1114 iommus = <&sysmmu_fimd1>;
1115 };
1117 &g2d {
1118 iommus = <&sysmmu_g2d>;
1119 clocks = <&clock CLK_G2D>;
1120 clock-names = "fimg2d";
1121 status = "okay";
1122 };
1124 &i2c_0 {
1125 clocks = <&clock CLK_I2C0>;
1126 clock-names = "i2c";
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&i2c0_bus>;
1129 };
1131 &i2c_1 {
1132 clocks = <&clock CLK_I2C1>;
1133 clock-names = "i2c";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&i2c1_bus>;
1136 };
1138 &i2c_2 {
1139 clocks = <&clock CLK_I2C2>;
1140 clock-names = "i2c";
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&i2c2_bus>;
1143 };
1145 &i2c_3 {
1146 clocks = <&clock CLK_I2C3>;
1147 clock-names = "i2c";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&i2c3_bus>;
1150 };
1152 &prng {
1153 clocks = <&clock CLK_SSS>;
1154 clock-names = "secss";
1155 };
1157 &pwm {
1158 clocks = <&clock CLK_PWM>;
1159 clock-names = "timers";
1160 };
1162 &rtc {
1163 clocks = <&clock CLK_RTC>;
1164 clock-names = "rtc";
1165 interrupt-parent = <&pmu_system_controller>;
1166 status = "disabled";
1167 };
1169 &serial_0 {
1170 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1171 clock-names = "uart", "clk_uart_baud0";
1172 dmas = <&pdma0 13>, <&pdma0 14>;
1173 dma-names = "rx", "tx";
1174 };
1176 &serial_1 {
1177 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1178 clock-names = "uart", "clk_uart_baud0";
1179 dmas = <&pdma1 15>, <&pdma1 16>;
1180 dma-names = "rx", "tx";
1181 };
1183 &serial_2 {
1184 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1185 clock-names = "uart", "clk_uart_baud0";
1186 dmas = <&pdma0 15>, <&pdma0 16>;
1187 dma-names = "rx", "tx";
1188 };
1190 &serial_3 {
1191 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1192 clock-names = "uart", "clk_uart_baud0";
1193 dmas = <&pdma1 17>, <&pdma1 18>;
1194 dma-names = "rx", "tx";
1195 };
1197 &sss {
1198 clocks = <&clock CLK_SSS>;
1199 clock-names = "secss";
1200 };
1202 &trng {
1203 clocks = <&clock CLK_SSS>;
1204 clock-names = "secss";
1205 };
1207 #include "exynos5250-pinctrl.dtsi"
1208 #include "exynos-syscon-restart.dtsi"