arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi

   1 /*
   2  * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include "imx27.dtsi"
  14
  15 / {
  16         model = "Eukrea CPUIMX27";
  17         compatible = "eukrea,cpuimx27", "fsl,imx27";
  18
  19         memory@a0000000 {
  20                 device_type = "memory";
  21                 reg = <0xa0000000 0x04000000>;
  22         };
  23
  24         clk14745600: clk-uart {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <14745600>;
  28         };
  29 };
  30
  31 &fec {
  32         pinctrl-names = "default";
  33         pinctrl-0 = <&pinctrl_fec>;
  34         status = "okay";
  35 };
  36
  37 &i2c1 {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_i2c1>;
  40         status = "okay";
  41
  42         pcf8563@51 {
  43                 compatible = "nxp,pcf8563";
  44                 reg = <0x51>;
  45         };
  46 };
  47
  48 &nfc {
  49         pinctrl-names = "default";
  50         pinctrl-0 = <&pinctrl_nfc>;
  51         nand-bus-width = <8>;
  52         nand-ecc-mode = "hw";
  53         nand-on-flash-bbt;
  54         status = "okay";
  55 };
  56
  57 &owire {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_owire>;
  60         status = "okay";
  61 };
  62
  63 &sdhci2 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_sdhc2>;
  66         bus-width = <4>;
  67         non-removable;
  68         status = "okay";
  69 };
  70
  71 &uart4 {
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_uart4>;
  74         uart-has-rtscts;
  75         status = "okay";
  76 };
  77
  78 &usbh2 {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_usbh2>;
  81         dr_mode = "host";
  82         phy_type = "ulpi";
  83         disable-over-current;
  84         status = "okay";
  85 };
  86
  87 &usbotg {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_usbotg>;
  90         dr_mode = "otg";
  91         phy_type = "ulpi";
  92         disable-over-current;
  93         status = "okay";
  94 };
  95
  96 &weim {
  97         status = "okay";
  98
  99         nor: nor@0,0 {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "cfi-flash";
 103                 reg = <0 0x00000000 0x04000000>;
 104                 bank-width = <2>;
 105                 linux,mtd-name = "physmap-flash.0";
 106                 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
 107         };
 108
 109         uart8250@3,200000 {
 110                 pinctrl-names = "default";
 111                 pinctrl-0 = <&pinctrl_uart8250_1>;
 112                 compatible = "ns8250";
 113                 clocks = <&clk14745600>;
 114                 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
 115                 interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
 116                 reg = <3 0x200000 0x1000>;
 117                 reg-shift = <1>;
 118                 reg-io-width = <1>;
 119                 no-loopback-test;
 120         };
 121
 122         uart8250@3,400000 {
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_uart8250_2>;
 125                 compatible = "ns8250";
 126                 clocks = <&clk14745600>;
 127                 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
 128                 interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
 129                 reg = <3 0x400000 0x1000>;
 130                 reg-shift = <1>;
 131                 reg-io-width = <1>;
 132                 no-loopback-test;
 133         };
 134
 135         uart8250@3,800000 {
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&pinctrl_uart8250_3>;
 138                 compatible = "ns8250";
 139                 clocks = <&clk14745600>;
 140                 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
 141                 interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
 142                 reg = <3 0x800000 0x1000>;
 143                 reg-shift = <1>;
 144                 reg-io-width = <1>;
 145                 no-loopback-test;
 146         };
 147
 148         uart8250@3,1000000 {
 149                 pinctrl-names = "default";
 150                 pinctrl-0 = <&pinctrl_uart8250_4>;
 151                 compatible = "ns8250";
 152                 clocks = <&clk14745600>;
 153                 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
 154                 interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
 155                 reg = <3 0x1000000 0x1000>;
 156                 reg-shift = <1>;
 157                 reg-io-width = <1>;
 158                 no-loopback-test;
 159         };
 160 };
 161
 162 &iomuxc {
 163         imx27-eukrea-cpuimx27 {
 164                 pinctrl_fec: fecgrp {
 165                         fsl,pins = <
 166                                 MX27_PAD_SD3_CMD__FEC_TXD0              0x0
 167                                 MX27_PAD_SD3_CLK__FEC_TXD1              0x0
 168                                 MX27_PAD_ATA_DATA0__FEC_TXD2            0x0
 169                                 MX27_PAD_ATA_DATA1__FEC_TXD3            0x0
 170                                 MX27_PAD_ATA_DATA2__FEC_RX_ER           0x0
 171                                 MX27_PAD_ATA_DATA3__FEC_RXD1            0x0
 172                                 MX27_PAD_ATA_DATA4__FEC_RXD2            0x0
 173                                 MX27_PAD_ATA_DATA5__FEC_RXD3            0x0
 174                                 MX27_PAD_ATA_DATA6__FEC_MDIO            0x0
 175                                 MX27_PAD_ATA_DATA7__FEC_MDC             0x0
 176                                 MX27_PAD_ATA_DATA8__FEC_CRS             0x0
 177                                 MX27_PAD_ATA_DATA9__FEC_TX_CLK          0x0
 178                                 MX27_PAD_ATA_DATA10__FEC_RXD0           0x0
 179                                 MX27_PAD_ATA_DATA11__FEC_RX_DV          0x0
 180                                 MX27_PAD_ATA_DATA12__FEC_RX_CLK         0x0
 181                                 MX27_PAD_ATA_DATA13__FEC_COL            0x0
 182                                 MX27_PAD_ATA_DATA14__FEC_TX_ER          0x0
 183                                 MX27_PAD_ATA_DATA15__FEC_TX_EN          0x0
 184                         >;
 185                 };
 186
 187                 pinctrl_i2c1: i2c1grp {
 188                         fsl,pins = <
 189                                 MX27_PAD_I2C_DATA__I2C_DATA             0x0
 190                                 MX27_PAD_I2C_CLK__I2C_CLK               0x0
 191                         >;
 192                 };
 193
 194                 pinctrl_nfc: nfcgrp {
 195                         fsl,pins = <
 196                                 MX27_PAD_NFRB__NFRB                     0x0
 197                                 MX27_PAD_NFCLE__NFCLE                   0x0
 198                                 MX27_PAD_NFWP_B__NFWP_B                 0x0
 199                                 MX27_PAD_NFCE_B__NFCE_B                 0x0
 200                                 MX27_PAD_NFALE__NFALE                   0x0
 201                                 MX27_PAD_NFRE_B__NFRE_B                 0x0
 202                                 MX27_PAD_NFWE_B__NFWE_B                 0x0
 203                         >;
 204                 };
 205
 206                 pinctrl_owire: owiregrp {
 207                         fsl,pins = <
 208                                 MX27_PAD_RTCK__OWIRE                    0x0
 209                         >;
 210                 };
 211
 212                 pinctrl_sdhc2: sdhc2grp {
 213                         fsl,pins = <
 214                                 MX27_PAD_SD2_CLK__SD2_CLK               0x0
 215                                 MX27_PAD_SD2_CMD__SD2_CMD               0x0
 216                                 MX27_PAD_SD2_D0__SD2_D0                 0x0
 217                                 MX27_PAD_SD2_D1__SD2_D1                 0x0
 218                                 MX27_PAD_SD2_D2__SD2_D2                 0x0
 219                                 MX27_PAD_SD2_D3__SD2_D3                 0x0
 220                         >;
 221                 };
 222
 223                 pinctrl_uart4: uart4grp {
 224                         fsl,pins = <
 225                                 MX27_PAD_USBH1_TXDM__UART4_TXD          0x0
 226                                 MX27_PAD_USBH1_RXDP__UART4_RXD          0x0
 227                                 MX27_PAD_USBH1_TXDP__UART4_CTS          0x0
 228                                 MX27_PAD_USBH1_FS__UART4_RTS            0x0
 229                         >;
 230                 };
 231
 232                 pinctrl_uart8250_1: uart82501grp {
 233                         fsl,pins = <
 234                                 MX27_PAD_USB_PWR__GPIO2_23              0x0
 235                         >;
 236                 };
 237
 238                 pinctrl_uart8250_2: uart82502grp {
 239                         fsl,pins = <
 240                                 MX27_PAD_USBH1_SUSP__GPIO2_22           0x0
 241                         >;
 242                 };
 243
 244                 pinctrl_uart8250_3: uart82503grp {
 245                         fsl,pins = <
 246                                 MX27_PAD_USBH1_OE_B__GPIO2_27           0x0
 247                         >;
 248                 };
 249
 250                 pinctrl_uart8250_4: uart82504grp {
 251                         fsl,pins = <
 252                                 MX27_PAD_USBH1_RXDM__GPIO2_30           0x0
 253                         >;
 254                 };
 255
 256                 pinctrl_usbh2: usbh2grp {
 257                         fsl,pins = <
 258                                 MX27_PAD_USBH2_CLK__USBH2_CLK           0x0
 259                                 MX27_PAD_USBH2_DIR__USBH2_DIR           0x0
 260                                 MX27_PAD_USBH2_NXT__USBH2_NXT           0x0
 261                                 MX27_PAD_USBH2_STP__USBH2_STP           0x0
 262                                 MX27_PAD_CSPI2_SCLK__USBH2_DATA0        0x0
 263                                 MX27_PAD_CSPI2_MOSI__USBH2_DATA1        0x0
 264                                 MX27_PAD_CSPI2_MISO__USBH2_DATA2        0x0
 265                                 MX27_PAD_CSPI2_SS1__USBH2_DATA3         0x0
 266                                 MX27_PAD_CSPI2_SS2__USBH2_DATA4         0x0
 267                                 MX27_PAD_CSPI1_SS2__USBH2_DATA5         0x0
 268                                 MX27_PAD_CSPI2_SS0__USBH2_DATA6         0x0
 269                                 MX27_PAD_USBH2_DATA7__USBH2_DATA7       0x0
 270                         >;
 271                 };
 272
 273                 pinctrl_usbotg: usbotggrp {
 274                         fsl,pins = <
 275                                 MX27_PAD_USBOTG_CLK__USBOTG_CLK         0x0
 276                                 MX27_PAD_USBOTG_DIR__USBOTG_DIR         0x0
 277                                 MX27_PAD_USBOTG_NXT__USBOTG_NXT         0x0
 278                                 MX27_PAD_USBOTG_STP__USBOTG_STP         0x0
 279                                 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0     0x0
 280                                 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1     0x0
 281                                 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2     0x0
 282                                 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3     0x0
 283                                 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4     0x0
 284                                 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5     0x0
 285                                 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6     0x0
 286                                 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7     0x0
 287                         >;
 288                 };
 289         };
 290 };