arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2019 Logic PD, Inc.
   4
   5 / {
   6         keyboard {
   7                 compatible = "gpio-keys";
   8
   9                 btn0 {
  10                         gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
  11                         label = "btn0";
  12                         linux,code = <KEY_WAKEUP>;
  13                         debounce-interval = <10>;
  14                         wakeup-source;
  15                 };
  16
  17                 btn1 {
  18                         gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
  19                         label = "btn1";
  20                         linux,code = <KEY_WAKEUP>;
  21                         debounce-interval = <10>;
  22                         wakeup-source;
  23                 };
  24
  25                 btn2 {
  26                         gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
  27                         label = "btn2";
  28                         linux,code = <KEY_WAKEUP>;
  29                         debounce-interval = <10>;
  30                         wakeup-source;
  31                 };
  32
  33                 btn3 {
  34                         gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
  35                         label = "btn3";
  36                         linux,code = <KEY_WAKEUP>;
  37                         debounce-interval = <10>;
  38                         wakeup-source;
  39                 };
  40
  41         };
  42
  43         leds {
  44                 compatible = "gpio-leds";
  45
  46                 gen-led0 {
  47                         label = "led0";
  48                         pinctrl-names = "default";
  49                         pinctrl-0 = <&pinctrl_led0>;
  50                         gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  51                         linux,default-trigger = "cpu0";
  52                 };
  53
  54                 gen-led1 {
  55                         label = "led1";
  56                         gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
  57                 };
  58
  59                 gen-led2 {
  60                         label = "led2";
  61                         gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
  62                         linux,default-trigger = "heartbeat";
  63                 };
  64
  65                 gen-led3 {
  66                         label = "led3";
  67                         gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
  68                         linux,default-trigger = "default-on";
  69                 };
  70         };
  71
  72         reg_usb_otg_vbus: regulator-otg-vbus {
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_reg_usb_otg>;
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "usb_otg_vbus";
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  80                 enable-active-high;
  81         };
  82
  83         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "usb_h1_vbus";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  91                 enable-active-high;
  92         };
  93
  94         reg_3v3: regulator-3v3 {
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_reg_3v3>;
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "reg_3v3";
  99                 regulator-min-microvolt = <3300000>;
 100                 regulator-max-microvolt = <3300000>;
 101                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 102                 enable-active-high;
 103                 regulator-always-on;
 104         };
 105
 106         reg_enet: regulator-ethernet {
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&pinctrl_reg_enet>;
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "ethernet-supply";
 111                 regulator-min-microvolt = <3300000>;
 112                 regulator-max-microvolt = <3300000>;
 113                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 114                 startup-delay-us = <70000>;
 115                 enable-active-high;
 116                 vin-supply = <&sw4_reg>;
 117         };
 118
 119         reg_audio: regulator-audio {
 120                 pinctrl-names = "default";
 121                 pinctrl-0 = <&pinctrl_reg_audio>;
 122                 compatible = "regulator-fixed";
 123                 regulator-name = "3v3_aud";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 127                 enable-active-high;
 128                 vin-supply = <&reg_3v3>;
 129         };
 130
 131         reg_hdmi: regulator-hdmi {
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_reg_hdmi>;
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "hdmi-supply";
 136                 regulator-min-microvolt = <3300000>;
 137                 regulator-max-microvolt = <3300000>;
 138                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 139                 enable-active-high;
 140                 vin-supply = <&reg_3v3>;
 141         };
 142
 143         reg_uart3: regulator-uart3 {
 144                 pinctrl-names = "default";
 145                 pinctrl-0 = <&pinctrl_reg_uart3>;
 146                 compatible = "regulator-fixed";
 147                 regulator-name = "uart3-supply";
 148                 gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 149                 enable-active-high;
 150                 regulator-always-on;
 151                 vin-supply = <&reg_3v3>;
 152         };
 153
 154         reg_1v8: regulator-1v8 {
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&pinctrl_reg_1v8>;
 157                 compatible = "regulator-fixed";
 158                 regulator-name = "1v8-supply";
 159                 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
 160                 enable-active-high;
 161                 regulator-always-on;
 162                 vin-supply = <&reg_3v3>;
 163         };
 164
 165         reg_pcie: regulator-pcie {
 166                 compatible = "regulator-fixed";
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&pinctrl_reg_pcie>;
 169                 regulator-name = "mpcie_3v3";
 170                 regulator-min-microvolt = <3300000>;
 171                 regulator-max-microvolt = <3300000>;
 172                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 173                 enable-active-high;
 174         };
 175
 176         reg_mipi: regulator-mipi {
 177                 compatible = "regulator-fixed";
 178                 pinctrl-names = "default";
 179                 pinctrl-0 = <&pinctrl_reg_mipi>;
 180                 regulator-name = "mipi_pwr_en";
 181                 regulator-min-microvolt = <2800000>;
 182                 regulator-max-microvolt = <2800000>;
 183                 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 184                 enable-active-high;
 185         };
 186
 187         sound {
 188                 compatible = "fsl,imx-audio-wm8962";
 189                 model = "wm8962-audio";
 190                 ssi-controller = <&ssi2>;
 191                 audio-codec = <&wm8962>;
 192                 audio-routing =
 193                         "Headphone Jack", "HPOUTL",
 194                         "Headphone Jack", "HPOUTR",
 195                         "Ext Spk", "SPKOUTL",
 196                         "Ext Spk", "SPKOUTR",
 197                         "AMIC", "MICBIAS",
 198                         "IN3R", "AMIC";
 199                 mux-int-port = <2>;
 200                 mux-ext-port = <4>;
 201         };
 202 };
 203
 204 &audmux {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_audmux>;
 207         status = "okay";
 208 };
 209
 210 &ecspi1 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_ecspi1>;
 213         status = "disabled";
 214 };
 215
 216 &fec {
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&pinctrl_enet>;
 219         phy-mode = "rgmii";
 220         phy-reset-duration = <10>;
 221         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
 222         phy-supply = <&reg_enet>;
 223         interrupt-parent = <&gpio1>;
 224         interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 225         status = "okay";
 226 };
 227
 228 &i2c1 {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_i2c1>;
 231         clock-frequency = <400000>;
 232         status = "okay";
 233
 234         wm8962: audio-codec@1a {
 235                 compatible = "wlf,wm8962";
 236                 reg = <0x1a>;
 237                 clocks = <&clks IMX6QDL_CLK_CKO>;
 238                 clock-names = "xclk";
 239                 DCVDD-supply = <&reg_audio>;
 240                 DBVDD-supply = <&reg_audio>;
 241                 AVDD-supply = <&reg_audio>;
 242                 CPVDD-supply = <&reg_audio>;
 243                 MICVDD-supply = <&reg_audio>;
 244                 PLLVDD-supply = <&reg_audio>;
 245                 SPKVDD1-supply = <&reg_audio>;
 246                 SPKVDD2-supply = <&reg_audio>;
 247                 gpio-cfg = <
 248                         0x0000 /* 0:Default */
 249                         0x0000 /* 1:Default */
 250                         0x0013 /* 2:FN_DMICCLK */
 251                         0x0000 /* 3:Default */
 252                         0x8014 /* 4:FN_DMICCDAT */
 253                         0x0000 /* 5:Default */
 254                 >;
 255         };
 256 };
 257
 258 &i2c3 {
 259         ov5640: camera@10 {
 260                 compatible = "ovti,ov5640";
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&pinctrl_ov5640>;
 263                 reg = <0x10>;
 264                 clocks = <&clks IMX6QDL_CLK_CKO>;
 265                 clock-names = "xclk";
 266                 DOVDD-supply = <&reg_mipi>;
 267                 AVDD-supply = <&reg_mipi>;
 268                 DVDD-supply = <&reg_mipi>;
 269                 reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 270                 powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
 271
 272                 port {
 273                         ov5640_to_mipi_csi2: endpoint {
 274                                 remote-endpoint = <&mipi_csi2_in>;
 275                                 clock-lanes = <0>;
 276                                 data-lanes = <1 2>;
 277                         };
 278                 };
 279         };
 280
 281         pcf8575: gpio@20 {
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&pinctrl_pcf8574>;
 284                 compatible = "nxp,pcf8575";
 285                 reg = <0x20>;
 286                 interrupt-parent = <&gpio6>;
 287                 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 288                 gpio-controller;
 289                 #gpio-cells = <2>;
 290                 interrupt-controller;
 291                 #interrupt-cells = <2>;
 292                 lines-initial-states = <0x0710>;
 293                 wakeup-source;
 294         };
 295 };
 296
 297 &ipu1_csi1_from_mipi_vc1 {
 298         clock-lanes = <0>;
 299         data-lanes = <1 2>;
 300 };
 301
 302 &mipi_csi {
 303         status = "okay";
 304
 305         port@0 {
 306                 reg = <0>;
 307
 308                 mipi_csi2_in: endpoint {
 309                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 310                         clock-lanes = <0>;
 311                         data-lanes = <1 2>;
 312                 };
 313         };
 314 };
 315
 316 &pcie {
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_pcie>;
 319         reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
 320         vpcie-supply = <&reg_pcie>;
 321         status = "okay";
 322 };
 323
 324 &pwm3 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_pwm3>;
 327 };
 328
 329 &ssi2 {
 330         status = "okay";
 331 };
 332
 333 &uart3 {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&pinctrl_uart3>;
 336         status = "okay";
 337 };
 338
 339 &usbh1 {
 340         vbus-supply = <&reg_usb_h1_vbus>;
 341         status = "okay";
 342 };
 343
 344 &usbotg {
 345         vbus-supply = <&reg_usb_otg_vbus>;
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_usbotg>;
 348         disable-over-current;
 349         dr_mode = "otg";
 350         status = "okay";
 351 };
 352
 353 &usdhc2 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_usdhc2>;
 356         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 357         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 358         vmmc-supply = <&reg_3v3>;
 359         no-1-8-v;
 360         keep-power-in-suspend;
 361         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 362         status = "okay";
 363 };
 364
 365 &iomuxc {
 366         pinctrl_audmux: audmuxgrp {
 367                 fsl,pins = <
 368                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 369                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 370                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 371                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 372                 >;
 373         };
 374
 375         pinctrl_ecspi1: ecspi1grp {
 376                 fsl,pins = <
 377                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 378                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 379                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 380                         MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0         0x100b1
 381                 >;
 382         };
 383
 384         pinctrl_enet: enetgrp {
 385                 fsl,pins = <
 386                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
 387                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 388                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 389                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 390                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 391                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 392                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 393                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 394                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 395                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 396                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 397                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
 398                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 399                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 400                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 401                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 402                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0 /* ENET_INT */
 403                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x1b0b0 /* ETHR_nRST */
 404                 >;
 405         };
 406
 407         pinctrl_i2c1: i2c1grp {
 408                 fsl,pins = <
 409                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
 410                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
 411                 >;
 412         };
 413
 414         pinctrl_led0: led0grp {
 415             fsl,pins = <
 416                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 417             >;
 418         };
 419
 420         pinctrl_ov5640: ov5640grp {
 421                 fsl,pins = <
 422                         MX6QDL_PAD_EIM_D26__GPIO3_IO26  0x1b0b1
 423                         MX6QDL_PAD_EIM_D27__GPIO3_IO27  0x1b0b1
 424                 >;
 425         };
 426
 427         pinctrl_pcf8574: pcf8575grp {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
 430                 >;
 431         };
 432
 433         pinctrl_pcie: pciegrp {
 434                 fsl,pins = <
 435                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
 436                         MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
 437                 >;
 438         };
 439
 440         pinctrl_pwm3: pwm3grp {
 441             fsl,pins = <
 442                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 443             >;
 444         };
 445
 446         pinctrl_reg_1v8: reg1v8grp {
 447             fsl,pins = <
 448                 MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
 449             >;
 450         };
 451
 452         pinctrl_reg_3v3: reg3v3grp {
 453             fsl,pins = <
 454                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b0
 455             >;
 456         };
 457
 458         pinctrl_reg_audio: reg-audiogrp {
 459                 fsl,pins = <
 460                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 461                 >;
 462         };
 463
 464         pinctrl_reg_enet: reg-enetgrp {
 465                 fsl,pins = <
 466                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x1b0b0
 467                 >;
 468         };
 469
 470         pinctrl_reg_hdmi: reg-hdmigrp {
 471                 fsl,pins = <
 472                         MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x1b0b0
 473                 >;
 474         };
 475
 476         pinctrl_reg_mipi: reg-mipigrp {
 477                 fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
 478         };
 479
 480         pinctrl_reg_pcie: reg-pciegrp {
 481                 fsl,pins = <
 482                         MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
 483                         >;
 484         };
 485
 486         pinctrl_reg_uart3: reguart3grp {
 487             fsl,pins = <
 488                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
 489             >;
 490         };
 491
 492         pinctrl_reg_usb_h1_vbus: usbh1grp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 495                 >;
 496         };
 497
 498         pinctrl_reg_usb_otg: reg-usb-otggrp {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 501                 >;
 502         };
 503
 504         pinctrl_uart3: uart3grp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 507                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 508                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 509                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B         0x1b0b1
 510                 >;
 511         };
 512
 513         pinctrl_usbotg: usbotggrp {
 514                 fsl,pins = <
 515                         MX6QDL_PAD_GPIO_1__USB_OTG_ID   0xd17059
 516                 >;
 517         };
 518
 519         pinctrl_usdhc2: usdhc2grp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 522                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17069
 523                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
 524                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17069
 525                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17069
 526                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17069
 527                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17069
 528                 >;
 529         };
 530
 531         pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 534                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
 535                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
 536                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
 537                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
 538                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
 539                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
 540                 >;
 541         };
 542
 543         pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
 544                 fsl,pins = <
 545                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 546                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
 547                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
 548                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
 549                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
 550                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
 551                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
 552                 >;
 553         };
 554
 555 };