arch/arm/boot/dts/imx6qdl-gw552x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 led0 = &led0;
  18                 led1 = &led1;
  19                 led2 = &led2;
  20                 nand = &gpmi;
  21                 usb0 = &usbh1;
  22                 usb1 = &usbotg;
  23         };
  24
  25         chosen {
  26                 bootargs = "console=ttymxc1,115200";
  27         };
  28
  29         leds {
  30                 compatible = "gpio-leds";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_gpio_leds>;
  33
  34                 led0: user1 {
  35                         label = "user1";
  36                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  37                         default-state = "on";
  38                         linux,default-trigger = "heartbeat";
  39                 };
  40
  41                 led1: user2 {
  42                         label = "user2";
  43                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  44                         default-state = "off";
  45                 };
  46
  47                 led2: user3 {
  48                         label = "user3";
  49                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  50                         default-state = "off";
  51                 };
  52         };
  53
  54         memory@10000000 {
  55                 device_type = "memory";
  56                 reg = <0x10000000 0x20000000>;
  57         };
  58
  59         reg_1p0v: regulator-1p0v {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "1P0V";
  62                 regulator-min-microvolt = <1000000>;
  63                 regulator-max-microvolt = <1000000>;
  64                 regulator-always-on;
  65         };
  66
  67         reg_3p3v: regulator-3p3v {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "3P3V";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_5p0v: regulator-5p0v {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "5P0V";
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80                 regulator-always-on;
  81         };
  82 };
  83
  84 &gpmi {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_gpmi_nand>;
  87         status = "okay";
  88 };
  89
  90 &hdmi {
  91         ddc-i2c-bus = <&i2c3>;
  92         status = "okay";
  93 };
  94
  95 &i2c1 {
  96         clock-frequency = <100000>;
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&pinctrl_i2c1>;
  99         status = "okay";
 100
 101         eeprom1: eeprom@50 {
 102                 compatible = "atmel,24c02";
 103                 reg = <0x50>;
 104                 pagesize = <16>;
 105         };
 106
 107         eeprom2: eeprom@51 {
 108                 compatible = "atmel,24c02";
 109                 reg = <0x51>;
 110                 pagesize = <16>;
 111         };
 112
 113         eeprom3: eeprom@52 {
 114                 compatible = "atmel,24c02";
 115                 reg = <0x52>;
 116                 pagesize = <16>;
 117         };
 118
 119         eeprom4: eeprom@53 {
 120                 compatible = "atmel,24c02";
 121                 reg = <0x53>;
 122                 pagesize = <16>;
 123         };
 124
 125         gpio: pca9555@23 {
 126                 compatible = "nxp,pca9555";
 127                 reg = <0x23>;
 128                 gpio-controller;
 129                 #gpio-cells = <2>;
 130         };
 131
 132         rtc: ds1672@68 {
 133                 compatible = "dallas,ds1672";
 134                 reg = <0x68>;
 135         };
 136 };
 137
 138 &i2c2 {
 139         clock-frequency = <100000>;
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_i2c2>;
 142         status = "okay";
 143
 144         ltc3676: pmic@3c {
 145                 compatible = "lltc,ltc3676";
 146                 reg = <0x3c>;
 147                 pinctrl-names = "default";
 148                 pinctrl-0 = <&pinctrl_pmic>;
 149                 interrupt-parent = <&gpio1>;
 150                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 151
 152                 regulators {
 153                         /* VDD_SOC (1+R1/R2 = 1.635) */
 154                         reg_vdd_soc: sw1 {
 155                                 regulator-name = "vddsoc";
 156                                 regulator-min-microvolt = <674400>;
 157                                 regulator-max-microvolt = <1308000>;
 158                                 lltc,fb-voltage-divider = <127000 200000>;
 159                                 regulator-ramp-delay = <7000>;
 160                                 regulator-boot-on;
 161                                 regulator-always-on;
 162                         };
 163
 164                         /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
 165                         reg_1p8v: sw2 {
 166                                 regulator-name = "vdd1p8";
 167                                 regulator-min-microvolt = <1033310>;
 168                                 regulator-max-microvolt = <2004000>;
 169                                 lltc,fb-voltage-divider = <301000 200000>;
 170                                 regulator-ramp-delay = <7000>;
 171                                 regulator-boot-on;
 172                                 regulator-always-on;
 173                         };
 174
 175                         /* VDD_ARM (1+R1/R2 = 1.635) */
 176                         reg_vdd_arm: sw3 {
 177                                 regulator-name = "vddarm";
 178                                 regulator-min-microvolt = <674400>;
 179                                 regulator-max-microvolt = <1308000>;
 180                                 lltc,fb-voltage-divider = <127000 200000>;
 181                                 regulator-ramp-delay = <7000>;
 182                                 regulator-boot-on;
 183                                 regulator-always-on;
 184                         };
 185
 186                         /* VDD_DDR (1+R1/R2 = 2.105) */
 187                         reg_vdd_ddr: sw4 {
 188                                 regulator-name = "vddddr";
 189                                 regulator-min-microvolt = <868310>;
 190                                 regulator-max-microvolt = <1684000>;
 191                                 lltc,fb-voltage-divider = <221000 200000>;
 192                                 regulator-ramp-delay = <7000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 198                         reg_2p5v: ldo2 {
 199                                 regulator-name = "vdd2p5";
 200                                 regulator-min-microvolt = <2490375>;
 201                                 regulator-max-microvolt = <2490375>;
 202                                 lltc,fb-voltage-divider = <487000 200000>;
 203                                 regulator-boot-on;
 204                                 regulator-always-on;
 205                         };
 206
 207                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 208                         reg_3p0v: ldo4 {
 209                                 regulator-name = "vdd3p0";
 210                                 regulator-min-microvolt = <3023250>;
 211                                 regulator-max-microvolt = <3023250>;
 212                                 lltc,fb-voltage-divider = <634000 200000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216                 };
 217         };
 218 };
 219
 220 &i2c3 {
 221         clock-frequency = <100000>;
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_i2c3>;
 224         status = "okay";
 225 };
 226
 227 &pcie {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_pcie>;
 230         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 231         status = "okay";
 232 };
 233
 234 &pwm2 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 237         status = "disabled";
 238 };
 239
 240 &pwm3 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 243         status = "disabled";
 244 };
 245
 246 &uart2 {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_uart2>;
 249         status = "okay";
 250 };
 251
 252 &uart3 {
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_uart3>;
 255         status = "okay";
 256 };
 257
 258 &uart5 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_uart5>;
 261         status = "okay"; };
 262
 263 &usbh1 {
 264         status = "okay";
 265 };
 266
 267 &wdog1 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_wdog>;
 270         fsl,ext-reset-output;
 271 };
 272
 273 &iomuxc {
 274         pinctrl_gpio_leds: gpioledsgrp {
 275                 fsl,pins = <
 276                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 277                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 278                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 279                 >;
 280         };
 281
 282         pinctrl_gpmi_nand: gpminandgrp {
 283                 fsl,pins = <
 284                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 285                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 286                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 287                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 288                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 289                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 290                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 291                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 292                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 293                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 294                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 295                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 296                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 297                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 298                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 299                 >;
 300         };
 301
 302         pinctrl_i2c1: i2c1grp {
 303                 fsl,pins = <
 304                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 305                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 306                 >;
 307         };
 308
 309         pinctrl_i2c2: i2c2grp {
 310                 fsl,pins = <
 311                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 312                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 313                 >;
 314         };
 315
 316         pinctrl_i2c3: i2c3grp {
 317                 fsl,pins = <
 318                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 319                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 320                 >;
 321         };
 322
 323         pinctrl_pcie: pciegrp {
 324                 fsl,pins = <
 325                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
 326                 >;
 327         };
 328
 329         pinctrl_pmic: pmicgrp {
 330                 fsl,pins = <
 331                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 332                 >;
 333         };
 334
 335         pinctrl_pwm2: pwm2grp {
 336                 fsl,pins = <
 337                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 338                 >;
 339         };
 340
 341         pinctrl_pwm3: pwm3grp {
 342                 fsl,pins = <
 343                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 344                 >;
 345         };
 346
 347         pinctrl_uart2: uart2grp {
 348                 fsl,pins = <
 349                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 350                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 351                 >;
 352         };
 353
 354         pinctrl_uart3: uart3grp {
 355                 fsl,pins = <
 356                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 357                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 358                 >;
 359         };
 360
 361         pinctrl_uart5: uart5grp {
 362                 fsl,pins = <
 363                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 364                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 365                 >;
 366         };
 367
 368         pinctrl_wdog: wdoggrp {
 369                 fsl,pins = <
 370                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 371                 >;
 372         };
 373 };