arch/arm/boot/dts/imx6qdl-gw5903.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49
  50 / {
  51         chosen {
  52                 stdout-path = &uart2;
  53         };
  54
  55         backlight {
  56                 compatible = "pwm-backlight";
  57                 pwms = <&pwm1 0 5000000>;
  58                 brightness-levels = <
  59                         0  1  2  3  4  5  6  7  8  9
  60                         10 11 12 13 14 15 16 17 18 19
  61                         20 21 22 23 24 25 26 27 28 29
  62                         30 31 32 33 34 35 36 37 38 39
  63                         40 41 42 43 44 45 46 47 48 49
  64                         50 51 52 53 54 55 56 57 58 59
  65                         60 61 62 63 64 65 66 67 68 69
  66                         70 71 72 73 74 75 76 77 78 79
  67                         80 81 82 83 84 85 86 87 88 89
  68                         90 91 92 93 94 95 96 97 98 99
  69                         100
  70                         >;
  71                 default-brightness-level = <100>;
  72         };
  73
  74         leds {
  75                 compatible = "gpio-leds";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&pinctrl_gpio_leds>;
  78
  79                 led0: user1 {
  80                         label = "user1";
  81                         gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  82                         default-state = "off";
  83                 };
  84         };
  85
  86         memory@10000000 {
  87                 device_type = "memory";
  88                 reg = <0x10000000 0x40000000>;
  89         };
  90
  91         reg_5p0v: regulator-5p0v {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "5P0V";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_3p3v: regulator-3p3v {
 100                 compatible = "regulator-fixed";
 101                 regulator-name = "3P3V";
 102                 regulator-min-microvolt = <3300000>;
 103                 regulator-max-microvolt = <3300000>;
 104                 regulator-always-on;
 105         };
 106
 107         reg_2p5v: regulator-2p5v {
 108                 compatible = "regulator-fixed";
 109                 regulator-name = "2P5V";
 110                 regulator-min-microvolt = <2500000>;
 111                 regulator-max-microvolt = <2500000>;
 112                 regulator-always-on;
 113         };
 114
 115         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 116                 compatible = "regulator-fixed";
 117                 regulator-name = "usb_h1_vbus";
 118                 regulator-min-microvolt = <5000000>;
 119                 regulator-max-microvolt = <5000000>;
 120                 gpio = <&gpio3 30 0>;
 121                 enable-active-high;
 122         };
 123
 124         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 125                 compatible = "regulator-fixed";
 126                 regulator-name = "usb_otg_vbus";
 127                 regulator-min-microvolt = <5000000>;
 128                 regulator-max-microvolt = <5000000>;
 129                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
 130                 enable-active-high;
 131         };
 132
 133         reg_12p0: regulator-12p0v {
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "12P0V";
 136                 regulator-min-microvolt = <12000000>;
 137                 regulator-max-microvolt = <12000000>;
 138                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 139                 enable-active-high;
 140         };
 141
 142         sound {
 143                 compatible = "fsl,imx-audio-tlv320";
 144                 model = "imx-tlv320";
 145                 ssi-controller = <&ssi1>;
 146                 audio-codec = <&tlv320aic3105>;
 147                 /* routing of sink, source */
 148                 audio-routing =
 149                         /* TLV320 LINE1L pin <-> Mic Jack connector */
 150                         "LINE1L", "Mic Jack",
 151                         /* board Headphone Jack <-> HPOUT */
 152                         "Headphone Jack", "HPLOUT",
 153                         "Headphone Jack", "HPROUT",
 154                         "Mic Jack", "Mic Bias";
 155                 mux-int-port = <1>;
 156                 mux-ext-port = <6>;
 157         };
 158 };
 159
 160 &audmux {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_audmux>;
 163         status = "okay";
 164 };
 165
 166 &clks {
 167         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 168                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 169         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 170                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 171 };
 172
 173 &fec {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_enet>;
 176         phy-mode = "rgmii-id";
 177         status = "okay";
 178 };
 179
 180 &i2c1 {
 181         clock-frequency = <100000>;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_i2c1>;
 184         status = "okay";
 185
 186         pca9555: gpio@23 {
 187                 compatible = "nxp,pca9555";
 188                 reg = <0x23>;
 189                 gpio-controller;
 190                 #gpio-cells = <2>;
 191         };
 192
 193         eeprom1: eeprom@50 {
 194                 compatible = "atmel,24c02";
 195                 reg = <0x50>;
 196                 pagesize = <16>;
 197         };
 198
 199         eeprom2: eeprom@51 {
 200                 compatible = "atmel,24c02";
 201                 reg = <0x51>;
 202                 pagesize = <16>;
 203         };
 204
 205         eeprom3: eeprom@52 {
 206                 compatible = "atmel,24c02";
 207                 reg = <0x52>;
 208                 pagesize = <16>;
 209         };
 210
 211         eeprom4: eeprom@53 {
 212                 compatible = "atmel,24c02";
 213                 reg = <0x53>;
 214                 pagesize = <16>;
 215         };
 216
 217         dts1672: rtc@68 {
 218                 compatible = "dallas,ds1672";
 219                 reg = <0x68>;
 220         };
 221 };
 222
 223 &i2c2 {
 224         clock-frequency = <400000>;
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_i2c2>;
 227         status = "okay";
 228
 229         ltc3676: pmic@3c {
 230                 compatible = "lltc,ltc3676";
 231                 reg = <0x3c>;
 232                 interrupt-parent = <&gpio1>;
 233                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 234
 235                 regulators {
 236                         /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
 237                         reg_1p8v: sw1 {
 238                                 regulator-name = "vdd1p8";
 239                                 regulator-min-microvolt = <1033310>;
 240                                 regulator-max-microvolt = <2004000>;
 241                                 lltc,fb-voltage-divider = <301000 200000>;
 242                                 regulator-ramp-delay = <7000>;
 243                                 regulator-boot-on;
 244                                 regulator-always-on;
 245                         };
 246
 247                         /* VDD_DDR (1+R1/R2 = 2.105) */
 248                         reg_vdd_ddr: sw2 {
 249                                 regulator-name = "vddddr";
 250                                 regulator-min-microvolt = <868310>;
 251                                 regulator-max-microvolt = <1684000>;
 252                                 lltc,fb-voltage-divider = <221000 200000>;
 253                                 regulator-ramp-delay = <7000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         /* VDD_ARM (1+R1/R2 = 1.635) */
 259                         reg_vdd_arm: sw3 {
 260                                 regulator-name = "vddarm";
 261                                 regulator-min-microvolt = <674400>;
 262                                 regulator-max-microvolt = <1308000>;
 263                                 lltc,fb-voltage-divider = <127000 200000>;
 264                                 regulator-ramp-delay = <7000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                                 linux,phandle = <&reg_vdd_arm>;
 268                         };
 269
 270                         /* VDD_SOC (1+R1/R2 = 1.635) */
 271                         reg_vdd_soc: sw4 {
 272                                 regulator-name = "vddsoc";
 273                                 regulator-min-microvolt = <674400>;
 274                                 regulator-max-microvolt = <1308000>;
 275                                 lltc,fb-voltage-divider = <127000 200000>;
 276                                 regulator-ramp-delay = <7000>;
 277                                 regulator-boot-on;
 278                                 regulator-always-on;
 279                                 linux,phandle = <&reg_vdd_soc>;
 280                         };
 281
 282                         /* VDD_1P0 (1+R1/R2 = 1.38): */
 283                         reg_1p0v: ldo2 {
 284                                 regulator-name = "vdd1p0";
 285                                 regulator-min-microvolt = <1002777>;
 286                                 regulator-max-microvolt = <1002777>;
 287                                 lltc,fb-voltage-divider = <100000 261000>;
 288                                 regulator-boot-on;
 289                                 regulator-always-on;
 290                         };
 291
 292                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 293                         reg_3p0v: ldo4 {
 294                                 regulator-name = "vdd3p0";
 295                                 regulator-min-microvolt = <3023250>;
 296                                 regulator-max-microvolt = <3023250>;
 297                                 lltc,fb-voltage-divider = <634000 200000>;
 298                                 regulator-boot-on;
 299                                 regulator-always-on;
 300                         };
 301                 };
 302         };
 303 };
 304
 305 &i2c3 {
 306         clock-frequency = <400000>;
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&pinctrl_i2c3>;
 309         status = "okay";
 310
 311         tlv320aic3105: codec@18 {
 312                 compatible = "ti,tlv320aic3x";
 313                 reg = <0x18>;
 314                 gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>;
 315                 clocks = <&clks IMX6QDL_CLK_CKO>;
 316                 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
 317                 /* Regulators */
 318                 DRVDD-supply = <&reg_3p3v>;
 319                 AVDD-supply = <&reg_3p3v>;
 320                 IOVDD-supply = <&reg_3p3v>;
 321                 DVDD-supply = <&reg_1p8v>;
 322         };
 323
 324         accelerometer@1d {
 325                 compatible = "fsl,mma8451";
 326                 reg = <0x1d>;
 327                 interrupt-parent = <&gpio7>;
 328                 interrupts = <11 IRQ_TYPE_EDGE_RISING>;
 329                 interrupt-names = "INT2";
 330         };
 331
 332         /* headphone detect */
 333         ts3a227e@3b {
 334                 compatible = "ti,ts3a227e";
 335                 reg = <0x3b>;
 336                 interrupt-parent = <&gpio5>;
 337                 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 338                 ti,micbias = <4>; /* 2.5V micbias */
 339         };
 340 };
 341
 342 &ldb {
 343         status = "okay";
 344
 345         lvds-channel@0 {
 346                 fsl,data-mapping = "spwg";
 347                 fsl,data-width = <18>;
 348                 status = "okay";
 349
 350                 display-timings {
 351                         native-mode = <&timing0>;
 352                         timing0: g101evn010 {
 353                                 clock-frequency = <68930000>;
 354                                 hactive = <1280>;
 355                                 vactive = <800>;
 356                                 hback-porch = <220>;
 357                                 hfront-porch = <40>;
 358                                 vback-porch = <21>;
 359                                 vfront-porch = <7>;
 360                                 hsync-len = <60>;
 361                                 vsync-len = <10>;
 362                         };
 363                 };
 364         };
 365 };
 366
 367 &pwm1 {
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&pinctrl_pwm1>;
 370         status = "okay";
 371 };
 372
 373 &ssi1 {
 374         status = "okay";
 375 };
 376
 377 &uart1 {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&pinctrl_uart1>;
 380         status = "okay";
 381 };
 382
 383 &uart2 {
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&pinctrl_uart2>;
 386         status = "okay";
 387 };
 388
 389 &usbotg {
 390         vbus-supply = <&reg_usb_otg_vbus>;
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_usbotg>;
 393         disable-over-current;
 394         status = "okay";
 395 };
 396
 397 &usbh1 {
 398         vbus-supply = <&reg_usb_h1_vbus>;
 399         status = "okay";
 400 };
 401
 402 &usdhc1 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
 405         vmmc-supply = <&reg_3p3v>;
 406         non-removable;
 407         bus-width = <4>;
 408         status = "okay";
 409 };
 410
 411 &usdhc2 {
 412         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 413         pinctrl-0 = <&pinctrl_usdhc2>;
 414         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 415         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 416         cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 417         vmmc-supply = <&reg_3p3v>;
 418         max-frequency = <100000000>;
 419         status = "okay";
 420 };
 421
 422 &usdhc3 {
 423         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 424         pinctrl-0 = <&pinctrl_usdhc3>;
 425         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 426         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 427         non-removable;
 428         vmmc-supply = <&reg_3p3v>;
 429         keep-power-in-suspend;
 430         status = "okay";
 431 };
 432
 433 &wdog1 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_wdog>;
 436         fsl,ext-reset-output;
 437 };
 438
 439 &iomuxc {
 440         pinctrl_audmux: audmuxgrp {
 441                 fsl,pins = <
 442                         MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x130b0
 443                         MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x130b0
 444                         MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x130b0
 445                         MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x130b0
 446                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* MCK */
 447                 >;
 448         };
 449
 450         pinctrl_enet: enetgrp {
 451                 fsl,pins = <
 452                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 453                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 454                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 455                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 456                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 457                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 458                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 459                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 460                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 461                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 462                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 463                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 464                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 465                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 466                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 467                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 468                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x4001b0b0 /* PHY_EN */
 469                 >;
 470         };
 471
 472         pinctrl_gpio_leds: gpioledsgrp {
 473                 fsl,pins = <
 474                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 475                 >;
 476         };
 477
 478         pinctrl_i2c1: i2c1grp {
 479                 fsl,pins = <
 480                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 481                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 482                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 483                 >;
 484         };
 485
 486         pinctrl_i2c2: i2c2grp {
 487                 fsl,pins = <
 488                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 489                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 490                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 491                 >;
 492         };
 493
 494         pinctrl_i2c3: i2c3grp {
 495                 fsl,pins = <
 496                         /* I2C3 */
 497                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 498                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 499
 500                         /* Headphone Detect */
 501                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x0001b0b0 /* HPDET_IRQ# */
 502                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x0001b0b0 /* HPDET_MIC# */
 503
 504                         /* Codec */
 505                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x0001b0b0 /* CODEC_RST# */
 506
 507                         /* Touch Controller */
 508                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x0001b0b0 /* TOUCH_IRQ# */
 509                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x0001b0b0 /* TOUCH_RST */
 510
 511                         /* Stow Sensor */
 512                         MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x0001b0b0 /* ACCEL_IRQ2 */
 513                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x0001b0b0 /* ACCEL_IRQ1 */
 514                 >;
 515         };
 516
 517         pinctrl_pwm1: pwm1grp {
 518                 fsl,pins = <
 519                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 520                 >;
 521         };
 522
 523         pinctrl_uart1: uart1grp {
 524                 fsl,pins = <
 525                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 526                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 527                         MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30       0x1b0b1 /* TXEN */
 528                 >;
 529         };
 530
 531         pinctrl_uart2: uart2grp {
 532                 fsl,pins = <
 533                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 534                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 535                 >;
 536         };
 537
 538         pinctrl_usbotg: usbotggrp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 541                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x4001b0b0 /* PWR_EN */
 542                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 543                 >;
 544         };
 545
 546         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 547                 fsl,pins = <
 548                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x4001b0b0 /* EMMY_EN */
 549                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x4001b0b0 /* EMMY_CFG1# */
 550                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05         0x4001b0b0 /* EMMY_CFG2# */
 551                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06         0x0001b0b0 /* EMMY_BTWAKE# */
 552                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07         0x0001b0b0 /* EMMY_WFWAKE# */
 553
 554                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x100f9
 555                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x100f9
 556                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x170f9
 557                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x170f9
 558                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x170f9
 559                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x170f9
 560                 >;
 561         };
 562
 563         pinctrl_usdhc2: usdhc2grp {
 564                 fsl,pins = <
 565                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 566                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 567                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 568                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 569                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 570                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 571                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x17059 /* CD */
 572                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x17059
 573                 >;
 574         };
 575
 576         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 577                 fsl,pins = <
 578                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
 579                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
 580                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
 581                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
 582                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
 583                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
 584                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170b9 /* CD */
 585                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170b9
 586                 >;
 587         };
 588
 589         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 590                 fsl,pins = <
 591                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
 592                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
 593                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
 594                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
 595                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
 596                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
 597                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170f9 /* CD */
 598                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170f9
 599                 >;
 600         };
 601
 602         pinctrl_usdhc3: usdhc3grp {
 603                 fsl,pins = <
 604                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 605                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 606                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 607                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 608                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 609                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 610                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 611                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 612                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 613                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 614                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 615                 >;
 616         };
 617
 618         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 621                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 622                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 623                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 624                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 625                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 626                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 627                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 628                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 629                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 630                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 631                 >;
 632         };
 633
 634         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 635                 fsl,pins = <
 636                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 637                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 638                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 639                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 640                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 641                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 642                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 643                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 644                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 645                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 646                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 647                 >;
 648         };
 649
 650         pinctrl_wdog: wdoggrp {
 651                 fsl,pins = <
 652                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 653                 >;
 654         };
 655 };