| blob | fe17a3405edc5dd8d095d2b1b67d0f580a847997 |
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 /*
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 */
17 chosen {};
19 aliases {
20 ethernet0 = &fec;
21 can0 = &can1;
22 can1 = &can2;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 ipu0 = &ipu1;
34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 mmc3 = &usdhc4;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &ecspi3;
46 spi3 = &ecspi4;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
51 clocks {
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <32768>;
56 };
58 ckih1 {
59 compatible = "fsl,imx-ckih1", "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
64 osc {
65 compatible = "fsl,imx-osc", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <24000000>;
68 };
69 };
71 tempmon: tempmon {
72 compatible = "fsl,imx6q-tempmon";
73 interrupt-parent = <&gpc>;
74 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
75 fsl,tempmon = <&anatop>;
76 fsl,tempmon-data = <&ocotp>;
77 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
78 #thermal-sensor-cells = <0>;
79 };
81 ldb: ldb {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
85 gpr = <&gpr>;
86 status = "disabled";
88 lvds-channel@0 {
89 #address-cells = <1>;
90 #size-cells = <0>;
91 reg = <0>;
92 status = "disabled";
94 port@0 {
95 reg = <0>;
97 lvds0_mux_0: endpoint {
98 remote-endpoint = <&ipu1_di0_lvds0>;
99 };
100 };
102 port@1 {
103 reg = <1>;
105 lvds0_mux_1: endpoint {
106 remote-endpoint = <&ipu1_di1_lvds0>;
107 };
108 };
109 };
111 lvds-channel@1 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <1>;
115 status = "disabled";
117 port@0 {
118 reg = <0>;
120 lvds1_mux_0: endpoint {
121 remote-endpoint = <&ipu1_di0_lvds1>;
122 };
123 };
125 port@1 {
126 reg = <1>;
128 lvds1_mux_1: endpoint {
129 remote-endpoint = <&ipu1_di1_lvds1>;
130 };
131 };
132 };
133 };
135 pmu: pmu {
136 compatible = "arm,cortex-a9-pmu";
137 interrupt-parent = <&gpc>;
138 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
139 };
141 usbphynop1: usbphynop1 {
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
144 };
146 usbphynop2: usbphynop2 {
147 compatible = "usb-nop-xceiv";
148 #phy-cells = <0>;
149 };
151 soc {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "simple-bus";
155 interrupt-parent = <&gpc>;
156 ranges;
158 dma_apbh: dma-apbh@110000 {
159 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x00110000 0x2000>;
161 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
162 <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>,
164 <0 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
166 #dma-cells = <1>;
167 dma-channels = <4>;
168 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
169 };
171 gpmi: gpmi-nand@112000 {
172 compatible = "fsl,imx6q-gpmi-nand";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
180 <&clks IMX6QDL_CLK_GPMI_APB>,
181 <&clks IMX6QDL_CLK_GPMI_BCH>,
182 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
183 <&clks IMX6QDL_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
187 dma-names = "rx-tx";
188 status = "disabled";
189 };
191 hdmi: hdmi@120000 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <0x00120000 0x9000>;
195 interrupts = <0 115 0x04>;
196 gpr = <&gpr>;
197 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
198 <&clks IMX6QDL_CLK_HDMI_ISFR>;
199 clock-names = "iahb", "isfr";
200 status = "disabled";
202 port@0 {
203 reg = <0>;
205 hdmi_mux_0: endpoint {
206 remote-endpoint = <&ipu1_di0_hdmi>;
207 };
208 };
210 port@1 {
211 reg = <1>;
213 hdmi_mux_1: endpoint {
214 remote-endpoint = <&ipu1_di1_hdmi>;
215 };
216 };
217 };
219 gpu_3d: gpu@130000 {
220 compatible = "vivante,gc";
221 reg = <0x00130000 0x4000>;
222 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
224 <&clks IMX6QDL_CLK_GPU3D_CORE>,
225 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
226 clock-names = "bus", "core", "shader";
227 power-domains = <&pd_pu>;
228 #cooling-cells = <2>;
229 };
231 gpu_2d: gpu@134000 {
232 compatible = "vivante,gc";
233 reg = <0x00134000 0x4000>;
234 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
236 <&clks IMX6QDL_CLK_GPU2D_CORE>;
237 clock-names = "bus", "core";
238 power-domains = <&pd_pu>;
239 #cooling-cells = <2>;
240 };
242 timer@a00600 {
243 compatible = "arm,cortex-a9-twd-timer";
244 reg = <0x00a00600 0x20>;
245 interrupts = <1 13 0xf01>;
246 interrupt-parent = <&intc>;
247 clocks = <&clks IMX6QDL_CLK_TWD>;
248 };
250 intc: interrupt-controller@a01000 {
251 compatible = "arm,cortex-a9-gic";
252 #interrupt-cells = <3>;
253 interrupt-controller;
254 reg = <0x00a01000 0x1000>,
255 <0x00a00100 0x100>;
256 interrupt-parent = <&intc>;
257 };
259 L2: l2-cache@a02000 {
260 compatible = "arm,pl310-cache";
261 reg = <0x00a02000 0x1000>;
262 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
263 cache-unified;
264 cache-level = <2>;
265 arm,tag-latency = <4 2 3>;
266 arm,data-latency = <4 2 3>;
267 arm,shared-override;
268 };
270 pcie: pcie@1ffc000 {
271 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
272 reg = <0x01ffc000 0x04000>,
273 <0x01f00000 0x80000>;
274 reg-names = "dbi", "config";
275 #address-cells = <3>;
276 #size-cells = <2>;
277 device_type = "pci";
278 bus-range = <0x00 0xff>;
279 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
280 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
281 num-lanes = <1>;
282 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "msi";
284 #interrupt-cells = <1>;
285 interrupt-map-mask = <0 0 0 0x7>;
286 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
287 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
288 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
289 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
291 <&clks IMX6QDL_CLK_LVDS1_GATE>,
292 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
293 clock-names = "pcie", "pcie_bus", "pcie_phy";
294 status = "disabled";
295 };
297 aips-bus@2000000 { /* AIPS1 */
298 compatible = "fsl,aips-bus", "simple-bus";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 reg = <0x02000000 0x100000>;
302 ranges;
304 spba-bus@2000000 {
305 compatible = "fsl,spba-bus", "simple-bus";
306 #address-cells = <1>;
307 #size-cells = <1>;
308 reg = <0x02000000 0x40000>;
309 ranges;
311 spdif: spdif@2004000 {
312 compatible = "fsl,imx35-spdif";
313 reg = <0x02004000 0x4000>;
314 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
315 dmas = <&sdma 14 18 0>,
316 <&sdma 15 18 0>;
317 dma-names = "rx", "tx";
318 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
319 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
320 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
321 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
322 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
323 clock-names = "core", "rxtx0",
324 "rxtx1", "rxtx2",
325 "rxtx3", "rxtx4",
326 "rxtx5", "rxtx6",
327 "rxtx7", "spba";
328 status = "disabled";
329 };
331 ecspi1: spi@2008000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
335 reg = <0x02008000 0x4000>;
336 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
338 <&clks IMX6QDL_CLK_ECSPI1>;
339 clock-names = "ipg", "per";
340 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
341 dma-names = "rx", "tx";
342 status = "disabled";
343 };
345 ecspi2: spi@200c000 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
349 reg = <0x0200c000 0x4000>;
350 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
352 <&clks IMX6QDL_CLK_ECSPI2>;
353 clock-names = "ipg", "per";
354 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
355 dma-names = "rx", "tx";
356 status = "disabled";
357 };
359 ecspi3: spi@2010000 {
360 #address-cells = <1>;
361 #size-cells = <0>;
362 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
363 reg = <0x02010000 0x4000>;
364 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
366 <&clks IMX6QDL_CLK_ECSPI3>;
367 clock-names = "ipg", "per";
368 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
369 dma-names = "rx", "tx";
370 status = "disabled";
371 };
373 ecspi4: spi@2014000 {
374 #address-cells = <1>;
375 #size-cells = <0>;
376 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
377 reg = <0x02014000 0x4000>;
378 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
380 <&clks IMX6QDL_CLK_ECSPI4>;
381 clock-names = "ipg", "per";
382 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
383 dma-names = "rx", "tx";
384 status = "disabled";
385 };
387 uart1: serial@2020000 {
388 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
389 reg = <0x02020000 0x4000>;
390 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
392 <&clks IMX6QDL_CLK_UART_SERIAL>;
393 clock-names = "ipg", "per";
394 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
395 dma-names = "rx", "tx";
396 status = "disabled";
397 };
399 esai: esai@2024000 {
400 #sound-dai-cells = <0>;
401 compatible = "fsl,imx35-esai";
402 reg = <0x02024000 0x4000>;
403 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
405 <&clks IMX6QDL_CLK_ESAI_MEM>,
406 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
407 <&clks IMX6QDL_CLK_ESAI_IPG>,
408 <&clks IMX6QDL_CLK_SPBA>;
409 clock-names = "core", "mem", "extal", "fsys", "spba";
410 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
411 dma-names = "rx", "tx";
412 status = "disabled";
413 };
415 ssi1: ssi@2028000 {
416 #sound-dai-cells = <0>;
417 compatible = "fsl,imx6q-ssi",
418 "fsl,imx51-ssi";
419 reg = <0x02028000 0x4000>;
420 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
422 <&clks IMX6QDL_CLK_SSI1>;
423 clock-names = "ipg", "baud";
424 dmas = <&sdma 37 1 0>,
425 <&sdma 38 1 0>;
426 dma-names = "rx", "tx";
427 fsl,fifo-depth = <15>;
428 status = "disabled";
429 };
431 ssi2: ssi@202c000 {
432 #sound-dai-cells = <0>;
433 compatible = "fsl,imx6q-ssi",
434 "fsl,imx51-ssi";
435 reg = <0x0202c000 0x4000>;
436 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
438 <&clks IMX6QDL_CLK_SSI2>;
439 clock-names = "ipg", "baud";
440 dmas = <&sdma 41 1 0>,
441 <&sdma 42 1 0>;
442 dma-names = "rx", "tx";
443 fsl,fifo-depth = <15>;
444 status = "disabled";
445 };
447 ssi3: ssi@2030000 {
448 #sound-dai-cells = <0>;
449 compatible = "fsl,imx6q-ssi",
450 "fsl,imx51-ssi";
451 reg = <0x02030000 0x4000>;
452 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
454 <&clks IMX6QDL_CLK_SSI3>;
455 clock-names = "ipg", "baud";
456 dmas = <&sdma 45 1 0>,
457 <&sdma 46 1 0>;
458 dma-names = "rx", "tx";
459 fsl,fifo-depth = <15>;
460 status = "disabled";
461 };
463 asrc: asrc@2034000 {
464 compatible = "fsl,imx53-asrc";
465 reg = <0x02034000 0x4000>;
466 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
468 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
469 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
470 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
471 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
472 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
473 <&clks IMX6QDL_CLK_SPBA>;
474 clock-names = "mem", "ipg", "asrck_0",
475 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
476 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
477 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
478 "asrck_d", "asrck_e", "asrck_f", "spba";
479 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
480 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
481 dma-names = "rxa", "rxb", "rxc",
482 "txa", "txb", "txc";
483 fsl,asrc-rate = <48000>;
484 fsl,asrc-width = <16>;
485 status = "okay";
486 };
488 spba@203c000 {
489 reg = <0x0203c000 0x4000>;
490 };
491 };
493 vpu: vpu@2040000 {
494 compatible = "cnm,coda960";
495 reg = <0x02040000 0x3c000>;
496 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
497 <0 3 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "bit", "jpeg";
499 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
500 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
501 clock-names = "per", "ahb";
502 power-domains = <&pd_pu>;
503 resets = <&src 1>;
504 iram = <&ocram>;
505 };
507 aipstz@207c000 { /* AIPSTZ1 */
508 reg = <0x0207c000 0x4000>;
509 };
511 pwm1: pwm@2080000 {
512 #pwm-cells = <2>;
513 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
514 reg = <0x02080000 0x4000>;
515 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clks IMX6QDL_CLK_IPG>,
517 <&clks IMX6QDL_CLK_PWM1>;
518 clock-names = "ipg", "per";
519 status = "disabled";
520 };
522 pwm2: pwm@2084000 {
523 #pwm-cells = <2>;
524 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
525 reg = <0x02084000 0x4000>;
526 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&clks IMX6QDL_CLK_IPG>,
528 <&clks IMX6QDL_CLK_PWM2>;
529 clock-names = "ipg", "per";
530 status = "disabled";
531 };
533 pwm3: pwm@2088000 {
534 #pwm-cells = <2>;
535 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
536 reg = <0x02088000 0x4000>;
537 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&clks IMX6QDL_CLK_IPG>,
539 <&clks IMX6QDL_CLK_PWM3>;
540 clock-names = "ipg", "per";
541 status = "disabled";
542 };
544 pwm4: pwm@208c000 {
545 #pwm-cells = <2>;
546 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
547 reg = <0x0208c000 0x4000>;
548 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6QDL_CLK_IPG>,
550 <&clks IMX6QDL_CLK_PWM4>;
551 clock-names = "ipg", "per";
552 status = "disabled";
553 };
555 can1: flexcan@2090000 {
556 compatible = "fsl,imx6q-flexcan";
557 reg = <0x02090000 0x4000>;
558 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
560 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
561 clock-names = "ipg", "per";
562 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
563 status = "disabled";
564 };
566 can2: flexcan@2094000 {
567 compatible = "fsl,imx6q-flexcan";
568 reg = <0x02094000 0x4000>;
569 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
571 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
572 clock-names = "ipg", "per";
573 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
574 status = "disabled";
575 };
577 gpt: gpt@2098000 {
578 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
579 reg = <0x02098000 0x4000>;
580 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
582 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
583 <&clks IMX6QDL_CLK_GPT_3M>;
584 clock-names = "ipg", "per", "osc_per";
585 };
587 gpio1: gpio@209c000 {
588 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
589 reg = <0x0209c000 0x4000>;
590 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
591 <0 67 IRQ_TYPE_LEVEL_HIGH>;
592 gpio-controller;
593 #gpio-cells = <2>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
596 };
598 gpio2: gpio@20a0000 {
599 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
600 reg = <0x020a0000 0x4000>;
601 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
602 <0 69 IRQ_TYPE_LEVEL_HIGH>;
603 gpio-controller;
604 #gpio-cells = <2>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 };
609 gpio3: gpio@20a4000 {
610 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
611 reg = <0x020a4000 0x4000>;
612 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
613 <0 71 IRQ_TYPE_LEVEL_HIGH>;
614 gpio-controller;
615 #gpio-cells = <2>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
618 };
620 gpio4: gpio@20a8000 {
621 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
622 reg = <0x020a8000 0x4000>;
623 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
624 <0 73 IRQ_TYPE_LEVEL_HIGH>;
625 gpio-controller;
626 #gpio-cells = <2>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 };
631 gpio5: gpio@20ac000 {
632 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
633 reg = <0x020ac000 0x4000>;
634 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
635 <0 75 IRQ_TYPE_LEVEL_HIGH>;
636 gpio-controller;
637 #gpio-cells = <2>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
640 };
642 gpio6: gpio@20b0000 {
643 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
644 reg = <0x020b0000 0x4000>;
645 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
646 <0 77 IRQ_TYPE_LEVEL_HIGH>;
647 gpio-controller;
648 #gpio-cells = <2>;
649 interrupt-controller;
650 #interrupt-cells = <2>;
651 };
653 gpio7: gpio@20b4000 {
654 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
655 reg = <0x020b4000 0x4000>;
656 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
657 <0 79 IRQ_TYPE_LEVEL_HIGH>;
658 gpio-controller;
659 #gpio-cells = <2>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 };
664 kpp: kpp@20b8000 {
665 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
666 reg = <0x020b8000 0x4000>;
667 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX6QDL_CLK_IPG>;
669 status = "disabled";
670 };
672 wdog1: wdog@20bc000 {
673 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
674 reg = <0x020bc000 0x4000>;
675 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clks IMX6QDL_CLK_DUMMY>;
677 };
679 wdog2: wdog@20c0000 {
680 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
681 reg = <0x020c0000 0x4000>;
682 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clks IMX6QDL_CLK_DUMMY>;
684 status = "disabled";
685 };
687 clks: ccm@20c4000 {
688 compatible = "fsl,imx6q-ccm";
689 reg = <0x020c4000 0x4000>;
690 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
691 <0 88 IRQ_TYPE_LEVEL_HIGH>;
692 #clock-cells = <1>;
693 };
695 anatop: anatop@20c8000 {
696 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
697 reg = <0x020c8000 0x1000>;
698 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
699 <0 54 IRQ_TYPE_LEVEL_HIGH>,
700 <0 127 IRQ_TYPE_LEVEL_HIGH>;
702 regulator-1p1 {
703 compatible = "fsl,anatop-regulator";
704 regulator-name = "vdd1p1";
705 regulator-min-microvolt = <1000000>;
706 regulator-max-microvolt = <1200000>;
707 regulator-always-on;
708 anatop-reg-offset = <0x110>;
709 anatop-vol-bit-shift = <8>;
710 anatop-vol-bit-width = <5>;
711 anatop-min-bit-val = <4>;
712 anatop-min-voltage = <800000>;
713 anatop-max-voltage = <1375000>;
714 anatop-enable-bit = <0>;
715 };
717 regulator-3p0 {
718 compatible = "fsl,anatop-regulator";
719 regulator-name = "vdd3p0";
720 regulator-min-microvolt = <2800000>;
721 regulator-max-microvolt = <3150000>;
722 regulator-always-on;
723 anatop-reg-offset = <0x120>;
724 anatop-vol-bit-shift = <8>;
725 anatop-vol-bit-width = <5>;
726 anatop-min-bit-val = <0>;
727 anatop-min-voltage = <2625000>;
728 anatop-max-voltage = <3400000>;
729 anatop-enable-bit = <0>;
730 };
732 regulator-2p5 {
733 compatible = "fsl,anatop-regulator";
734 regulator-name = "vdd2p5";
735 regulator-min-microvolt = <2250000>;
736 regulator-max-microvolt = <2750000>;
737 regulator-always-on;
738 anatop-reg-offset = <0x130>;
739 anatop-vol-bit-shift = <8>;
740 anatop-vol-bit-width = <5>;
741 anatop-min-bit-val = <0>;
742 anatop-min-voltage = <2100000>;
743 anatop-max-voltage = <2875000>;
744 anatop-enable-bit = <0>;
745 };
747 reg_arm: regulator-vddcore {
748 compatible = "fsl,anatop-regulator";
749 regulator-name = "vddarm";
750 regulator-min-microvolt = <725000>;
751 regulator-max-microvolt = <1450000>;
752 regulator-always-on;
753 anatop-reg-offset = <0x140>;
754 anatop-vol-bit-shift = <0>;
755 anatop-vol-bit-width = <5>;
756 anatop-delay-reg-offset = <0x170>;
757 anatop-delay-bit-shift = <24>;
758 anatop-delay-bit-width = <2>;
759 anatop-min-bit-val = <1>;
760 anatop-min-voltage = <725000>;
761 anatop-max-voltage = <1450000>;
762 };
764 reg_pu: regulator-vddpu {
765 compatible = "fsl,anatop-regulator";
766 regulator-name = "vddpu";
767 regulator-min-microvolt = <725000>;
768 regulator-max-microvolt = <1450000>;
769 regulator-enable-ramp-delay = <150>;
770 anatop-reg-offset = <0x140>;
771 anatop-vol-bit-shift = <9>;
772 anatop-vol-bit-width = <5>;
773 anatop-delay-reg-offset = <0x170>;
774 anatop-delay-bit-shift = <26>;
775 anatop-delay-bit-width = <2>;
776 anatop-min-bit-val = <1>;
777 anatop-min-voltage = <725000>;
778 anatop-max-voltage = <1450000>;
779 };
781 reg_soc: regulator-vddsoc {
782 compatible = "fsl,anatop-regulator";
783 regulator-name = "vddsoc";
784 regulator-min-microvolt = <725000>;
785 regulator-max-microvolt = <1450000>;
786 regulator-always-on;
787 anatop-reg-offset = <0x140>;
788 anatop-vol-bit-shift = <18>;
789 anatop-vol-bit-width = <5>;
790 anatop-delay-reg-offset = <0x170>;
791 anatop-delay-bit-shift = <28>;
792 anatop-delay-bit-width = <2>;
793 anatop-min-bit-val = <1>;
794 anatop-min-voltage = <725000>;
795 anatop-max-voltage = <1450000>;
796 };
797 };
799 usbphy1: usbphy@20c9000 {
800 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
801 reg = <0x020c9000 0x1000>;
802 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
804 fsl,anatop = <&anatop>;
805 };
807 usbphy2: usbphy@20ca000 {
808 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
809 reg = <0x020ca000 0x1000>;
810 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
812 fsl,anatop = <&anatop>;
813 };
815 snvs: snvs@20cc000 {
816 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
817 reg = <0x020cc000 0x4000>;
819 snvs_rtc: snvs-rtc-lp {
820 compatible = "fsl,sec-v4.0-mon-rtc-lp";
821 regmap = <&snvs>;
822 offset = <0x34>;
823 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
824 <0 20 IRQ_TYPE_LEVEL_HIGH>;
825 };
827 snvs_poweroff: snvs-poweroff {
828 compatible = "syscon-poweroff";
829 regmap = <&snvs>;
830 offset = <0x38>;
831 value = <0x60>;
832 mask = <0x60>;
833 status = "disabled";
834 };
836 snvs_lpgpr: snvs-lpgpr {
837 compatible = "fsl,imx6q-snvs-lpgpr";
838 };
839 };
841 epit1: epit@20d0000 { /* EPIT1 */
842 reg = <0x020d0000 0x4000>;
843 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
844 };
846 epit2: epit@20d4000 { /* EPIT2 */
847 reg = <0x020d4000 0x4000>;
848 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
849 };
851 src: src@20d8000 {
852 compatible = "fsl,imx6q-src", "fsl,imx51-src";
853 reg = <0x020d8000 0x4000>;
854 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
855 <0 96 IRQ_TYPE_LEVEL_HIGH>;
856 #reset-cells = <1>;
857 };
859 gpc: gpc@20dc000 {
860 compatible = "fsl,imx6q-gpc";
861 reg = <0x020dc000 0x4000>;
862 interrupt-controller;
863 #interrupt-cells = <3>;
864 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
865 <0 90 IRQ_TYPE_LEVEL_HIGH>;
866 interrupt-parent = <&intc>;
867 clocks = <&clks IMX6QDL_CLK_IPG>;
868 clock-names = "ipg";
870 pgc {
871 #address-cells = <1>;
872 #size-cells = <0>;
874 power-domain@0 {
875 reg = <0>;
876 #power-domain-cells = <0>;
877 };
878 pd_pu: power-domain@1 {
879 reg = <1>;
880 #power-domain-cells = <0>;
881 power-supply = <®_pu>;
882 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
883 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
884 <&clks IMX6QDL_CLK_GPU2D_CORE>,
885 <&clks IMX6QDL_CLK_GPU2D_AXI>,
886 <&clks IMX6QDL_CLK_OPENVG_AXI>,
887 <&clks IMX6QDL_CLK_VPU_AXI>;
888 };
889 };
890 };
892 gpr: iomuxc-gpr@20e0000 {
893 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
894 reg = <0x20e0000 0x38>;
896 mux: mux-controller {
897 compatible = "mmio-mux";
898 #mux-control-cells = <1>;
899 };
900 };
902 iomuxc: iomuxc@20e0000 {
903 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
904 reg = <0x20e0000 0x4000>;
905 };
907 dcic1: dcic@20e4000 {
908 reg = <0x020e4000 0x4000>;
909 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
910 };
912 dcic2: dcic@20e8000 {
913 reg = <0x020e8000 0x4000>;
914 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
915 };
917 sdma: sdma@20ec000 {
918 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
919 reg = <0x020ec000 0x4000>;
920 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6QDL_CLK_SDMA>,
922 <&clks IMX6QDL_CLK_SDMA>;
923 clock-names = "ipg", "ahb";
924 #dma-cells = <3>;
925 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
926 };
927 };
929 aips-bus@2100000 { /* AIPS2 */
930 compatible = "fsl,aips-bus", "simple-bus";
931 #address-cells = <1>;
932 #size-cells = <1>;
933 reg = <0x02100000 0x100000>;
934 ranges;
936 crypto: caam@2100000 {
937 compatible = "fsl,sec-v4.0";
938 #address-cells = <1>;
939 #size-cells = <1>;
940 reg = <0x2100000 0x10000>;
941 ranges = <0 0x2100000 0x10000>;
942 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
943 <&clks IMX6QDL_CLK_CAAM_ACLK>,
944 <&clks IMX6QDL_CLK_CAAM_IPG>,
945 <&clks IMX6QDL_CLK_EIM_SLOW>;
946 clock-names = "mem", "aclk", "ipg", "emi_slow";
948 sec_jr0: jr0@1000 {
949 compatible = "fsl,sec-v4.0-job-ring";
950 reg = <0x1000 0x1000>;
951 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
952 };
954 sec_jr1: jr1@2000 {
955 compatible = "fsl,sec-v4.0-job-ring";
956 reg = <0x2000 0x1000>;
957 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
958 };
959 };
961 aipstz@217c000 { /* AIPSTZ2 */
962 reg = <0x0217c000 0x4000>;
963 };
965 usbotg: usb@2184000 {
966 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
967 reg = <0x02184000 0x200>;
968 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clks IMX6QDL_CLK_USBOH3>;
970 fsl,usbphy = <&usbphy1>;
971 fsl,usbmisc = <&usbmisc 0>;
972 ahb-burst-config = <0x0>;
973 tx-burst-size-dword = <0x10>;
974 rx-burst-size-dword = <0x10>;
975 status = "disabled";
976 };
978 usbh1: usb@2184200 {
979 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
980 reg = <0x02184200 0x200>;
981 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&clks IMX6QDL_CLK_USBOH3>;
983 fsl,usbphy = <&usbphy2>;
984 fsl,usbmisc = <&usbmisc 1>;
985 dr_mode = "host";
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
989 status = "disabled";
990 };
992 usbh2: usb@2184400 {
993 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
994 reg = <0x02184400 0x200>;
995 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6QDL_CLK_USBOH3>;
997 fsl,usbphy = <&usbphynop1>;
998 phy_type = "hsic";
999 fsl,usbmisc = <&usbmisc 2>;
1000 dr_mode = "host";
1001 ahb-burst-config = <0x0>;
1002 tx-burst-size-dword = <0x10>;
1003 rx-burst-size-dword = <0x10>;
1004 status = "disabled";
1005 };
1007 usbh3: usb@2184600 {
1008 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1009 reg = <0x02184600 0x200>;
1010 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1012 fsl,usbphy = <&usbphynop2>;
1013 phy_type = "hsic";
1014 fsl,usbmisc = <&usbmisc 3>;
1015 dr_mode = "host";
1016 ahb-burst-config = <0x0>;
1017 tx-burst-size-dword = <0x10>;
1018 rx-burst-size-dword = <0x10>;
1019 status = "disabled";
1020 };
1022 usbmisc: usbmisc@2184800 {
1023 #index-cells = <1>;
1024 compatible = "fsl,imx6q-usbmisc";
1025 reg = <0x02184800 0x200>;
1026 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1027 };
1029 fec: ethernet@2188000 {
1030 compatible = "fsl,imx6q-fec";
1031 reg = <0x02188000 0x4000>;
1032 interrupt-names = "int0", "pps";
1033 interrupts-extended =
1034 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1035 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6QDL_CLK_ENET>,
1037 <&clks IMX6QDL_CLK_ENET>,
1038 <&clks IMX6QDL_CLK_ENET_REF>;
1039 clock-names = "ipg", "ahb", "ptp";
1040 status = "disabled";
1041 };
1043 mlb@218c000 {
1044 reg = <0x0218c000 0x4000>;
1045 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1046 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1047 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1048 };
1050 usdhc1: usdhc@2190000 {
1051 compatible = "fsl,imx6q-usdhc";
1052 reg = <0x02190000 0x4000>;
1053 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1055 <&clks IMX6QDL_CLK_USDHC1>,
1056 <&clks IMX6QDL_CLK_USDHC1>;
1057 clock-names = "ipg", "ahb", "per";
1058 bus-width = <4>;
1059 status = "disabled";
1060 };
1062 usdhc2: usdhc@2194000 {
1063 compatible = "fsl,imx6q-usdhc";
1064 reg = <0x02194000 0x4000>;
1065 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1067 <&clks IMX6QDL_CLK_USDHC2>,
1068 <&clks IMX6QDL_CLK_USDHC2>;
1069 clock-names = "ipg", "ahb", "per";
1070 bus-width = <4>;
1071 status = "disabled";
1072 };
1074 usdhc3: usdhc@2198000 {
1075 compatible = "fsl,imx6q-usdhc";
1076 reg = <0x02198000 0x4000>;
1077 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1079 <&clks IMX6QDL_CLK_USDHC3>,
1080 <&clks IMX6QDL_CLK_USDHC3>;
1081 clock-names = "ipg", "ahb", "per";
1082 bus-width = <4>;
1083 status = "disabled";
1084 };
1086 usdhc4: usdhc@219c000 {
1087 compatible = "fsl,imx6q-usdhc";
1088 reg = <0x0219c000 0x4000>;
1089 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1091 <&clks IMX6QDL_CLK_USDHC4>,
1092 <&clks IMX6QDL_CLK_USDHC4>;
1093 clock-names = "ipg", "ahb", "per";
1094 bus-width = <4>;
1095 status = "disabled";
1096 };
1098 i2c1: i2c@21a0000 {
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1102 reg = <0x021a0000 0x4000>;
1103 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&clks IMX6QDL_CLK_I2C1>;
1105 status = "disabled";
1106 };
1108 i2c2: i2c@21a4000 {
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1112 reg = <0x021a4000 0x4000>;
1113 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6QDL_CLK_I2C2>;
1115 status = "disabled";
1116 };
1118 i2c3: i2c@21a8000 {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1122 reg = <0x021a8000 0x4000>;
1123 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&clks IMX6QDL_CLK_I2C3>;
1125 status = "disabled";
1126 };
1128 romcp@21ac000 {
1129 reg = <0x021ac000 0x4000>;
1130 };
1132 mmdc0: mmdc@21b0000 { /* MMDC0 */
1133 compatible = "fsl,imx6q-mmdc";
1134 reg = <0x021b0000 0x4000>;
1135 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1136 };
1138 mmdc1: mmdc@21b4000 { /* MMDC1 */
1139 reg = <0x021b4000 0x4000>;
1140 };
1142 weim: weim@21b8000 {
1143 #address-cells = <2>;
1144 #size-cells = <1>;
1145 compatible = "fsl,imx6q-weim";
1146 reg = <0x021b8000 0x4000>;
1147 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1149 fsl,weim-cs-gpr = <&gpr>;
1150 status = "disabled";
1151 };
1153 ocotp: ocotp@21bc000 {
1154 compatible = "fsl,imx6q-ocotp", "syscon";
1155 reg = <0x021bc000 0x4000>;
1156 clocks = <&clks IMX6QDL_CLK_IIM>;
1157 };
1159 tzasc@21d0000 { /* TZASC1 */
1160 reg = <0x021d0000 0x4000>;
1161 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1162 };
1164 tzasc@21d4000 { /* TZASC2 */
1165 reg = <0x021d4000 0x4000>;
1166 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1167 };
1169 audmux: audmux@21d8000 {
1170 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1171 reg = <0x021d8000 0x4000>;
1172 status = "disabled";
1173 };
1175 mipi_csi: mipi@21dc000 {
1176 compatible = "fsl,imx6-mipi-csi2";
1177 reg = <0x021dc000 0x4000>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 interrupts = <0 100 0x04>, <0 101 0x04>;
1181 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1182 <&clks IMX6QDL_CLK_VIDEO_27M>,
1183 <&clks IMX6QDL_CLK_EIM_PODF>;
1184 clock-names = "dphy", "ref", "pix";
1185 status = "disabled";
1186 };
1188 mipi_dsi: mipi@21e0000 {
1189 reg = <0x021e0000 0x4000>;
1190 status = "disabled";
1192 ports {
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1196 port@0 {
1197 reg = <0>;
1199 mipi_mux_0: endpoint {
1200 remote-endpoint = <&ipu1_di0_mipi>;
1201 };
1202 };
1204 port@1 {
1205 reg = <1>;
1207 mipi_mux_1: endpoint {
1208 remote-endpoint = <&ipu1_di1_mipi>;
1209 };
1210 };
1211 };
1212 };
1214 vdoa@21e4000 {
1215 compatible = "fsl,imx6q-vdoa";
1216 reg = <0x021e4000 0x4000>;
1217 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&clks IMX6QDL_CLK_VDOA>;
1219 };
1221 uart2: serial@21e8000 {
1222 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1223 reg = <0x021e8000 0x4000>;
1224 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1225 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1226 <&clks IMX6QDL_CLK_UART_SERIAL>;
1227 clock-names = "ipg", "per";
1228 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1229 dma-names = "rx", "tx";
1230 status = "disabled";
1231 };
1233 uart3: serial@21ec000 {
1234 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1235 reg = <0x021ec000 0x4000>;
1236 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1238 <&clks IMX6QDL_CLK_UART_SERIAL>;
1239 clock-names = "ipg", "per";
1240 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1241 dma-names = "rx", "tx";
1242 status = "disabled";
1243 };
1245 uart4: serial@21f0000 {
1246 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1247 reg = <0x021f0000 0x4000>;
1248 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1250 <&clks IMX6QDL_CLK_UART_SERIAL>;
1251 clock-names = "ipg", "per";
1252 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1253 dma-names = "rx", "tx";
1254 status = "disabled";
1255 };
1257 uart5: serial@21f4000 {
1258 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1259 reg = <0x021f4000 0x4000>;
1260 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1262 <&clks IMX6QDL_CLK_UART_SERIAL>;
1263 clock-names = "ipg", "per";
1264 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1265 dma-names = "rx", "tx";
1266 status = "disabled";
1267 };
1268 };
1270 ipu1: ipu@2400000 {
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 compatible = "fsl,imx6q-ipu";
1274 reg = <0x02400000 0x400000>;
1275 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1276 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&clks IMX6QDL_CLK_IPU1>,
1278 <&clks IMX6QDL_CLK_IPU1_DI0>,
1279 <&clks IMX6QDL_CLK_IPU1_DI1>;
1280 clock-names = "bus", "di0", "di1";
1281 resets = <&src 2>;
1283 ipu1_csi0: port@0 {
1284 reg = <0>;
1286 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1287 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1288 };
1289 };
1291 ipu1_csi1: port@1 {
1292 reg = <1>;
1293 };
1295 ipu1_di0: port@2 {
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1298 reg = <2>;
1300 ipu1_di0_disp0: endpoint@0 {
1301 reg = <0>;
1302 };
1304 ipu1_di0_hdmi: endpoint@1 {
1305 reg = <1>;
1306 remote-endpoint = <&hdmi_mux_0>;
1307 };
1309 ipu1_di0_mipi: endpoint@2 {
1310 reg = <2>;
1311 remote-endpoint = <&mipi_mux_0>;
1312 };
1314 ipu1_di0_lvds0: endpoint@3 {
1315 reg = <3>;
1316 remote-endpoint = <&lvds0_mux_0>;
1317 };
1319 ipu1_di0_lvds1: endpoint@4 {
1320 reg = <4>;
1321 remote-endpoint = <&lvds1_mux_0>;
1322 };
1323 };
1325 ipu1_di1: port@3 {
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 reg = <3>;
1330 ipu1_di1_disp1: endpoint@0 {
1331 reg = <0>;
1332 };
1334 ipu1_di1_hdmi: endpoint@1 {
1335 reg = <1>;
1336 remote-endpoint = <&hdmi_mux_1>;
1337 };
1339 ipu1_di1_mipi: endpoint@2 {
1340 reg = <2>;
1341 remote-endpoint = <&mipi_mux_1>;
1342 };
1344 ipu1_di1_lvds0: endpoint@3 {
1345 reg = <3>;
1346 remote-endpoint = <&lvds0_mux_1>;
1347 };
1349 ipu1_di1_lvds1: endpoint@4 {
1350 reg = <4>;
1351 remote-endpoint = <&lvds1_mux_1>;
1352 };
1353 };
1354 };
1355 };
1356 };