arch/arm/boot/dts/imx6sx-softing-vining-2000.dts

   1 /*
   2  * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include "imx6sx.dtsi"
  14
  15 / {
  16         model = "Softing VIN|ING 2000";
  17         compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory@80000000 {
  24                 device_type = "memory";
  25                 reg = <0x80000000 0x40000000>;
  26         };
  27
  28         reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "usb_otg1_vbus";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_usb_otg1>;
  33                 regulator-min-microvolt = <5000000>;
  34                 regulator-max-microvolt = <5000000>;
  35                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  36                 enable-active-high;
  37         };
  38
  39         reg_peri_3v3: regulator-peri_3v3 {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "peri_3v3";
  42                 regulator-min-microvolt = <3300000>;
  43                 regulator-max-microvolt = <3300000>;
  44         };
  45
  46         pwmleds {
  47                 compatible = "pwm-leds";
  48
  49                 red {
  50                         label = "red";
  51                         max-brightness = <255>;
  52                         pwms = <&pwm6 0 50000>;
  53                 };
  54
  55                 green {
  56                         label = "green";
  57                         max-brightness = <255>;
  58                         pwms = <&pwm2 0 50000>;
  59                 };
  60
  61                 blue {
  62                         label = "blue";
  63                         max-brightness = <255>;
  64                         pwms = <&pwm1 0 50000>;
  65                 };
  66         };
  67 };
  68
  69 &adc1 {
  70         vref-supply = <&reg_peri_3v3>;
  71         status = "okay";
  72 };
  73
  74 &cpu0 {
  75         /*
  76          * This board has a shared rail of reg_arm and reg_soc (supplied by
  77          * sw1a_reg) which is modeled below, but still this module behaves
  78          * unstable without higher voltages. Hence, set higher voltages here.
  79          */
  80         operating-points = <
  81                 /* kHz    uV */
  82                 996000  1250000
  83                 792000  1175000
  84                 396000  1175000
  85                 198000  1175000
  86                 >;
  87         fsl,soc-operating-points = <
  88                 /* ARM kHz  SOC uV */
  89                 996000  1250000
  90                 792000  1175000
  91                 396000  1175000
  92                 198000  1175000
  93         >;
  94 };
  95
  96 &ecspi4 {
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&pinctrl_ecspi4>;
  99         cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
 100         status = "okay";
 101 };
 102
 103 &fec1 {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_enet1>;
 106         phy-supply = <&reg_peri_3v3>;
 107         phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 108         phy-reset-duration = <5>;
 109         phy-mode = "rmii";
 110         phy-handle = <&ethphy0>;
 111         status = "okay";
 112
 113         mdio {
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116
 117                 ethphy0: ethernet0-phy@0 {
 118                         reg = <0>;
 119                         max-speed = <100>;
 120                         interrupt-parent = <&gpio2>;
 121                         interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
 122                 };
 123         };
 124 };
 125
 126 &fec2 {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_enet2>;
 129         phy-supply = <&reg_peri_3v3>;
 130         phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
 131         phy-reset-duration = <5>;
 132         phy-mode = "rmii";
 133         phy-handle = <&ethphy1>;
 134         status = "okay";
 135
 136         mdio {
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139
 140                 ethphy1: ethernet1-phy@0 {
 141                         reg = <0>;
 142                         max-speed = <100>;
 143                         interrupt-parent = <&gpio2>;
 144                         interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 145                 };
 146         };
 147 };
 148
 149 &flexcan1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_flexcan1>;
 152         status = "okay";
 153 };
 154
 155 &flexcan2 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_flexcan2>;
 158         status = "okay";
 159 };
 160
 161 &i2c1 {
 162         clock-frequency = <100000>;
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_i2c1>;
 165         status = "okay";
 166
 167         proximity: sx9500@28 {
 168                 compatible = "semtech,sx9500";
 169                 reg = <0x28>;
 170                 pinctrl-names = "default";
 171                 pinctrl-0 = <&pinctrl_sx9500>;
 172                 interrupt-parent = <&gpio2>;
 173                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 174                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 175         };
 176
 177         pmic: pfuze100@8 {
 178                 compatible = "fsl,pfuze200";
 179                 reg = <0x08>;
 180
 181                 regulators {
 182                         sw1a_reg: sw1ab {
 183                                 regulator-min-microvolt = <300000>;
 184                                 regulator-max-microvolt = <1875000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                                 regulator-ramp-delay = <6250>;
 188                         };
 189
 190                         sw2_reg: sw2 {
 191                                 regulator-min-microvolt = <800000>;
 192                                 regulator-max-microvolt = <3300000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         sw3a_reg: sw3a {
 198                                 regulator-min-microvolt = <400000>;
 199                                 regulator-max-microvolt = <1975000>;
 200                                 regulator-boot-on;
 201                                 regulator-always-on;
 202                         };
 203
 204                         sw3b_reg: sw3b {
 205                                 regulator-min-microvolt = <400000>;
 206                                 regulator-max-microvolt = <1975000>;
 207                                 regulator-boot-on;
 208                                 regulator-always-on;
 209                         };
 210
 211                         snvs_reg: vsnvs {
 212                                 regulator-min-microvolt = <1000000>;
 213                                 regulator-max-microvolt = <3000000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vref_reg: vrefddr {
 219                                 regulator-boot-on;
 220                                 regulator-always-on;
 221                         };
 222
 223                         vgen1_reg: vgen1 {
 224                                 regulator-min-microvolt = <800000>;
 225                                 regulator-max-microvolt = <1550000>;
 226                                 regulator-always-on;
 227                         };
 228
 229                         vgen2_reg: vgen2 {
 230                                 regulator-min-microvolt = <800000>;
 231                                 regulator-max-microvolt = <1550000>;
 232                         };
 233
 234                         vgen3_reg: vgen3 {
 235                                 regulator-min-microvolt = <1800000>;
 236                                 regulator-max-microvolt = <3300000>;
 237                                 regulator-always-on;
 238                         };
 239
 240                         vgen4_reg: vgen4 {
 241                                 regulator-min-microvolt = <1800000>;
 242                                 regulator-max-microvolt = <3300000>;
 243                                 regulator-always-on;
 244                         };
 245
 246                         vgen5_reg: vgen5 {
 247                                 regulator-min-microvolt = <1800000>;
 248                                 regulator-max-microvolt = <3300000>;
 249                                 regulator-always-on;
 250                         };
 251
 252                         vgen6_reg: vgen6 {
 253                                 regulator-min-microvolt = <1800000>;
 254                                 regulator-max-microvolt = <3300000>;
 255                                 regulator-always-on;
 256                         };
 257                 };
 258         };
 259 };
 260
 261 &i2c3 {
 262         clock-frequency = <100000>;
 263         pinctrl-names = "default";
 264         pinctrl-0 = <&pinctrl_i2c3>;
 265         status = "okay";
 266 };
 267
 268 &iomuxc {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&pinctrl_gpios>;
 271
 272         pinctrl_ecspi4: ecspi4grp {
 273                 fsl,pins = <
 274                         MX6SX_PAD_SD3_CLK__ECSPI4_SCLK          0x130b1
 275                         MX6SX_PAD_SD3_DATA3__ECSPI4_MISO        0x130b1
 276                         MX6SX_PAD_SD3_CMD__ECSPI4_MOSI          0x130b1
 277                         MX6SX_PAD_SD3_DATA2__GPIO7_IO_4         0x30b0
 278                 >;
 279         };
 280
 281         pinctrl_enet1: enet1grp {
 282                 fsl,pins = <
 283                         MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x30c1
 284                         MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x30c1
 285                         MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0f9
 286                         MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0f9
 287                         MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x30c1
 288                         MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0f9
 289                         MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4000a038
 290                         /* LAN8720 PHY Reset */
 291                         MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9        0x10b0
 292                         /* MDIO */
 293                         MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0f9
 294                         MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0f9
 295                         /* IRQ from PHY */
 296                         MX6SX_PAD_KEY_ROW2__GPIO2_IO_17         0x10b0
 297                 >;
 298         };
 299
 300         pinctrl_enet2: enet2grp {
 301                 fsl,pins = <
 302                         MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0x1b0b0
 303                         MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0x1b0b0
 304                         MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x1b0b0
 305                         MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x1b0b0
 306                         MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x1b0b0
 307                         MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0x1b0b0
 308                         MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4000a038
 309                         /* LAN8720 PHY Reset */
 310                         MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21       0x10b0
 311                         /* MDIO */
 312                         MX6SX_PAD_ENET1_COL__ENET2_MDC          0xa0f9
 313                         MX6SX_PAD_ENET1_CRS__ENET2_MDIO         0xa0f9
 314                         /* IRQ from PHY */
 315                         MX6SX_PAD_KEY_ROW4__GPIO2_IO_19         0x10b0
 316                 >;
 317         };
 318
 319         pinctrl_flexcan1: flexcan1grp {
 320                 fsl,pins = <
 321                         MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b0b0
 322                         MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b0b0
 323                 >;
 324         };
 325
 326         pinctrl_flexcan2: flexcan2grp {
 327                 fsl,pins = <
 328                         MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b0b0
 329                         MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b0b0
 330                 >;
 331         };
 332
 333         pinctrl_gpios: gpiosgrp {
 334                 fsl,pins = <
 335                         /* reset external uC */
 336                         MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19     0x10b0
 337                         /* IRQ from external uC */
 338                         MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x10b0
 339                         /* overcurrent detection */
 340                         MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8        0x10b0
 341                 >;
 342         };
 343
 344         pinctrl_i2c1: i2c1grp {
 345                 fsl,pins = <
 346                         MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 347                         MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 348                 >;
 349         };
 350
 351         pinctrl_i2c3: i2c3grp {
 352                 fsl,pins = <
 353                         MX6SX_PAD_NAND_ALE__I2C3_SDA            0x4001b8b1
 354                         MX6SX_PAD_NAND_CLE__I2C3_SCL            0x4001b8b1
 355                 >;
 356         };
 357
 358         pinctrl_pwm1: pwm1grp-1 {
 359                 fsl,pins = <
 360                         /* blue LED */
 361                         MX6SX_PAD_RGMII2_RD3__PWM1_OUT          0x1b0b1
 362                 >;
 363         };
 364
 365         pinctrl_pwm2: pwm2grp-1 {
 366                 fsl,pins = <
 367                         /* green LED */
 368                         MX6SX_PAD_RGMII2_RD2__PWM2_OUT          0x1b0b1
 369                 >;
 370         };
 371
 372         pinctrl_pwm6: pwm6grp-1 {
 373                 fsl,pins = <
 374                         /* red LED */
 375                         MX6SX_PAD_RGMII2_TD2__PWM6_OUT          0x1b0b1
 376                 >;
 377         };
 378
 379         pinctrl_sx9500: sx9500grp {
 380                 fsl,pins = <
 381                         /* Reset */
 382                         MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x838
 383                         /* IRQ */
 384                         MX6SX_PAD_KEY_ROW1__GPIO2_IO_16         0x70e0
 385                 >;
 386         };
 387
 388         pinctrl_uart1: uart1grp {
 389                 fsl,pins = <
 390                         MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 391                         MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 392                 >;
 393         };
 394
 395         pinctrl_uart2: uart2grp {
 396                 fsl,pins = <
 397                         MX6SX_PAD_GPIO1_IO06__UART2_TX          0x1b0b1
 398                         MX6SX_PAD_GPIO1_IO07__UART2_RX          0x1b0b1
 399                 >;
 400         };
 401
 402         pinctrl_usb_otg1: usbotg1grp {
 403                 fsl,pins = <
 404                         MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 405                 >;
 406         };
 407
 408         pinctrl_usb_otg1_id: usbotg1idgrp {
 409                 fsl,pins = <
 410                         MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 411                 >;
 412         };
 413
 414         pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
 415                 fsl,pins = <
 416                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 417                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 418                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 419                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 420                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 421                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 422                         MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28       0x1b000
 423                         MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26       0x10b0
 424                 >;
 425         };
 426
 427         pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
 428                 fsl,pins = <
 429                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x100b9
 430                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x170b9
 431                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x170b9
 432                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x170b9
 433                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x170b9
 434                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x170b9
 435                 >;
 436         };
 437
 438         pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
 439                 fsl,pins = <
 440                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x100f9
 441                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x170f9
 442                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x170f9
 443                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x170f9
 444                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x170f9
 445                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x170f9
 446                 >;
 447         };
 448
 449         pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
 450                 fsl,pins = <
 451                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 452                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 453                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 454                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 455                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 456                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 457                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17059
 458                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17059
 459                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17059
 460                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17059
 461                         MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B   0x17068
 462                 >;
 463         };
 464
 465         pinctrl_usdhc4_100mhz: usdhc4-100mhz {
 466                 fsl,pins = <
 467                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
 468                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
 469                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
 470                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
 471                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
 472                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
 473                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
 474                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
 475                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
 476                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
 477                 >;
 478         };
 479
 480         pinctrl_usdhc4_200mhz: usdhc4-200mhz {
 481                 fsl,pins = <
 482                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
 483                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
 484                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
 485                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
 486                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
 487                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
 488                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
 489                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
 490                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
 491                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
 492                 >;
 493         };
 494 };
 495
 496 &pwm1 {
 497         pinctrl-names = "default";
 498         pinctrl-0 = <&pinctrl_pwm1>;
 499         status = "okay";
 500 };
 501
 502 &pwm2 {
 503         pinctrl-names = "default";
 504         pinctrl-0 = <&pinctrl_pwm2>;
 505         status = "okay";
 506 };
 507
 508 &pwm6 {
 509         pinctrl-names = "default";
 510         pinctrl-0 = <&pinctrl_pwm6>;
 511         status = "okay";
 512 };
 513
 514 &reg_arm {
 515         vin-supply = <&sw1a_reg>;
 516 };
 517
 518 &reg_soc {
 519         vin-supply = <&sw1a_reg>;
 520 };
 521
 522 &snvs_poweroff {
 523         status = "okay";
 524 };
 525
 526 &uart1 {
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&pinctrl_uart1>;
 529         status = "okay";
 530 };
 531
 532 &uart2 {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pinctrl_uart2>;
 535         status = "okay";
 536 };
 537
 538 &usbotg1 {
 539         vbus-supply = <&reg_usb_otg1_vbus>;
 540         pinctrl-names = "default";
 541         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 542         status = "okay";
 543 };
 544
 545 &usbotg2 {
 546         dr_mode = "host";
 547         status = "okay";
 548 };
 549
 550 &usdhc2 {
 551         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 552         pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
 553         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 554         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 555         cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
 556         keep-power-in-suspend;
 557         status = "okay";
 558 };
 559
 560 &usdhc4 {
 561         /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
 562          * not on necessary 1.8V.
 563          */
 564         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 565         pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
 566         pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
 567         pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
 568         bus-width = <8>;
 569         keep-power-in-suspend;
 570         non-removable;
 571         cap-mmc-hw-reset;
 572         status = "okay";
 573 };