arch/arm/boot/dts/imx7s-warp.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 NXP Semiconductors.
   4  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/input/input.h>
  10 #include "imx7s.dtsi"
  11
  12 / {
  13         model = "Warp i.MX7 Board";
  14         compatible = "warp,imx7s-warp", "fsl,imx7s";
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0x20000000>;
  19         };
  20
  21         gpio-keys {
  22                 compatible = "gpio-keys";
  23                 pinctrl-0 = <&pinctrl_gpio>;
  24                 autorepeat;
  25
  26                 back {
  27                         label = "Back";
  28                         gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  29                         linux,code = <KEY_BACK>;
  30                         wakeup-source;
  31                 };
  32         };
  33
  34         reg_brcm: regulator-brcm {
  35                 compatible = "regulator-fixed";
  36                 enable-active-high;
  37                 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&pinctrl_brcm_reg>;
  40                 regulator-name = "brcm_reg";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 startup-delay-us = <200000>;
  44         };
  45
  46         reg_bt: regulator-bt {
  47                 compatible = "regulator-fixed";
  48                 pinctrl-names = "default";
  49                 pinctrl-0 = <&pinctrl_bt_reg>;
  50                 enable-active-high;
  51                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  52                 regulator-name = "bt_reg";
  53                 regulator-min-microvolt = <3300000>;
  54                 regulator-max-microvolt = <3300000>;
  55                 regulator-always-on;
  56         };
  57
  58         sound {
  59                 compatible = "simple-audio-card";
  60                 simple-audio-card,name = "imx7-sgtl5000";
  61                 simple-audio-card,format = "i2s";
  62                 simple-audio-card,bitclock-master = <&dailink_master>;
  63                 simple-audio-card,frame-master = <&dailink_master>;
  64                 simple-audio-card,cpu {
  65                         sound-dai = <&sai1>;
  66                 };
  67
  68                 dailink_master: simple-audio-card,codec {
  69                         sound-dai = <&codec>;
  70                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  71                 };
  72         };
  73 };
  74
  75 &clks {
  76         assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  77         assigned-clock-rates = <884736000>;
  78 };
  79
  80 &i2c1 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_i2c1>;
  83         status = "okay";
  84
  85         pmic: pfuze3000@8 {
  86                 compatible = "fsl,pfuze3000";
  87                 reg = <0x08>;
  88
  89                 regulators {
  90                         sw1a_reg: sw1a {
  91                                 regulator-min-microvolt = <700000>;
  92                                 regulator-max-microvolt = <1475000>;
  93                                 regulator-boot-on;
  94                                 regulator-always-on;
  95                                 regulator-ramp-delay = <6250>;
  96                         };
  97
  98                         /* use sw1c_reg to align with pfuze100/pfuze200 */
  99                         sw1c_reg: sw1b {
 100                                 regulator-min-microvolt = <700000>;
 101                                 regulator-max-microvolt = <1475000>;
 102                                 regulator-boot-on;
 103                                 regulator-always-on;
 104                                 regulator-ramp-delay = <6250>;
 105                         };
 106
 107                         sw2_reg: sw2 {
 108                                 regulator-min-microvolt = <1500000>;
 109                                 regulator-max-microvolt = <1850000>;
 110                                 regulator-boot-on;
 111                                 regulator-always-on;
 112                         };
 113
 114                         sw3a_reg: sw3 {
 115                                 regulator-min-microvolt = <900000>;
 116                                 regulator-max-microvolt = <1650000>;
 117                                 regulator-boot-on;
 118                                 regulator-always-on;
 119                         };
 120
 121                         swbst_reg: swbst {
 122                                 regulator-min-microvolt = <5000000>;
 123                                 regulator-max-microvolt = <5150000>;
 124                         };
 125
 126                         snvs_reg: vsnvs {
 127                                 regulator-min-microvolt = <1000000>;
 128                                 regulator-max-microvolt = <3000000>;
 129                                 regulator-boot-on;
 130                                 regulator-always-on;
 131                         };
 132
 133                         vref_reg: vrefddr {
 134                                 regulator-boot-on;
 135                                 regulator-always-on;
 136                         };
 137
 138                         vgen1_reg: vldo1 {
 139                                 regulator-min-microvolt = <1800000>;
 140                                 regulator-max-microvolt = <3300000>;
 141                                 regulator-always-on;
 142                         };
 143
 144                         vgen2_reg: vldo2 {
 145                                 regulator-min-microvolt = <800000>;
 146                                 regulator-max-microvolt = <1550000>;
 147                         };
 148
 149                         vgen3_reg: vccsd {
 150                                 regulator-min-microvolt = <2850000>;
 151                                 regulator-max-microvolt = <3300000>;
 152                                 regulator-always-on;
 153                         };
 154
 155                         vgen4_reg: v33 {
 156                                 regulator-min-microvolt = <2850000>;
 157                                 regulator-max-microvolt = <3300000>;
 158                                 regulator-always-on;
 159                         };
 160
 161                         vgen5_reg: vldo3 {
 162                                 regulator-min-microvolt = <1800000>;
 163                                 regulator-max-microvolt = <3300000>;
 164                                 regulator-always-on;
 165                         };
 166
 167                         vgen6_reg: vldo4 {
 168                                 regulator-min-microvolt = <1800000>;
 169                                 regulator-max-microvolt = <3300000>;
 170                                 regulator-always-on;
 171                         };
 172                 };
 173         };
 174 };
 175
 176 &i2c2 {
 177         clock-frequency = <100000>;
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_i2c2>;
 180         status = "okay";
 181 };
 182
 183 &i2c3 {
 184         clock-frequency = <100000>;
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_i2c3>;
 187         status = "okay";
 188 };
 189
 190 &i2c4 {
 191         clock-frequency = <100000>;
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_i2c4>;
 194         status = "okay";
 195
 196         codec: sgtl5000@a {
 197                 #sound-dai-cells = <0>;
 198                 reg = <0x0a>;
 199                 compatible = "fsl,sgtl5000";
 200                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 201                 pinctrl-names = "default";
 202                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 203                 VDDA-supply = <&vgen4_reg>;
 204                 VDDIO-supply = <&vgen4_reg>;
 205                 VDDD-supply = <&vgen2_reg>;
 206         };
 207
 208         mpl3115@60 {
 209                 compatible = "fsl,mpl3115";
 210                 reg = <0x60>;
 211         };
 212 };
 213
 214 &sai1 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_sai1>;
 217         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 218                           <&clks IMX7D_SAI1_ROOT_CLK>;
 219         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 220         assigned-clock-rates = <0>, <36864000>;
 221         status = "okay";
 222 };
 223
 224 &uart1 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_uart1>;
 227         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 228         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 229         status = "okay";
 230 };
 231
 232 &uart3  {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_uart3>;
 235         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 236         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 237         uart-has-rtscts;
 238         status = "okay";
 239 };
 240
 241 &uart6 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_uart6>;
 244         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 245         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 246         fsl,dte-mode;
 247         status = "okay";
 248 };
 249
 250 &usbotg1 {
 251         dr_mode = "peripheral";
 252         status = "okay";
 253 };
 254
 255 &usdhc1 {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&pinctrl_usdhc1>;
 258         bus-width = <4>;
 259         keep-power-in-suspend;
 260         no-1-8-v;
 261         non-removable;
 262         vmmc-supply = <&reg_brcm>;
 263         status = "okay";
 264 };
 265
 266 &usdhc3 {
 267         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 268         pinctrl-0 = <&pinctrl_usdhc3>;
 269         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 270         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 271         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 272         assigned-clock-rates = <400000000>;
 273         bus-width = <8>;
 274         no-1-8-v;
 275         fsl,tuning-step = <2>;
 276         non-removable;
 277         status = "okay";
 278 };
 279
 280 &wdog1 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_wdog>;
 283         fsl,ext-reset-output;
 284         status = "okay";
 285 };
 286
 287 &iomuxc {
 288         pinctrl_brcm_reg: brcmreggrp {
 289                 fsl,pins = <
 290                         MX7D_PAD_SD2_WP__GPIO5_IO10     0x14 /* WL_REG_ON */
 291                 >;
 292         };
 293
 294         pinctrl_bt_reg: btreggrp {
 295                 fsl,pins = <
 296                         MX7D_PAD_SD2_DATA3__GPIO5_IO17  0x14 /* BT_REG_ON */
 297                 >;
 298         };
 299
 300         pinctrl_gpio: gpiogrp {
 301                 fsl,pins = <
 302                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1     0x14
 303                 >;
 304         };
 305
 306         pinctrl_i2c1: i2c1grp {
 307                 fsl,pins = <
 308                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 309                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 310                 >;
 311         };
 312
 313         pinctrl_i2c2: i2c2grp {
 314                 fsl,pins = <
 315                         MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
 316                         MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
 317                 >;
 318         };
 319
 320         pinctrl_i2c3: i2c3grp {
 321                 fsl,pins = <
 322                         MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
 323                         MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
 324                 >;
 325         };
 326
 327         pinctrl_i2c4: i2c4grp {
 328                 fsl,pins = <
 329                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
 330                         MX7D_PAD_I2C4_SDA__I2C4_SDA     0x4000007f
 331                 >;
 332         };
 333
 334         pinctrl_sai1: sai1grp {
 335                 fsl,pins = <
 336                         MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
 337                         MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
 338                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 339                         MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
 340                 >;
 341         };
 342
 343         pinctrl_sai1_mclk: sai1mclkgrp {
 344                 fsl,pins = <
 345                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 346                 >;
 347         };
 348
 349         pinctrl_uart1: uart1grp {
 350                 fsl,pins = <
 351                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 352                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 353                 >;
 354         };
 355
 356         pinctrl_uart3: uart3grp {
 357                 fsl,pins = <
 358                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 359                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 360                         MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
 361                         MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
 362                 >;
 363         };
 364
 365         pinctrl_uart6: uart6grp {
 366                 fsl,pins = <
 367                         MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
 368                         MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
 369                 >;
 370         };
 371
 372         pinctrl_usdhc1: usdhc1grp {
 373                 fsl,pins = <
 374                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 375                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 376                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 377                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 378                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 379                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 380                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
 381                 >;
 382         };
 383
 384         pinctrl_usdhc3: usdhc3grp {
 385                 fsl,pins = <
 386                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 387                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 388                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 389                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 390                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 391                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 392                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 393                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 394                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 395                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 396                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x19
 397                 >;
 398         };
 399
 400         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 401                 fsl,pins = <
 402                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 403                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 404                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 405                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 406                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 407                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 408                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 409                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 410                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 411                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 412                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1a
 413                 >;
 414         };
 415
 416         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 417                 fsl,pins = <
 418                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 419                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 420                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 421                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 422                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 423                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 424                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 425                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 426                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 427                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 428                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1b
 429                 >;
 430         };
 431 };
 432
 433 &iomuxc_lpsr {
 434         pinctrl_wdog: wdoggrp {
 435                 fsl,pins = <
 436                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 437                 >;
 438         };
 439 };