| blob | f02fb97f515c255c01b3daf47c499542958bea96 |
1 /*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
10 #include <dt-bindings/clock/marvell,mmp2.h>
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 i2c0 = &twsi1;
22 i2c1 = &twsi2;
23 };
25 soc {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "simple-bus";
29 interrupt-parent = <&intc>;
30 ranges;
32 L2: l2-cache {
33 compatible = "marvell,tauros2-cache";
34 marvell,tauros2-cache-features = <0x3>;
35 };
37 axi@d4200000 { /* AXI */
38 compatible = "mrvl,axi-bus", "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0xd4200000 0x00200000>;
42 ranges;
44 intc: interrupt-controller@d4282000 {
45 compatible = "mrvl,mmp2-intc";
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 reg = <0xd4282000 0x1000>;
49 mrvl,intc-nr-irqs = <64>;
50 };
52 intcmux4: interrupt-controller@d4282150 {
53 compatible = "mrvl,mmp2-mux-intc";
54 interrupts = <4>;
55 interrupt-controller;
56 #interrupt-cells = <1>;
57 reg = <0x150 0x4>, <0x168 0x4>;
58 reg-names = "mux status", "mux mask";
59 mrvl,intc-nr-irqs = <2>;
60 };
62 intcmux5: interrupt-controller@d4282154 {
63 compatible = "mrvl,mmp2-mux-intc";
64 interrupts = <5>;
65 interrupt-controller;
66 #interrupt-cells = <1>;
67 reg = <0x154 0x4>, <0x16c 0x4>;
68 reg-names = "mux status", "mux mask";
69 mrvl,intc-nr-irqs = <2>;
70 mrvl,clr-mfp-irq = <1>;
71 };
73 intcmux9: interrupt-controller@d4282180 {
74 compatible = "mrvl,mmp2-mux-intc";
75 interrupts = <9>;
76 interrupt-controller;
77 #interrupt-cells = <1>;
78 reg = <0x180 0x4>, <0x17c 0x4>;
79 reg-names = "mux status", "mux mask";
80 mrvl,intc-nr-irqs = <3>;
81 };
83 intcmux17: interrupt-controller@d4282158 {
84 compatible = "mrvl,mmp2-mux-intc";
85 interrupts = <17>;
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 reg = <0x158 0x4>, <0x170 0x4>;
89 reg-names = "mux status", "mux mask";
90 mrvl,intc-nr-irqs = <5>;
91 };
93 intcmux35: interrupt-controller@d428215c {
94 compatible = "mrvl,mmp2-mux-intc";
95 interrupts = <35>;
96 interrupt-controller;
97 #interrupt-cells = <1>;
98 reg = <0x15c 0x4>, <0x174 0x4>;
99 reg-names = "mux status", "mux mask";
100 mrvl,intc-nr-irqs = <15>;
101 };
103 intcmux51: interrupt-controller@d4282160 {
104 compatible = "mrvl,mmp2-mux-intc";
105 interrupts = <51>;
106 interrupt-controller;
107 #interrupt-cells = <1>;
108 reg = <0x160 0x4>, <0x178 0x4>;
109 reg-names = "mux status", "mux mask";
110 mrvl,intc-nr-irqs = <2>;
111 };
113 intcmux55: interrupt-controller@d4282188 {
114 compatible = "mrvl,mmp2-mux-intc";
115 interrupts = <55>;
116 interrupt-controller;
117 #interrupt-cells = <1>;
118 reg = <0x188 0x4>, <0x184 0x4>;
119 reg-names = "mux status", "mux mask";
120 mrvl,intc-nr-irqs = <2>;
121 };
123 usb_otg_phy0: usb-otg-phy@d4207000 {
124 compatible = "marvell,mmp2-usb-phy";
125 reg = <0xd4207000 0x40>;
126 #phy-cells = <0>;
127 status = "disabled";
128 };
130 usb_otg0: usb-otg@d4208000 {
131 compatible = "marvell,pxau2o-ehci";
132 reg = <0xd4208000 0x200>;
133 interrupts = <44>;
134 clocks = <&soc_clocks MMP2_CLK_USB>;
135 clock-names = "USBCLK";
136 phys = <&usb_otg_phy0>;
137 phy-names = "usb";
138 status = "disabled";
139 };
141 mmc1: mmc@d4280000 {
142 compatible = "mrvl,pxav3-mmc";
143 reg = <0xd4280000 0x120>;
144 clocks = <&soc_clocks MMP2_CLK_SDH0>;
145 clock-names = "io";
146 interrupts = <39>;
147 status = "disabled";
148 };
150 mmc2: mmc@d4280800 {
151 compatible = "mrvl,pxav3-mmc";
152 reg = <0xd4280800 0x120>;
153 clocks = <&soc_clocks MMP2_CLK_SDH1>;
154 clock-names = "io";
155 interrupts = <52>;
156 status = "disabled";
157 };
159 mmc3: mmc@d4281000 {
160 compatible = "mrvl,pxav3-mmc";
161 reg = <0xd4281000 0x120>;
162 clocks = <&soc_clocks MMP2_CLK_SDH2>;
163 clock-names = "io";
164 interrupts = <53>;
165 status = "disabled";
166 };
168 mmc4: mmc@d4281800 {
169 compatible = "mrvl,pxav3-mmc";
170 reg = <0xd4281800 0x120>;
171 clocks = <&soc_clocks MMP2_CLK_SDH3>;
172 clock-names = "io";
173 interrupts = <54>;
174 status = "disabled";
175 };
176 };
178 apb@d4000000 { /* APB */
179 compatible = "mrvl,apb-bus", "simple-bus";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 reg = <0xd4000000 0x00200000>;
183 ranges;
185 timer0: timer@d4014000 {
186 compatible = "mrvl,mmp-timer";
187 reg = <0xd4014000 0x100>;
188 interrupts = <13>;
189 clocks = <&soc_clocks MMP2_CLK_TIMER>;
190 };
192 uart1: uart@d4030000 {
193 compatible = "mrvl,mmp-uart";
194 reg = <0xd4030000 0x1000>;
195 interrupts = <27>;
196 clocks = <&soc_clocks MMP2_CLK_UART0>;
197 resets = <&soc_clocks MMP2_CLK_UART0>;
198 status = "disabled";
199 };
201 uart2: uart@d4017000 {
202 compatible = "mrvl,mmp-uart";
203 reg = <0xd4017000 0x1000>;
204 interrupts = <28>;
205 clocks = <&soc_clocks MMP2_CLK_UART1>;
206 resets = <&soc_clocks MMP2_CLK_UART1>;
207 status = "disabled";
208 };
210 uart3: uart@d4018000 {
211 compatible = "mrvl,mmp-uart";
212 reg = <0xd4018000 0x1000>;
213 interrupts = <24>;
214 clocks = <&soc_clocks MMP2_CLK_UART2>;
215 resets = <&soc_clocks MMP2_CLK_UART2>;
216 status = "disabled";
217 };
219 uart4: uart@d4016000 {
220 compatible = "mrvl,mmp-uart";
221 reg = <0xd4016000 0x1000>;
222 interrupts = <46>;
223 clocks = <&soc_clocks MMP2_CLK_UART3>;
224 resets = <&soc_clocks MMP2_CLK_UART3>;
225 status = "disabled";
226 };
228 gpio: gpio@d4019000 {
229 compatible = "marvell,mmp2-gpio";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 reg = <0xd4019000 0x1000>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupts = <49>;
236 interrupt-names = "gpio_mux";
237 clocks = <&soc_clocks MMP2_CLK_GPIO>;
238 resets = <&soc_clocks MMP2_CLK_GPIO>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 ranges;
243 gcb0: gpio@d4019000 {
244 reg = <0xd4019000 0x4>;
245 };
247 gcb1: gpio@d4019004 {
248 reg = <0xd4019004 0x4>;
249 };
251 gcb2: gpio@d4019008 {
252 reg = <0xd4019008 0x4>;
253 };
255 gcb3: gpio@d4019100 {
256 reg = <0xd4019100 0x4>;
257 };
259 gcb4: gpio@d4019104 {
260 reg = <0xd4019104 0x4>;
261 };
263 gcb5: gpio@d4019108 {
264 reg = <0xd4019108 0x4>;
265 };
266 };
268 twsi1: i2c@d4011000 {
269 compatible = "mrvl,mmp-twsi";
270 reg = <0xd4011000 0x1000>;
271 interrupts = <7>;
272 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
273 resets = <&soc_clocks MMP2_CLK_TWSI0>;
274 #address-cells = <1>;
275 #size-cells = <0>;
276 mrvl,i2c-fast-mode;
277 status = "disabled";
278 };
280 twsi2: i2c@d4031000 {
281 compatible = "mrvl,mmp-twsi";
282 reg = <0xd4031000 0x1000>;
283 interrupt-parent = <&intcmux17>;
284 interrupts = <0>;
285 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
286 resets = <&soc_clocks MMP2_CLK_TWSI1>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 status = "disabled";
290 };
292 twsi3: i2c@d4032000 {
293 compatible = "mrvl,mmp-twsi";
294 reg = <0xd4032000 0x1000>;
295 interrupt-parent = <&intcmux17>;
296 interrupts = <1>;
297 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
298 resets = <&soc_clocks MMP2_CLK_TWSI2>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
304 twsi4: i2c@d4033000 {
305 compatible = "mrvl,mmp-twsi";
306 reg = <0xd4033000 0x1000>;
307 interrupt-parent = <&intcmux17>;
308 interrupts = <2>;
309 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
310 resets = <&soc_clocks MMP2_CLK_TWSI3>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 status = "disabled";
314 };
317 twsi5: i2c@d4033800 {
318 compatible = "mrvl,mmp-twsi";
319 reg = <0xd4033800 0x1000>;
320 interrupt-parent = <&intcmux17>;
321 interrupts = <3>;
322 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
323 resets = <&soc_clocks MMP2_CLK_TWSI4>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
329 twsi6: i2c@d4034000 {
330 compatible = "mrvl,mmp-twsi";
331 reg = <0xd4034000 0x1000>;
332 interrupt-parent = <&intcmux17>;
333 interrupts = <4>;
334 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
335 resets = <&soc_clocks MMP2_CLK_TWSI5>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339 };
341 rtc: rtc@d4010000 {
342 compatible = "mrvl,mmp-rtc";
343 reg = <0xd4010000 0x1000>;
344 interrupts = <1 0>;
345 interrupt-names = "rtc 1Hz", "rtc alarm";
346 interrupt-parent = <&intcmux5>;
347 clocks = <&soc_clocks MMP2_CLK_RTC>;
348 resets = <&soc_clocks MMP2_CLK_RTC>;
349 status = "disabled";
350 };
352 ssp1: ssp@d4035000 {
353 compatible = "marvell,mmp2-ssp";
354 reg = <0xd4035000 0x1000>;
355 clocks = <&soc_clocks MMP2_CLK_SSP0>;
356 interrupts = <0>;
357 status = "disabled";
358 };
360 ssp2: ssp@d4036000 {
361 compatible = "marvell,mmp2-ssp";
362 reg = <0xd4036000 0x1000>;
363 clocks = <&soc_clocks MMP2_CLK_SSP1>;
364 interrupts = <1>;
365 status = "disabled";
366 };
368 ssp3: ssp@d4037000 {
369 compatible = "marvell,mmp2-ssp";
370 reg = <0xd4037000 0x1000>;
371 clocks = <&soc_clocks MMP2_CLK_SSP2>;
372 interrupts = <20>;
373 status = "disabled";
374 };
376 ssp4: ssp@d4039000 {
377 compatible = "marvell,mmp2-ssp";
378 reg = <0xd4039000 0x1000>;
379 clocks = <&soc_clocks MMP2_CLK_SSP3>;
380 interrupts = <21>;
381 status = "disabled";
382 };
383 };
385 soc_clocks: clocks{
386 compatible = "marvell,mmp2-clock";
387 reg = <0xd4050000 0x1000>,
388 <0xd4282800 0x400>,
389 <0xd4015000 0x1000>;
390 reg-names = "mpmu", "apmu", "apbc";
391 #clock-cells = <1>;
392 #reset-cells = <1>;
393 };
394 };
395 };