1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Erin Lo <erin.lo@mediatek.com>
12 model = "MediaTek MT2701 evaluation board";
13 compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
16 device_type = "memory";
17 reg = <0 0x80000000 0 0x40000000>;
21 compatible = "mediatek,mt2701-cs42448-machine";
22 mediatek,platform = <&afe>;
23 /* CS42448 Machine name */
25 "Line Out Jack", "AOUT1L",
26 "Line Out Jack", "AOUT1R",
27 "Line Out Jack", "AOUT2L",
28 "Line Out Jack", "AOUT2R",
29 "Line Out Jack", "AOUT3L",
30 "Line Out Jack", "AOUT3R",
31 "Line Out Jack", "AOUT4L",
32 "Line Out Jack", "AOUT4R",
37 "AIN3L", "Satellite Tuner In",
38 "AIN3R", "Satellite Tuner In",
41 mediatek,audio-codec = <&cs42448>;
42 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&aud_pins_default>;
45 i2s1-in-sel-gpio1 = <&pio 53 0>;
46 i2s1-in-sel-gpio2 = <&pio 54 0>;
50 bt_sco_codec:bt_sco_codec {
51 compatible = "linux,bt-sco";
54 backlight_lcd: backlight_lcd {
55 compatible = "pwm-backlight";
56 pwms = <&bls 0 100000>;
58 0 16 32 48 64 80 96 112
59 128 144 160 176 192 208 224 240
62 default-brightness-level = <9>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pwm_bls_gpio>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&i2c0_pins_a>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&i2c1_pins_a>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&i2c2_pins_a>;
93 compatible = "cirrus,cs42448";
95 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
101 i2c0_pins_a: i2c0@0 {
103 pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>,
104 <MT2701_PIN_76_SCL0__FUNC_SCL0>;
109 i2c1_pins_a: i2c1@0 {
111 pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>,
112 <MT2701_PIN_58_SCL1__FUNC_SCL1>;
117 i2c2_pins_a: i2c2@0 {
119 pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>,
120 <MT2701_PIN_78_SCL2__FUNC_SCL2>;
125 pwm_bls_gpio: pwm_bls_gpio {
127 pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
133 pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
134 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
135 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
136 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
141 aud_pins_default: audiodefault {
143 pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>,
144 <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>,
145 <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>,
146 <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>,
147 <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>,
148 <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>,
149 <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>,
150 <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>,
151 <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>,
152 <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>,
153 <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>,
154 <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>,
155 <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>,
156 <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>,
157 <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>,
158 <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>,
159 <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>,
160 <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>;
161 drive-strength = <MTK_DRIVE_12mA>;
168 pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
169 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
170 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
171 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
178 pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
179 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
180 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
181 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&spi_pins_a>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&spi_pins_b>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&spi_pins_c>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&nor_pins_default>;
210 compatible = "jedec,spi-nor";
216 nor_pins_default: nor {
218 pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>,
219 <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>,
220 <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>,
221 <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
222 <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
223 <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
224 drive-strength = <MTK_DRIVE_4mA>;