arch/arm/boot/dts/ox810se.dtsi

   1 /*
   2  * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
   3  *
   4  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 #include <dt-bindings/clock/oxsemi,ox810se.h>
  10 #include <dt-bindings/reset/oxsemi,ox810se.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         compatible = "oxsemi,ox810se";
  16
  17         cpus {
  18                 #address-cells = <0>;
  19                 #size-cells = <0>;
  20
  21                 cpu {
  22                         device_type = "cpu";
  23                         compatible = "arm,arm926ej-s";
  24                         clocks = <&armclk>;
  25                 };
  26         };
  27
  28         memory {
  29                 device_type = "memory";
  30                 /* Max 256MB @ 0x48000000 */
  31                 reg = <0x48000000 0x10000000>;
  32         };
  33
  34         clocks {
  35                 osc: oscillator {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <25000000>;
  39                 };
  40
  41                 gmacclk: gmacclk {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                         clock-frequency = <125000000>;
  45                 };
  46
  47                 rpsclk: rpsclk {
  48                         compatible = "fixed-factor-clock";
  49                         #clock-cells = <0>;
  50                         clock-div = <1>;
  51                         clock-mult = <1>;
  52                         clocks = <&osc>;
  53                 };
  54
  55                 pll400: pll400 {
  56                         compatible = "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <733333333>;
  59                 };
  60
  61                 sysclk: sysclk {
  62                         compatible = "fixed-factor-clock";
  63                         #clock-cells = <0>;
  64                         clock-div = <4>;
  65                         clock-mult = <1>;
  66                         clocks = <&pll400>;
  67                 };
  68
  69                 armclk: armclk {
  70                         compatible = "fixed-factor-clock";
  71                         #clock-cells = <0>;
  72                         clock-div = <2>;
  73                         clock-mult = <1>;
  74                         clocks = <&pll400>;
  75                 };
  76         };
  77
  78         soc {
  79                 #address-cells = <1>;
  80                 #size-cells = <1>;
  81                 compatible = "simple-bus";
  82                 ranges;
  83                 interrupt-parent = <&intc>;
  84
  85                 apb-bridge@44000000 {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         compatible = "simple-bus";
  89                         ranges = <0 0x44000000 0x1000000>;
  90
  91                         pinctrl: pinctrl {
  92                                 compatible = "oxsemi,ox810se-pinctrl";
  93
  94                                 /* Regmap for sys registers */
  95                                 oxsemi,sys-ctrl = <&sys>;
  96
  97                                 pinctrl_uart0: uart0 {
  98                                         uart0a {
  99                                                 pins = "gpio31";
 100                                                 function = "fct3";
 101                                         };
 102                                         uart0b {
 103                                                 pins = "gpio32";
 104                                                 function = "fct3";
 105                                         };
 106                                 };
 107
 108                                 pinctrl_uart0_modem: uart0_modem {
 109                                         uart0c {
 110                                                 pins = "gpio27";
 111                                                 function = "fct3";
 112                                         };
 113                                         uart0d {
 114                                                 pins = "gpio28";
 115                                                 function = "fct3";
 116                                         };
 117                                         uart0e {
 118                                                 pins = "gpio29";
 119                                                 function = "fct3";
 120                                         };
 121                                         uart0f {
 122                                                 pins = "gpio30";
 123                                                 function = "fct3";
 124                                         };
 125                                         uart0g {
 126                                                 pins = "gpio33";
 127                                                 function = "fct3";
 128                                         };
 129                                         uart0h {
 130                                                 pins = "gpio34";
 131                                                 function = "fct3";
 132                                         };
 133                                 };
 134
 135                                 pinctrl_uart1: uart1 {
 136                                         uart1a {
 137                                                 pins = "gpio20";
 138                                                 function = "fct3";
 139                                         };
 140                                         uart1b {
 141                                                 pins = "gpio22";
 142                                                 function = "fct3";
 143                                         };
 144                                 };
 145
 146                                 pinctrl_uart1_modem: uart1_modem {
 147                                         uart1c {
 148                                                 pins = "gpio8";
 149                                                 function = "fct3";
 150                                         };
 151                                         uart1d {
 152                                                 pins = "gpio9";
 153                                                 function = "fct3";
 154                                         };
 155                                         uart1e {
 156                                                 pins = "gpio23";
 157                                                 function = "fct3";
 158                                         };
 159                                         uart1f {
 160                                                 pins = "gpio24";
 161                                                 function = "fct3";
 162                                         };
 163                                         uart1g {
 164                                                 pins = "gpio25";
 165                                                 function = "fct3";
 166                                         };
 167                                         uart1h {
 168                                                 pins = "gpio26";
 169                                                 function = "fct3";
 170                                         };
 171                                 };
 172
 173                                 pinctrl_uart2: uart2 {
 174                                         uart2a {
 175                                                 pins = "gpio6";
 176                                                 function = "fct3";
 177                                         };
 178                                         uart2b {
 179                                                 pins = "gpio7";
 180                                                 function = "fct3";
 181                                         };
 182                                 };
 183
 184                                 pinctrl_uart2_modem: uart2_modem {
 185                                         uart2c {
 186                                                 pins = "gpio0";
 187                                                 function = "fct3";
 188                                         };
 189                                         uart2d {
 190                                                 pins = "gpio1";
 191                                                 function = "fct3";
 192                                         };
 193                                         uart2e {
 194                                                 pins = "gpio2";
 195                                                 function = "fct3";
 196                                         };
 197                                         uart2f {
 198                                                 pins = "gpio3";
 199                                                 function = "fct3";
 200                                         };
 201                                         uart2g {
 202                                                 pins = "gpio4";
 203                                                 function = "fct3";
 204                                         };
 205                                         uart2h {
 206                                                 pins = "gpio5";
 207                                                 function = "fct3";
 208                                         };
 209                                 };
 210                         };
 211
 212                         gpio0: gpio@0 {
 213                                 compatible = "oxsemi,ox810se-gpio";
 214                                 reg = <0x000000 0x100000>;
 215                                 interrupts = <21>;
 216                                 #gpio-cells = <2>;
 217                                 gpio-controller;
 218                                 interrupt-controller;
 219                                 #interrupt-cells = <2>;
 220                                 ngpios = <32>;
 221                                 oxsemi,gpio-bank = <0>;
 222                                 gpio-ranges = <&pinctrl 0 0 32>;
 223                         };
 224
 225                         gpio1: gpio@100000 {
 226                                 compatible = "oxsemi,ox810se-gpio";
 227                                 reg = <0x100000 0x100000>;
 228                                 interrupts = <22>;
 229                                 #gpio-cells = <2>;
 230                                 gpio-controller;
 231                                 interrupt-controller;
 232                                 #interrupt-cells = <2>;
 233                                 ngpios = <3>;
 234                                 oxsemi,gpio-bank = <1>;
 235                                 gpio-ranges = <&pinctrl 0 32 3>;
 236                         };
 237
 238                         uart0: serial@200000 {
 239                                compatible = "ns16550a";
 240                                reg = <0x200000 0x100000>;
 241                                clocks = <&sysclk>;
 242                                interrupts = <23>;
 243                                reg-shift = <0>;
 244                                fifo-size = <16>;
 245                                reg-io-width = <1>;
 246                                current-speed = <115200>;
 247                                no-loopback-test;
 248                                status = "disabled";
 249                                resets = <&reset RESET_UART1>;
 250                         };
 251
 252                         uart1: serial@300000 {
 253                                compatible = "ns16550a";
 254                                reg = <0x300000 0x100000>;
 255                                clocks = <&sysclk>;
 256                                interrupts = <24>;
 257                                reg-shift = <0>;
 258                                fifo-size = <16>;
 259                                reg-io-width = <1>;
 260                                current-speed = <115200>;
 261                                no-loopback-test;
 262                                status = "disabled";
 263                                resets = <&reset RESET_UART2>;
 264                         };
 265
 266                         uart2: serial@900000 {
 267                                compatible = "ns16550a";
 268                                reg = <0x900000 0x100000>;
 269                                clocks = <&sysclk>;
 270                                interrupts = <29>;
 271                                reg-shift = <0>;
 272                                fifo-size = <16>;
 273                                reg-io-width = <1>;
 274                                current-speed = <115200>;
 275                                no-loopback-test;
 276                                status = "disabled";
 277                                resets = <&reset RESET_UART3>;
 278                         };
 279
 280                         uart3: serial@a00000 {
 281                                compatible = "ns16550a";
 282                                reg = <0xa00000 0x100000>;
 283                                clocks = <&sysclk>;
 284                                interrupts = <30>;
 285                                reg-shift = <0>;
 286                                fifo-size = <16>;
 287                                reg-io-width = <1>;
 288                                current-speed = <115200>;
 289                                no-loopback-test;
 290                                status = "disabled";
 291                                resets = <&reset RESET_UART4>;
 292                         };
 293                 };
 294
 295                 apb-bridge@45000000 {
 296                         #address-cells = <1>;
 297                         #size-cells = <1>;
 298                         compatible = "simple-bus";
 299                         ranges = <0 0x45000000 0x1000000>;
 300
 301                         sys: sys-ctrl@0 {
 302                                 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
 303                                 reg = <0x000000 0x100000>;
 304
 305                                 reset: reset-controller {
 306                                         compatible = "oxsemi,ox810se-reset";
 307                                         #reset-cells = <1>;
 308                                 };
 309
 310                                 stdclk: stdclk {
 311                                         compatible = "oxsemi,ox810se-stdclk";
 312                                         #clock-cells = <1>;
 313                                 };
 314                         };
 315
 316                         rps@300000 {
 317                                 #address-cells = <1>;
 318                                 #size-cells = <1>;
 319                                 compatible = "simple-bus";
 320                                 ranges = <0 0x300000 0x100000>;
 321
 322                                 intc: interrupt-controller@0 {
 323                                         compatible = "oxsemi,ox810se-rps-irq";
 324                                         interrupt-controller;
 325                                         reg = <0 0x200>;
 326                                         #interrupt-cells = <1>;
 327                                         valid-mask = <0xFFFFFFFF>;
 328                                         clear-mask = <0>;
 329                                 };
 330
 331                                 timer0: timer@200 {
 332                                         compatible = "oxsemi,ox810se-rps-timer";
 333                                         reg = <0x200 0x40>;
 334                                         clocks = <&rpsclk>;
 335                                         interrupts = <4 5>;
 336                                 };
 337                         };
 338                 };
 339         };
 340 };