| blob | 65a994f0e09babe6edf817941c3adc61b6d846ae |
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
20 cpu@0 {
21 compatible = "qcom,scorpion";
22 enable-method = "qcom,gcc-msm8660";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 };
28 cpu@1 {
29 compatible = "qcom,scorpion";
30 enable-method = "qcom,gcc-msm8660";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 };
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
42 memory {
43 device_type = "memory";
44 reg = <0x0 0x0>;
45 };
47 cpu-pmu {
48 compatible = "qcom,scorpion-mp-pmu";
49 interrupts = <1 9 0x304>;
50 };
52 clocks {
53 cxo_board {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <19200000>;
57 };
59 pxo_board {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 };
65 sleep_clk {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <32768>;
69 };
70 };
72 /*
73 * These channels from the ADC are simply hardware monitors.
74 * That is why the ADC is referred to as "HKADC" - HouseKeeping
75 * ADC.
76 */
77 iio-hwmon {
78 compatible = "iio-hwmon";
79 io-channels = <&xoadc 0x00 0x01>, /* Battery */
80 <&xoadc 0x00 0x02>, /* DC in (charger) */
81 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
82 <&xoadc 0x00 0x0b>, /* Die temperature */
83 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
84 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
85 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
86 };
88 soc: soc {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92 compatible = "simple-bus";
94 intc: interrupt-controller@2080000 {
95 compatible = "qcom,msm-8660-qgic";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = < 0x02080000 0x1000 >,
99 < 0x02081000 0x1000 >;
100 };
102 timer@2000000 {
103 compatible = "qcom,scss-timer", "qcom,msm-timer";
104 interrupts = <1 0 0x301>,
105 <1 1 0x301>,
106 <1 2 0x301>;
107 reg = <0x02000000 0x100>;
108 clock-frequency = <27000000>,
109 <32768>;
110 cpu-offset = <0x40000>;
111 };
113 tlmm: pinctrl@800000 {
114 compatible = "qcom,msm8660-pinctrl";
115 reg = <0x800000 0x4000>;
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupts = <0 16 0x4>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
123 };
125 gcc: clock-controller@900000 {
126 compatible = "qcom,gcc-msm8660";
127 #clock-cells = <1>;
128 #reset-cells = <1>;
129 reg = <0x900000 0x4000>;
130 };
132 gsbi6: gsbi@16500000 {
133 compatible = "qcom,gsbi-v1.0.0";
134 cell-index = <12>;
135 reg = <0x16500000 0x100>;
136 clocks = <&gcc GSBI6_H_CLK>;
137 clock-names = "iface";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges;
141 status = "disabled";
143 syscon-tcsr = <&tcsr>;
145 gsbi6_serial: serial@16540000 {
146 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
147 reg = <0x16540000 0x1000>,
148 <0x16500000 0x1000>;
149 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
151 clock-names = "core", "iface";
152 status = "disabled";
153 };
155 gsbi6_i2c: i2c@16580000 {
156 compatible = "qcom,i2c-qup-v1.1.1";
157 reg = <0x16580000 0x1000>;
158 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
160 clock-names = "core", "iface";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 status = "disabled";
164 };
165 };
167 gsbi7: gsbi@16600000 {
168 compatible = "qcom,gsbi-v1.0.0";
169 cell-index = <12>;
170 reg = <0x16600000 0x100>;
171 clocks = <&gcc GSBI7_H_CLK>;
172 clock-names = "iface";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
176 status = "disabled";
178 syscon-tcsr = <&tcsr>;
180 gsbi7_serial: serial@16640000 {
181 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
182 reg = <0x16640000 0x1000>,
183 <0x16600000 0x1000>;
184 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
186 clock-names = "core", "iface";
187 status = "disabled";
188 };
190 gsbi7_i2c: i2c@16680000 {
191 compatible = "qcom,i2c-qup-v1.1.1";
192 reg = <0x16680000 0x1000>;
193 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
195 clock-names = "core", "iface";
196 #address-cells = <1>;
197 #size-cells = <0>;
198 status = "disabled";
199 };
200 };
202 gsbi8: gsbi@19800000 {
203 compatible = "qcom,gsbi-v1.0.0";
204 cell-index = <12>;
205 reg = <0x19800000 0x100>;
206 clocks = <&gcc GSBI8_H_CLK>;
207 clock-names = "iface";
208 #address-cells = <1>;
209 #size-cells = <1>;
210 ranges;
212 syscon-tcsr = <&tcsr>;
214 gsbi8_i2c: i2c@19880000 {
215 compatible = "qcom,i2c-qup-v1.1.1";
216 reg = <0x19880000 0x1000>;
217 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
219 clock-names = "core", "iface";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 status = "disabled";
223 };
224 };
226 gsbi12: gsbi@19c00000 {
227 compatible = "qcom,gsbi-v1.0.0";
228 cell-index = <12>;
229 reg = <0x19c00000 0x100>;
230 clocks = <&gcc GSBI12_H_CLK>;
231 clock-names = "iface";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
236 syscon-tcsr = <&tcsr>;
238 gsbi12_serial: serial@19c40000 {
239 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
240 reg = <0x19c40000 0x1000>,
241 <0x19c00000 0x1000>;
242 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
244 clock-names = "core", "iface";
245 status = "disabled";
246 };
248 gsbi12_i2c: i2c@19c80000 {
249 compatible = "qcom,i2c-qup-v1.1.1";
250 reg = <0x19c80000 0x1000>;
251 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
253 clock-names = "core", "iface";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 status = "disabled";
257 };
258 };
260 external-bus@1a100000 {
261 compatible = "qcom,msm8660-ebi2";
262 #address-cells = <2>;
263 #size-cells = <1>;
264 ranges = <0 0x0 0x1a800000 0x00800000>,
265 <1 0x0 0x1b000000 0x00800000>,
266 <2 0x0 0x1b800000 0x00800000>,
267 <3 0x0 0x1d000000 0x08000000>,
268 <4 0x0 0x1c800000 0x00800000>,
269 <5 0x0 0x1c000000 0x00800000>;
270 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
271 reg-names = "ebi2", "xmem";
272 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
273 clock-names = "ebi2x", "ebi2";
274 status = "disabled";
275 };
277 qcom,ssbi@500000 {
278 compatible = "qcom,ssbi";
279 reg = <0x500000 0x1000>;
280 qcom,controller-type = "pmic-arbiter";
282 pm8058: pmic@0 {
283 compatible = "qcom,pm8058";
284 interrupt-parent = <&tlmm>;
285 interrupts = <88 8>;
286 #interrupt-cells = <2>;
287 interrupt-controller;
288 #address-cells = <1>;
289 #size-cells = <0>;
291 pm8058_gpio: gpio@150 {
292 compatible = "qcom,pm8058-gpio",
293 "qcom,ssbi-gpio";
294 reg = <0x150>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 gpio-controller;
298 #gpio-cells = <2>;
300 };
302 pm8058_mpps: mpps@50 {
303 compatible = "qcom,pm8058-mpp",
304 "qcom,ssbi-mpp";
305 reg = <0x50>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-parent = <&pm8058>;
309 interrupts =
310 <128 IRQ_TYPE_NONE>,
311 <129 IRQ_TYPE_NONE>,
312 <130 IRQ_TYPE_NONE>,
313 <131 IRQ_TYPE_NONE>,
314 <132 IRQ_TYPE_NONE>,
315 <133 IRQ_TYPE_NONE>,
316 <134 IRQ_TYPE_NONE>,
317 <135 IRQ_TYPE_NONE>,
318 <136 IRQ_TYPE_NONE>,
319 <137 IRQ_TYPE_NONE>,
320 <138 IRQ_TYPE_NONE>,
321 <139 IRQ_TYPE_NONE>;
322 };
324 pwrkey@1c {
325 compatible = "qcom,pm8058-pwrkey";
326 reg = <0x1c>;
327 interrupt-parent = <&pm8058>;
328 interrupts = <50 1>, <51 1>;
329 debounce = <15625>;
330 pull-up;
331 };
333 keypad@148 {
334 compatible = "qcom,pm8058-keypad";
335 reg = <0x148>;
336 interrupt-parent = <&pm8058>;
337 interrupts = <74 1>, <75 1>;
338 debounce = <15>;
339 scan-delay = <32>;
340 row-hold = <91500>;
341 };
343 xoadc: xoadc@197 {
344 compatible = "qcom,pm8058-adc";
345 reg = <0x197>;
346 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
347 #address-cells = <2>;
348 #size-cells = <0>;
349 #io-channel-cells = <2>;
351 vcoin: adc-channel@0 {
352 reg = <0x00 0x00>;
353 };
354 vbat: adc-channel@1 {
355 reg = <0x00 0x01>;
356 };
357 dcin: adc-channel@2 {
358 reg = <0x00 0x02>;
359 };
360 ichg: adc-channel@3 {
361 reg = <0x00 0x03>;
362 };
363 vph_pwr: adc-channel@4 {
364 reg = <0x00 0x04>;
365 };
366 usb_vbus: adc-channel@a {
367 reg = <0x00 0x0a>;
368 };
369 die_temp: adc-channel@b {
370 reg = <0x00 0x0b>;
371 };
372 ref_625mv: adc-channel@c {
373 reg = <0x00 0x0c>;
374 };
375 ref_1250mv: adc-channel@d {
376 reg = <0x00 0x0d>;
377 };
378 ref_325mv: adc-channel@e {
379 reg = <0x00 0x0e>;
380 };
381 ref_muxoff: adc-channel@f {
382 reg = <0x00 0x0f>;
383 };
384 };
386 rtc@1e8 {
387 compatible = "qcom,pm8058-rtc";
388 reg = <0x1e8>;
389 interrupt-parent = <&pm8058>;
390 interrupts = <39 1>;
391 allow-set-time;
392 };
394 vibrator@4a {
395 compatible = "qcom,pm8058-vib";
396 reg = <0x4a>;
397 };
398 };
399 };
401 l2cc: clock-controller@2082000 {
402 compatible = "syscon";
403 reg = <0x02082000 0x1000>;
404 };
406 rpm: rpm@104000 {
407 compatible = "qcom,rpm-msm8660";
408 reg = <0x00104000 0x1000>;
409 qcom,ipc = <&l2cc 0x8 2>;
411 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
412 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
413 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
414 interrupt-names = "ack", "err", "wakeup";
415 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
416 clock-names = "ram";
418 rpmcc: clock-controller {
419 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
420 #clock-cells = <1>;
421 };
423 pm8901-regulators {
424 compatible = "qcom,rpm-pm8901-regulators";
426 pm8901_l0: l0 {};
427 pm8901_l1: l1 {};
428 pm8901_l2: l2 {};
429 pm8901_l3: l3 {};
430 pm8901_l4: l4 {};
431 pm8901_l5: l5 {};
432 pm8901_l6: l6 {};
434 /* S0 and S1 Handled as SAW regulators by SPM */
435 pm8901_s2: s2 {};
436 pm8901_s3: s3 {};
437 pm8901_s4: s4 {};
439 pm8901_lvs0: lvs0 {};
440 pm8901_lvs1: lvs1 {};
441 pm8901_lvs2: lvs2 {};
442 pm8901_lvs3: lvs3 {};
444 pm8901_mvs: mvs {};
445 };
447 pm8058-regulators {
448 compatible = "qcom,rpm-pm8058-regulators";
450 pm8058_l0: l0 {};
451 pm8058_l1: l1 {};
452 pm8058_l2: l2 {};
453 pm8058_l3: l3 {};
454 pm8058_l4: l4 {};
455 pm8058_l5: l5 {};
456 pm8058_l6: l6 {};
457 pm8058_l7: l7 {};
458 pm8058_l8: l8 {};
459 pm8058_l9: l9 {};
460 pm8058_l10: l10 {};
461 pm8058_l11: l11 {};
462 pm8058_l12: l12 {};
463 pm8058_l13: l13 {};
464 pm8058_l14: l14 {};
465 pm8058_l15: l15 {};
466 pm8058_l16: l16 {};
467 pm8058_l17: l17 {};
468 pm8058_l18: l18 {};
469 pm8058_l19: l19 {};
470 pm8058_l20: l20 {};
471 pm8058_l21: l21 {};
472 pm8058_l22: l22 {};
473 pm8058_l23: l23 {};
474 pm8058_l24: l24 {};
475 pm8058_l25: l25 {};
477 pm8058_s0: s0 {};
478 pm8058_s1: s1 {};
479 pm8058_s2: s2 {};
480 pm8058_s3: s3 {};
481 pm8058_s4: s4 {};
483 pm8058_lvs0: lvs0 {};
484 pm8058_lvs1: lvs1 {};
486 pm8058_ncp: ncp {};
487 };
488 };
490 amba {
491 compatible = "simple-bus";
492 #address-cells = <1>;
493 #size-cells = <1>;
494 ranges;
495 sdcc1: sdcc@12400000 {
496 status = "disabled";
497 compatible = "arm,pl18x", "arm,primecell";
498 arm,primecell-periphid = <0x00051180>;
499 reg = <0x12400000 0x8000>;
500 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
501 interrupt-names = "cmd_irq";
502 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
503 clock-names = "mclk", "apb_pclk";
504 bus-width = <8>;
505 max-frequency = <48000000>;
506 non-removable;
507 cap-sd-highspeed;
508 cap-mmc-highspeed;
509 };
511 sdcc2: sdcc@12140000 {
512 status = "disabled";
513 compatible = "arm,pl18x", "arm,primecell";
514 arm,primecell-periphid = <0x00051180>;
515 reg = <0x12140000 0x8000>;
516 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
517 interrupt-names = "cmd_irq";
518 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
519 clock-names = "mclk", "apb_pclk";
520 bus-width = <8>;
521 max-frequency = <48000000>;
522 cap-sd-highspeed;
523 cap-mmc-highspeed;
524 };
526 sdcc3: sdcc@12180000 {
527 compatible = "arm,pl18x", "arm,primecell";
528 arm,primecell-periphid = <0x00051180>;
529 status = "disabled";
530 reg = <0x12180000 0x8000>;
531 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
532 interrupt-names = "cmd_irq";
533 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
534 clock-names = "mclk", "apb_pclk";
535 bus-width = <4>;
536 cap-sd-highspeed;
537 cap-mmc-highspeed;
538 max-frequency = <48000000>;
539 no-1-8-v;
540 };
542 sdcc4: sdcc@121c0000 {
543 compatible = "arm,pl18x", "arm,primecell";
544 arm,primecell-periphid = <0x00051180>;
545 status = "disabled";
546 reg = <0x121c0000 0x8000>;
547 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "cmd_irq";
549 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
550 clock-names = "mclk", "apb_pclk";
551 bus-width = <4>;
552 max-frequency = <48000000>;
553 cap-sd-highspeed;
554 cap-mmc-highspeed;
555 };
557 sdcc5: sdcc@12200000 {
558 compatible = "arm,pl18x", "arm,primecell";
559 arm,primecell-periphid = <0x00051180>;
560 status = "disabled";
561 reg = <0x12200000 0x8000>;
562 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
563 interrupt-names = "cmd_irq";
564 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
565 clock-names = "mclk", "apb_pclk";
566 bus-width = <4>;
567 cap-sd-highspeed;
568 cap-mmc-highspeed;
569 max-frequency = <48000000>;
570 };
571 };
573 tcsr: syscon@1a400000 {
574 compatible = "qcom,tcsr-msm8660", "syscon";
575 reg = <0x1a400000 0x100>;
576 };
577 };
579 };