arch/arm/boot/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         chosen {
  14                 stdout-path = "serial2:115200n8";
  15         };
  16
  17         /*
  18          * The default coreboot on veyron devices ignores memory@0 nodes
  19          * and would instead create another memory node.
  20          */
  21         memory {
  22                 device_type = "memory";
  23                 reg = <0x0 0x0 0x0 0x80000000>;
  24         };
  25
  26         gpio_keys: gpio-keys {
  27                 compatible = "gpio-keys";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pwr_key_l>;
  33                 power {
  34                         label = "Power";
  35                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_POWER>;
  37                         debounce-interval = <100>;
  38                         wakeup-source;
  39                 };
  40         };
  41
  42         gpio-restart {
  43                 compatible = "gpio-restart";
  44                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&ap_warm_reset_h>;
  47                 priority = <200>;
  48         };
  49
  50         emmc_pwrseq: emmc-pwrseq {
  51                 compatible = "mmc-pwrseq-emmc";
  52                 pinctrl-0 = <&emmc_reset>;
  53                 pinctrl-names = "default";
  54                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  55         };
  56
  57         sdio_pwrseq: sdio-pwrseq {
  58                 compatible = "mmc-pwrseq-simple";
  59                 clocks = <&rk808 RK808_CLKOUT1>;
  60                 clock-names = "ext_clock";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  63
  64                 /*
  65                  * On the module itself this is one of these (depending
  66                  * on the actual card populated):
  67                  * - SDIO_RESET_L_WL_REG_ON
  68                  * - PDN (power down when low)
  69                  */
  70                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
  71         };
  72
  73         vcc_5v: vcc-5v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "vcc_5v";
  76                 regulator-always-on;
  77                 regulator-boot-on;
  78                 regulator-min-microvolt = <5000000>;
  79                 regulator-max-microvolt = <5000000>;
  80         };
  81
  82         vcc33_sys: vcc33-sys {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "vcc33_sys";
  85                 regulator-always-on;
  86                 regulator-boot-on;
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89         };
  90
  91         vcc50_hdmi: vcc50-hdmi {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "vcc50_hdmi";
  94                 regulator-always-on;
  95                 regulator-boot-on;
  96                 vin-supply = <&vcc_5v>;
  97         };
  98 };
  99
 100 &cpu0 {
 101         cpu0-supply = <&vdd_cpu>;
 102 };
 103
 104 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
 105 &cpu_opp_table {
 106         /delete-node/ opp-312000000;
 107
 108         opp-1512000000 {
 109                 opp-microvolt = <1250000>;
 110         };
 111         opp-1608000000 {
 112                 opp-microvolt = <1300000>;
 113         };
 114         opp-1704000000 {
 115                 opp-hz = /bits/ 64 <1704000000>;
 116                 opp-microvolt = <1350000>;
 117         };
 118         opp-1800000000 {
 119                 opp-hz = /bits/ 64 <1800000000>;
 120                 opp-microvolt = <1400000>;
 121         };
 122 };
 123
 124 &emmc {
 125         status = "okay";
 126
 127         bus-width = <8>;
 128         cap-mmc-highspeed;
 129         rockchip,default-sample-phase = <158>;
 130         disable-wp;
 131         mmc-hs200-1_8v;
 132         mmc-pwrseq = <&emmc_pwrseq>;
 133         non-removable;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 136 };
 137
 138 &gpu {
 139         mali-supply = <&vdd_gpu>;
 140         status = "okay";
 141 };
 142
 143 &hdmi {
 144         ddc-i2c-bus = <&i2c5>;
 145         status = "okay";
 146 };
 147
 148 &i2c0 {
 149         status = "okay";
 150
 151         clock-frequency = <400000>;
 152         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 153         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 154
 155         rk808: pmic@1b {
 156                 compatible = "rockchip,rk808";
 157                 reg = <0x1b>;
 158                 clock-output-names = "xin32k", "wifibt_32kin";
 159                 interrupt-parent = <&gpio0>;
 160                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 161                 pinctrl-names = "default";
 162                 pinctrl-0 = <&pmic_int_l>;
 163                 rockchip,system-power-controller;
 164                 wakeup-source;
 165                 #clock-cells = <1>;
 166
 167                 vcc1-supply = <&vcc33_sys>;
 168                 vcc2-supply = <&vcc33_sys>;
 169                 vcc3-supply = <&vcc33_sys>;
 170                 vcc4-supply = <&vcc33_sys>;
 171                 vcc6-supply = <&vcc_5v>;
 172                 vcc7-supply = <&vcc33_sys>;
 173                 vcc8-supply = <&vcc33_sys>;
 174                 vcc12-supply = <&vcc_18>;
 175                 vddio-supply = <&vcc33_io>;
 176
 177                 regulators {
 178                         vdd_cpu: DCDC_REG1 {
 179                                 regulator-name = "vdd_arm";
 180                                 regulator-always-on;
 181                                 regulator-boot-on;
 182                                 regulator-min-microvolt = <750000>;
 183                                 regulator-max-microvolt = <1450000>;
 184                                 regulator-ramp-delay = <6001>;
 185                                 regulator-state-mem {
 186                                         regulator-off-in-suspend;
 187                                 };
 188                         };
 189
 190                         vdd_gpu: DCDC_REG2 {
 191                                 regulator-name = "vdd_gpu";
 192                                 regulator-always-on;
 193                                 regulator-boot-on;
 194                                 regulator-min-microvolt = <800000>;
 195                                 regulator-max-microvolt = <1250000>;
 196                                 regulator-ramp-delay = <6001>;
 197                                 regulator-state-mem {
 198                                         regulator-on-in-suspend;
 199                                         regulator-suspend-microvolt = <1000000>;
 200                                 };
 201                         };
 202
 203                         vcc135_ddr: DCDC_REG3 {
 204                                 regulator-name = "vcc135_ddr";
 205                                 regulator-always-on;
 206                                 regulator-boot-on;
 207                                 regulator-state-mem {
 208                                         regulator-on-in-suspend;
 209                                 };
 210                         };
 211
 212                         /*
 213                          * vcc_18 has several aliases.  (vcc18_flashio and
 214                          * vcc18_wl).  We'll add those aliases here just to
 215                          * make it easier to follow the schematic.  The signals
 216                          * are actually hooked together and only separated for
 217                          * power measurement purposes).
 218                          */
 219                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 220                                 regulator-name = "vcc_18";
 221                                 regulator-always-on;
 222                                 regulator-boot-on;
 223                                 regulator-min-microvolt = <1800000>;
 224                                 regulator-max-microvolt = <1800000>;
 225                                 regulator-state-mem {
 226                                         regulator-on-in-suspend;
 227                                         regulator-suspend-microvolt = <1800000>;
 228                                 };
 229                         };
 230
 231                         /*
 232                          * Note that both vcc33_io and vcc33_pmuio are always
 233                          * powered together. To simplify the logic in the dts
 234                          * we just refer to vcc33_io every time something is
 235                          * powered from vcc33_pmuio. In fact, on later boards
 236                          * (such as danger) they're the same net.
 237                          */
 238                         vcc33_io: LDO_REG1 {
 239                                 regulator-name = "vcc33_io";
 240                                 regulator-always-on;
 241                                 regulator-boot-on;
 242                                 regulator-min-microvolt = <3300000>;
 243                                 regulator-max-microvolt = <3300000>;
 244                                 regulator-state-mem {
 245                                         regulator-on-in-suspend;
 246                                         regulator-suspend-microvolt = <3300000>;
 247                                 };
 248                         };
 249
 250                         vdd_10: LDO_REG3 {
 251                                 regulator-name = "vdd_10";
 252                                 regulator-always-on;
 253                                 regulator-boot-on;
 254                                 regulator-min-microvolt = <1000000>;
 255                                 regulator-max-microvolt = <1000000>;
 256                                 regulator-state-mem {
 257                                         regulator-on-in-suspend;
 258                                         regulator-suspend-microvolt = <1000000>;
 259                                 };
 260                         };
 261
 262                         vdd10_lcd_pwren_h: LDO_REG7 {
 263                                 regulator-name = "vdd10_lcd_pwren_h";
 264                                 regulator-always-on;
 265                                 regulator-boot-on;
 266                                 regulator-min-microvolt = <2500000>;
 267                                 regulator-max-microvolt = <2500000>;
 268                                 regulator-state-mem {
 269                                         regulator-off-in-suspend;
 270                                 };
 271                         };
 272
 273                         vcc33_lcd: SWITCH_REG1 {
 274                                 regulator-name = "vcc33_lcd";
 275                                 regulator-always-on;
 276                                 regulator-boot-on;
 277                                 regulator-state-mem {
 278                                         regulator-off-in-suspend;
 279                                 };
 280                         };
 281                 };
 282         };
 283 };
 284
 285 &i2c1 {
 286         status = "okay";
 287
 288         clock-frequency = <400000>;
 289         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 290         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 291
 292         tpm: tpm@20 {
 293                 compatible = "infineon,slb9645tt";
 294                 reg = <0x20>;
 295                 powered-while-suspended;
 296         };
 297 };
 298
 299 &i2c2 {
 300         status = "okay";
 301
 302         /* 100kHz since 4.7k resistors don't rise fast enough */
 303         clock-frequency = <100000>;
 304         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 305         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 306 };
 307
 308 &i2c4 {
 309         status = "okay";
 310
 311         clock-frequency = <400000>;
 312         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 313         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 314 };
 315
 316 &i2c5 {
 317         status = "okay";
 318
 319         clock-frequency = <100000>;
 320         i2c-scl-falling-time-ns = <300>;
 321         i2c-scl-rising-time-ns = <1000>;
 322 };
 323
 324 &io_domains {
 325         status = "okay";
 326
 327         bb-supply = <&vcc33_io>;
 328         dvp-supply = <&vcc_18>;
 329         flash0-supply = <&vcc18_flashio>;
 330         gpio1830-supply = <&vcc33_io>;
 331         gpio30-supply = <&vcc33_io>;
 332         lcdc-supply = <&vcc33_lcd>;
 333         wifi-supply = <&vcc18_wl>;
 334 };
 335
 336 &pwm1 {
 337         status = "okay";
 338 };
 339
 340 &sdio0 {
 341         status = "okay";
 342
 343         bus-width = <4>;
 344         cap-sd-highspeed;
 345         cap-sdio-irq;
 346         keep-power-in-suspend;
 347         mmc-pwrseq = <&sdio_pwrseq>;
 348         non-removable;
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 351         sd-uhs-sdr12;
 352         sd-uhs-sdr25;
 353         sd-uhs-sdr50;
 354         sd-uhs-sdr104;
 355         vmmc-supply = <&vcc33_sys>;
 356         vqmmc-supply = <&vcc18_wl>;
 357 };
 358
 359 &spi2 {
 360         status = "okay";
 361
 362         rx-sample-delay-ns = <12>;
 363
 364         flash@0 {
 365                 compatible = "jedec,spi-nor";
 366                 spi-max-frequency = <50000000>;
 367                 reg = <0>;
 368         };
 369 };
 370
 371 &tsadc {
 372         status = "okay";
 373
 374         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 375         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 376 };
 377
 378 &uart0 {
 379         status = "okay";
 380
 381         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 382         assigned-clocks = <&cru SCLK_UART0>;
 383         assigned-clock-rates = <48000000>;
 384
 385         /* Pins don't include flow control by default; add that in */
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 388 };
 389
 390 &uart1 {
 391         status = "okay";
 392 };
 393
 394 &uart2 {
 395         status = "okay";
 396 };
 397
 398 &usbphy {
 399         status = "okay";
 400 };
 401
 402 &usb_host0_ehci {
 403         status = "okay";
 404
 405         needs-reset-on-resume;
 406 };
 407
 408 &usb_host1 {
 409         status = "okay";
 410 };
 411
 412 &usb_otg {
 413         status = "okay";
 414
 415         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 416         assigned-clock-parents = <&usbphy0>;
 417         dr_mode = "host";
 418 };
 419
 420 &vopb {
 421         status = "okay";
 422 };
 423
 424 &vopb_mmu {
 425         status = "okay";
 426 };
 427
 428 &wdt {
 429         status = "okay";
 430 };
 431
 432 &pinctrl {
 433         pinctrl-names = "default", "sleep";
 434         pinctrl-0 = <
 435                 /* Common for sleep and wake, but no owners */
 436                 &global_pwroff
 437         >;
 438         pinctrl-1 = <
 439                 /* Common for sleep and wake, but no owners */
 440                 &global_pwroff
 441         >;
 442
 443         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 444                 bias-disable;
 445                 drive-strength = <8>;
 446         };
 447
 448         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 449                 bias-pull-up;
 450                 drive-strength = <8>;
 451         };
 452
 453         pcfg_output_high: pcfg-output-high {
 454                 output-high;
 455         };
 456
 457         pcfg_output_low: pcfg-output-low {
 458                 output-low;
 459         };
 460
 461         buttons {
 462                 pwr_key_l: pwr-key-l {
 463                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 464                 };
 465         };
 466
 467         emmc {
 468                 emmc_reset: emmc-reset {
 469                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 470                 };
 471
 472                 /*
 473                  * We run eMMC at max speed; bump up drive strength.
 474                  * We also have external pulls, so disable the internal ones.
 475                  */
 476                 emmc_clk: emmc-clk {
 477                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 478                 };
 479
 480                 emmc_cmd: emmc-cmd {
 481                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 482                 };
 483
 484                 emmc_bus8: emmc-bus8 {
 485                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 486                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 487                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 488                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 489                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 490                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 491                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 492                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 493                 };
 494         };
 495
 496         pmic {
 497                 pmic_int_l: pmic-int-l {
 498                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 499                 };
 500         };
 501
 502         reboot {
 503                 ap_warm_reset_h: ap-warm-reset-h {
 504                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 505                 };
 506         };
 507
 508         recovery-switch {
 509                 rec_mode_l: rec-mode-l {
 510                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 511                 };
 512         };
 513
 514         sdio0 {
 515                 wifi_enable_h: wifienable-h {
 516                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 517                 };
 518
 519                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 520                 bt_enable_l: bt-enable-l {
 521                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 522                 };
 523
 524                 /*
 525                  * We run sdio0 at max speed; bump up drive strength.
 526                  * We also have external pulls, so disable the internal ones.
 527                  */
 528                 sdio0_bus4: sdio0-bus4 {
 529                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 530                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 531                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 532                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 533                 };
 534
 535                 sdio0_cmd: sdio0-cmd {
 536                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 537                 };
 538
 539                 sdio0_clk: sdio0-clk {
 540                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 541                 };
 542         };
 543
 544         tpm {
 545                 tpm_int_h: tpm-int-h {
 546                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 547                 };
 548         };
 549
 550         write-protect {
 551                 fw_wp_ap: fw-wp-ap {
 552                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 553                 };
 554         };
 555 };