| blob | ae24599d58296f4ede568c2ce91b89216c6afa5c |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
9 / {
10 #address-cells = <1>;
11 #size-cells = <1>;
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 };
24 cpu@1 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <1>;
28 next-level-cache = <&L2>;
29 };
30 };
32 intc: intc@ffffd000 {
33 compatible = "arm,cortex-a9-gic";
34 #interrupt-cells = <3>;
35 interrupt-controller;
36 reg = <0xffffd000 0x1000>,
37 <0xffffc100 0x100>;
38 };
40 soc {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "simple-bus";
44 device_type = "soc";
45 interrupt-parent = <&intc>;
46 ranges;
48 amba {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
54 pdma: pdma@ffda1000 {
55 compatible = "arm,pl330", "arm,primecell";
56 reg = <0xffda1000 0x1000>;
57 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
58 <0 84 IRQ_TYPE_LEVEL_HIGH>,
59 <0 85 IRQ_TYPE_LEVEL_HIGH>,
60 <0 86 IRQ_TYPE_LEVEL_HIGH>,
61 <0 87 IRQ_TYPE_LEVEL_HIGH>,
62 <0 88 IRQ_TYPE_LEVEL_HIGH>,
63 <0 89 IRQ_TYPE_LEVEL_HIGH>,
64 <0 90 IRQ_TYPE_LEVEL_HIGH>,
65 <0 91 IRQ_TYPE_LEVEL_HIGH>;
66 #dma-cells = <1>;
67 #dma-channels = <8>;
68 #dma-requests = <32>;
69 clocks = <&l4_main_clk>;
70 clock-names = "apb_pclk";
71 };
72 };
74 base_fpga_region {
75 #address-cells = <0x1>;
76 #size-cells = <0x1>;
78 compatible = "fpga-region";
79 fpga-mgr = <&fpga_mgr>;
80 };
82 clkmgr@ffd04000 {
83 compatible = "altr,clk-mgr";
84 reg = <0xffd04000 0x1000>;
86 clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
90 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 };
95 cb_intosc_ls_clk: cb_intosc_ls_clk {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 };
100 f2s_free_clk: f2s_free_clk {
101 #clock-cells = <0>;
102 compatible = "fixed-clock";
103 };
105 osc1: osc1 {
106 #clock-cells = <0>;
107 compatible = "fixed-clock";
108 };
110 main_pll: main_pll@40 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 #clock-cells = <0>;
114 compatible = "altr,socfpga-a10-pll-clock";
115 clocks = <&osc1>, <&cb_intosc_ls_clk>,
116 <&f2s_free_clk>;
117 reg = <0x40>;
119 main_mpu_base_clk: main_mpu_base_clk {
120 #clock-cells = <0>;
121 compatible = "altr,socfpga-a10-perip-clk";
122 clocks = <&main_pll>;
123 div-reg = <0x140 0 11>;
124 };
126 main_noc_base_clk: main_noc_base_clk {
127 #clock-cells = <0>;
128 compatible = "altr,socfpga-a10-perip-clk";
129 clocks = <&main_pll>;
130 div-reg = <0x144 0 11>;
131 };
133 main_emaca_clk: main_emaca_clk@68 {
134 #clock-cells = <0>;
135 compatible = "altr,socfpga-a10-perip-clk";
136 clocks = <&main_pll>;
137 reg = <0x68>;
138 };
140 main_emacb_clk: main_emacb_clk@6c {
141 #clock-cells = <0>;
142 compatible = "altr,socfpga-a10-perip-clk";
143 clocks = <&main_pll>;
144 reg = <0x6C>;
145 };
147 main_emac_ptp_clk: main_emac_ptp_clk@70 {
148 #clock-cells = <0>;
149 compatible = "altr,socfpga-a10-perip-clk";
150 clocks = <&main_pll>;
151 reg = <0x70>;
152 };
154 main_gpio_db_clk: main_gpio_db_clk@74 {
155 #clock-cells = <0>;
156 compatible = "altr,socfpga-a10-perip-clk";
157 clocks = <&main_pll>;
158 reg = <0x74>;
159 };
161 main_sdmmc_clk: main_sdmmc_clk@78 {
162 #clock-cells = <0>;
163 compatible = "altr,socfpga-a10-perip-clk"
164 ;
165 clocks = <&main_pll>;
166 reg = <0x78>;
167 };
169 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
170 #clock-cells = <0>;
171 compatible = "altr,socfpga-a10-perip-clk";
172 clocks = <&main_pll>;
173 reg = <0x7C>;
174 };
176 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
177 #clock-cells = <0>;
178 compatible = "altr,socfpga-a10-perip-clk";
179 clocks = <&main_pll>;
180 reg = <0x80>;
181 };
183 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
184 #clock-cells = <0>;
185 compatible = "altr,socfpga-a10-perip-clk";
186 clocks = <&main_pll>;
187 reg = <0x84>;
188 };
190 main_periph_ref_clk: main_periph_ref_clk@9c {
191 #clock-cells = <0>;
192 compatible = "altr,socfpga-a10-perip-clk";
193 clocks = <&main_pll>;
194 reg = <0x9C>;
195 };
196 };
198 periph_pll: periph_pll@c0 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 #clock-cells = <0>;
202 compatible = "altr,socfpga-a10-pll-clock";
203 clocks = <&osc1>, <&cb_intosc_ls_clk>,
204 <&f2s_free_clk>, <&main_periph_ref_clk>;
205 reg = <0xC0>;
207 peri_mpu_base_clk: peri_mpu_base_clk {
208 #clock-cells = <0>;
209 compatible = "altr,socfpga-a10-perip-clk";
210 clocks = <&periph_pll>;
211 div-reg = <0x140 16 11>;
212 };
214 peri_noc_base_clk: peri_noc_base_clk {
215 #clock-cells = <0>;
216 compatible = "altr,socfpga-a10-perip-clk";
217 clocks = <&periph_pll>;
218 div-reg = <0x144 16 11>;
219 };
221 peri_emaca_clk: peri_emaca_clk@e8 {
222 #clock-cells = <0>;
223 compatible = "altr,socfpga-a10-perip-clk";
224 clocks = <&periph_pll>;
225 reg = <0xE8>;
226 };
228 peri_emacb_clk: peri_emacb_clk@ec {
229 #clock-cells = <0>;
230 compatible = "altr,socfpga-a10-perip-clk";
231 clocks = <&periph_pll>;
232 reg = <0xEC>;
233 };
235 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
236 #clock-cells = <0>;
237 compatible = "altr,socfpga-a10-perip-clk";
238 clocks = <&periph_pll>;
239 reg = <0xF0>;
240 };
242 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
243 #clock-cells = <0>;
244 compatible = "altr,socfpga-a10-perip-clk";
245 clocks = <&periph_pll>;
246 reg = <0xF4>;
247 };
249 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
250 #clock-cells = <0>;
251 compatible = "altr,socfpga-a10-perip-clk";
252 clocks = <&periph_pll>;
253 reg = <0xF8>;
254 };
256 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
257 #clock-cells = <0>;
258 compatible = "altr,socfpga-a10-perip-clk";
259 clocks = <&periph_pll>;
260 reg = <0xFC>;
261 };
263 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
264 #clock-cells = <0>;
265 compatible = "altr,socfpga-a10-perip-clk";
266 clocks = <&periph_pll>;
267 reg = <0x100>;
268 };
270 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
271 #clock-cells = <0>;
272 compatible = "altr,socfpga-a10-perip-clk";
273 clocks = <&periph_pll>;
274 reg = <0x104>;
275 };
276 };
278 mpu_free_clk: mpu_free_clk@60 {
279 #clock-cells = <0>;
280 compatible = "altr,socfpga-a10-perip-clk";
281 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
282 <&osc1>, <&cb_intosc_hs_div2_clk>,
283 <&f2s_free_clk>;
284 reg = <0x60>;
285 };
287 noc_free_clk: noc_free_clk@64 {
288 #clock-cells = <0>;
289 compatible = "altr,socfpga-a10-perip-clk";
290 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
291 <&osc1>, <&cb_intosc_hs_div2_clk>,
292 <&f2s_free_clk>;
293 reg = <0x64>;
294 };
296 s2f_user1_free_clk: s2f_user1_free_clk@104 {
297 #clock-cells = <0>;
298 compatible = "altr,socfpga-a10-perip-clk";
299 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
300 <&osc1>, <&cb_intosc_hs_div2_clk>,
301 <&f2s_free_clk>;
302 reg = <0x104>;
303 };
305 sdmmc_free_clk: sdmmc_free_clk@f8 {
306 #clock-cells = <0>;
307 compatible = "altr,socfpga-a10-perip-clk";
308 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
309 <&osc1>, <&cb_intosc_hs_div2_clk>,
310 <&f2s_free_clk>;
311 fixed-divider = <4>;
312 reg = <0xF8>;
313 };
315 l4_sys_free_clk: l4_sys_free_clk {
316 #clock-cells = <0>;
317 compatible = "altr,socfpga-a10-perip-clk";
318 clocks = <&noc_free_clk>;
319 fixed-divider = <4>;
320 };
322 l4_main_clk: l4_main_clk {
323 #clock-cells = <0>;
324 compatible = "altr,socfpga-a10-gate-clk";
325 clocks = <&noc_free_clk>;
326 div-reg = <0xA8 0 2>;
327 clk-gate = <0x48 1>;
328 };
330 l4_mp_clk: l4_mp_clk {
331 #clock-cells = <0>;
332 compatible = "altr,socfpga-a10-gate-clk";
333 clocks = <&noc_free_clk>;
334 div-reg = <0xA8 8 2>;
335 clk-gate = <0x48 2>;
336 };
338 l4_sp_clk: l4_sp_clk {
339 #clock-cells = <0>;
340 compatible = "altr,socfpga-a10-gate-clk";
341 clocks = <&noc_free_clk>;
342 div-reg = <0xA8 16 2>;
343 clk-gate = <0x48 3>;
344 };
346 mpu_periph_clk: mpu_periph_clk {
347 #clock-cells = <0>;
348 compatible = "altr,socfpga-a10-gate-clk";
349 clocks = <&mpu_free_clk>;
350 fixed-divider = <4>;
351 clk-gate = <0x48 0>;
352 };
354 sdmmc_clk: sdmmc_clk {
355 #clock-cells = <0>;
356 compatible = "altr,socfpga-a10-gate-clk";
357 clocks = <&sdmmc_free_clk>;
358 clk-gate = <0xC8 5>;
359 clk-phase = <0 135>;
360 };
362 qspi_clk: qspi_clk {
363 #clock-cells = <0>;
364 compatible = "altr,socfpga-a10-gate-clk";
365 clocks = <&l4_main_clk>;
366 clk-gate = <0xC8 11>;
367 };
369 nand_x_clk: nand_x_clk {
370 #clock-cells = <0>;
371 compatible = "altr,socfpga-a10-gate-clk";
372 clocks = <&l4_mp_clk>;
373 clk-gate = <0xC8 10>;
374 };
376 nand_ecc_clk: nand_ecc_clk {
377 #clock-cells = <0>;
378 compatible = "altr,socfpga-a10-gate-clk";
379 clocks = <&nand_x_clk>;
380 clk-gate = <0xC8 10>;
381 };
383 nand_clk: nand_clk {
384 #clock-cells = <0>;
385 compatible = "altr,socfpga-a10-gate-clk";
386 clocks = <&nand_x_clk>;
387 fixed-divider = <4>;
388 clk-gate = <0xC8 10>;
389 };
391 spi_m_clk: spi_m_clk {
392 #clock-cells = <0>;
393 compatible = "altr,socfpga-a10-gate-clk";
394 clocks = <&l4_main_clk>;
395 clk-gate = <0xC8 9>;
396 };
398 usb_clk: usb_clk {
399 #clock-cells = <0>;
400 compatible = "altr,socfpga-a10-gate-clk";
401 clocks = <&l4_mp_clk>;
402 clk-gate = <0xC8 8>;
403 };
405 s2f_usr1_clk: s2f_usr1_clk {
406 #clock-cells = <0>;
407 compatible = "altr,socfpga-a10-gate-clk";
408 clocks = <&peri_s2f_usr1_clk>;
409 clk-gate = <0xC8 6>;
410 };
411 };
412 };
414 socfpga_axi_setup: stmmac-axi-config {
415 snps,wr_osr_lmt = <0xf>;
416 snps,rd_osr_lmt = <0xf>;
417 snps,blen = <0 0 0 0 16 0 0>;
418 };
420 gmac0: ethernet@ff800000 {
421 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
422 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
423 reg = <0xff800000 0x2000>;
424 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "macirq";
426 /* Filled in by bootloader */
427 mac-address = [00 00 00 00 00 00];
428 snps,multicast-filter-bins = <256>;
429 snps,perfect-filter-entries = <128>;
430 tx-fifo-depth = <4096>;
431 rx-fifo-depth = <16384>;
432 clocks = <&l4_mp_clk>;
433 clock-names = "stmmaceth";
434 resets = <&rst EMAC0_RESET>;
435 reset-names = "stmmaceth";
436 snps,axi-config = <&socfpga_axi_setup>;
437 status = "disabled";
438 };
440 gmac1: ethernet@ff802000 {
441 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
442 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
443 reg = <0xff802000 0x2000>;
444 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "macirq";
446 /* Filled in by bootloader */
447 mac-address = [00 00 00 00 00 00];
448 snps,multicast-filter-bins = <256>;
449 snps,perfect-filter-entries = <128>;
450 tx-fifo-depth = <4096>;
451 rx-fifo-depth = <16384>;
452 clocks = <&l4_mp_clk>;
453 clock-names = "stmmaceth";
454 resets = <&rst EMAC1_RESET>;
455 reset-names = "stmmaceth";
456 snps,axi-config = <&socfpga_axi_setup>;
457 status = "disabled";
458 };
460 gmac2: ethernet@ff804000 {
461 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
462 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
463 reg = <0xff804000 0x2000>;
464 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "macirq";
466 /* Filled in by bootloader */
467 mac-address = [00 00 00 00 00 00];
468 snps,multicast-filter-bins = <256>;
469 snps,perfect-filter-entries = <128>;
470 tx-fifo-depth = <4096>;
471 rx-fifo-depth = <16384>;
472 clocks = <&l4_mp_clk>;
473 resets = <&rst EMAC2_RESET>;
474 clock-names = "stmmaceth";
475 snps,axi-config = <&socfpga_axi_setup>;
476 status = "disabled";
477 };
479 gpio0: gpio@ffc02900 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "snps,dw-apb-gpio";
483 reg = <0xffc02900 0x100>;
484 resets = <&rst GPIO0_RESET>;
485 status = "disabled";
487 porta: gpio-controller@0 {
488 compatible = "snps,dw-apb-gpio-port";
489 gpio-controller;
490 #gpio-cells = <2>;
491 snps,nr-gpios = <29>;
492 reg = <0>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
496 };
497 };
499 gpio1: gpio@ffc02a00 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 compatible = "snps,dw-apb-gpio";
503 reg = <0xffc02a00 0x100>;
504 resets = <&rst GPIO1_RESET>;
505 status = "disabled";
507 portb: gpio-controller@0 {
508 compatible = "snps,dw-apb-gpio-port";
509 gpio-controller;
510 #gpio-cells = <2>;
511 snps,nr-gpios = <29>;
512 reg = <0>;
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
516 };
517 };
519 gpio2: gpio@ffc02b00 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "snps,dw-apb-gpio";
523 reg = <0xffc02b00 0x100>;
524 resets = <&rst GPIO2_RESET>;
525 status = "disabled";
527 portc: gpio-controller@0 {
528 compatible = "snps,dw-apb-gpio-port";
529 gpio-controller;
530 #gpio-cells = <2>;
531 snps,nr-gpios = <27>;
532 reg = <0>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
536 };
537 };
539 fpga_mgr: fpga-mgr@ffd03000 {
540 compatible = "altr,socfpga-a10-fpga-mgr";
541 reg = <0xffd03000 0x100
542 0xffcfe400 0x20>;
543 clocks = <&l4_mp_clk>;
544 resets = <&rst FPGAMGR_RESET>;
545 reset-names = "fpgamgr";
546 };
548 i2c0: i2c@ffc02200 {
549 #address-cells = <1>;
550 #size-cells = <0>;
551 compatible = "snps,designware-i2c";
552 reg = <0xffc02200 0x100>;
553 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&l4_sp_clk>;
555 resets = <&rst I2C0_RESET>;
556 status = "disabled";
557 };
559 i2c1: i2c@ffc02300 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "snps,designware-i2c";
563 reg = <0xffc02300 0x100>;
564 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&l4_sp_clk>;
566 resets = <&rst I2C1_RESET>;
567 status = "disabled";
568 };
570 i2c2: i2c@ffc02400 {
571 #address-cells = <1>;
572 #size-cells = <0>;
573 compatible = "snps,designware-i2c";
574 reg = <0xffc02400 0x100>;
575 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&l4_sp_clk>;
577 resets = <&rst I2C2_RESET>;
578 status = "disabled";
579 };
581 i2c3: i2c@ffc02500 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "snps,designware-i2c";
585 reg = <0xffc02500 0x100>;
586 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&l4_sp_clk>;
588 resets = <&rst I2C3_RESET>;
589 status = "disabled";
590 };
592 i2c4: i2c@ffc02600 {
593 #address-cells = <1>;
594 #size-cells = <0>;
595 compatible = "snps,designware-i2c";
596 reg = <0xffc02600 0x100>;
597 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&l4_sp_clk>;
599 resets = <&rst I2C4_RESET>;
600 status = "disabled";
601 };
603 spi0: spi@ffda4000 {
604 compatible = "snps,dw-apb-ssi";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 reg = <0xffda4000 0x100>;
608 interrupts = <0 101 4>;
609 num-cs = <4>;
610 /*32bit_access;*/
611 clocks = <&spi_m_clk>;
612 resets = <&rst SPIM0_RESET>;
613 status = "disabled";
614 };
616 spi1: spi@ffda5000 {
617 compatible = "snps,dw-apb-ssi";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 reg = <0xffda5000 0x100>;
621 interrupts = <0 102 4>;
622 num-cs = <4>;
623 /*32bit_access;*/
624 tx-dma-channel = <&pdma 16>;
625 rx-dma-channel = <&pdma 17>;
626 clocks = <&spi_m_clk>;
627 resets = <&rst SPIM1_RESET>;
628 status = "disabled";
629 };
631 sdr: sdr@ffcfb100 {
632 compatible = "altr,sdr-ctl", "syscon";
633 reg = <0xffcfb100 0x80>;
634 };
636 L2: l2-cache@fffff000 {
637 compatible = "arm,pl310-cache";
638 reg = <0xfffff000 0x1000>;
639 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
640 cache-unified;
641 cache-level = <2>;
642 prefetch-data = <1>;
643 prefetch-instr = <1>;
644 arm,shared-override;
645 };
647 mmc: dwmmc0@ff808000 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 compatible = "altr,socfpga-dw-mshc";
651 reg = <0xff808000 0x1000>;
652 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
653 fifo-depth = <0x400>;
654 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
655 clock-names = "biu", "ciu";
656 resets = <&rst SDMMC_RESET>;
657 status = "disabled";
658 };
660 nand: nand@ffb90000 {
661 #address-cells = <1>;
662 #size-cells = <1>;
663 compatible = "altr,socfpga-denali-nand";
664 reg = <0xffb90000 0x72000>,
665 <0xffb80000 0x10000>;
666 reg-names = "nand_data", "denali_reg";
667 interrupts = <0 99 4>;
668 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
669 clock-names = "nand", "nand_x", "ecc";
670 resets = <&rst NAND_RESET>;
671 status = "disabled";
672 };
674 ocram: sram@ffe00000 {
675 compatible = "mmio-sram";
676 reg = <0xffe00000 0x40000>;
677 };
679 eccmgr: eccmgr {
680 compatible = "altr,socfpga-a10-ecc-manager";
681 altr,sysmgr-syscon = <&sysmgr>;
682 #address-cells = <1>;
683 #size-cells = <1>;
684 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
685 <0 0 IRQ_TYPE_LEVEL_HIGH>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
688 ranges;
690 sdramedac {
691 compatible = "altr,sdram-edac-a10";
692 altr,sdr-syscon = <&sdr>;
693 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
694 <49 IRQ_TYPE_LEVEL_HIGH>;
695 };
697 l2-ecc@ffd06010 {
698 compatible = "altr,socfpga-a10-l2-ecc";
699 reg = <0xffd06010 0x4>;
700 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
701 <32 IRQ_TYPE_LEVEL_HIGH>;
702 };
704 ocram-ecc@ff8c3000 {
705 compatible = "altr,socfpga-a10-ocram-ecc";
706 reg = <0xff8c3000 0x400>;
707 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
708 <33 IRQ_TYPE_LEVEL_HIGH>;
709 };
711 emac0-rx-ecc@ff8c0800 {
712 compatible = "altr,socfpga-eth-mac-ecc";
713 reg = <0xff8c0800 0x400>;
714 altr,ecc-parent = <&gmac0>;
715 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
716 <36 IRQ_TYPE_LEVEL_HIGH>;
717 };
719 emac0-tx-ecc@ff8c0c00 {
720 compatible = "altr,socfpga-eth-mac-ecc";
721 reg = <0xff8c0c00 0x400>;
722 altr,ecc-parent = <&gmac0>;
723 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
724 <37 IRQ_TYPE_LEVEL_HIGH>;
725 };
727 dma-ecc@ff8c8000 {
728 compatible = "altr,socfpga-dma-ecc";
729 reg = <0xff8c8000 0x400>;
730 altr,ecc-parent = <&pdma>;
731 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
732 <42 IRQ_TYPE_LEVEL_HIGH>;
733 };
735 usb0-ecc@ff8c8800 {
736 compatible = "altr,socfpga-usb-ecc";
737 reg = <0xff8c8800 0x400>;
738 altr,ecc-parent = <&usb0>;
739 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
740 <34 IRQ_TYPE_LEVEL_HIGH>;
741 };
742 };
744 qspi: spi@ff809000 {
745 compatible = "cdns,qspi-nor";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 reg = <0xff809000 0x100>,
749 <0xffa00000 0x100000>;
750 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
751 cdns,fifo-depth = <128>;
752 cdns,fifo-width = <4>;
753 cdns,trigger-address = <0x00000000>;
754 clocks = <&qspi_clk>;
755 resets = <&rst QSPI_RESET>;
756 status = "disabled";
757 };
759 rst: rstmgr@ffd05000 {
760 #reset-cells = <1>;
761 compatible = "altr,rst-mgr";
762 reg = <0xffd05000 0x100>;
763 altr,modrst-offset = <0x20>;
764 };
766 scu: snoop-control-unit@ffffc000 {
767 compatible = "arm,cortex-a9-scu";
768 reg = <0xffffc000 0x100>;
769 };
771 sysmgr: sysmgr@ffd06000 {
772 compatible = "altr,sys-mgr", "syscon";
773 reg = <0xffd06000 0x300>;
774 cpu1-start-addr = <0xffd06230>;
775 };
777 /* Local timer */
778 timer@ffffc600 {
779 compatible = "arm,cortex-a9-twd-timer";
780 reg = <0xffffc600 0x100>;
781 interrupts = <1 13 0xf01>;
782 clocks = <&mpu_periph_clk>;
783 };
785 timer0: timer0@ffc02700 {
786 compatible = "snps,dw-apb-timer";
787 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
788 reg = <0xffc02700 0x100>;
789 clocks = <&l4_sp_clk>;
790 clock-names = "timer";
791 resets = <&rst SPTIMER0_RESET>;
792 reset-names = "timer";
793 };
795 timer1: timer1@ffc02800 {
796 compatible = "snps,dw-apb-timer";
797 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
798 reg = <0xffc02800 0x100>;
799 clocks = <&l4_sp_clk>;
800 clock-names = "timer";
801 resets = <&rst SPTIMER1_RESET>;
802 reset-names = "timer";
803 };
805 timer2: timer2@ffd00000 {
806 compatible = "snps,dw-apb-timer";
807 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
808 reg = <0xffd00000 0x100>;
809 clocks = <&l4_sys_free_clk>;
810 clock-names = "timer";
811 resets = <&rst L4SYSTIMER0_RESET>;
812 reset-names = "timer";
813 };
815 timer3: timer3@ffd00100 {
816 compatible = "snps,dw-apb-timer";
817 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
818 reg = <0xffd01000 0x100>;
819 clocks = <&l4_sys_free_clk>;
820 clock-names = "timer";
821 resets = <&rst L4SYSTIMER1_RESET>;
822 reset-names = "timer";
823 };
825 uart0: serial0@ffc02000 {
826 compatible = "snps,dw-apb-uart";
827 reg = <0xffc02000 0x100>;
828 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
829 reg-shift = <2>;
830 reg-io-width = <4>;
831 clocks = <&l4_sp_clk>;
832 resets = <&rst UART0_RESET>;
833 status = "disabled";
834 };
836 uart1: serial1@ffc02100 {
837 compatible = "snps,dw-apb-uart";
838 reg = <0xffc02100 0x100>;
839 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
840 reg-shift = <2>;
841 reg-io-width = <4>;
842 clocks = <&l4_sp_clk>;
843 resets = <&rst UART1_RESET>;
844 status = "disabled";
845 };
847 usbphy0: usbphy {
848 #phy-cells = <0>;
849 compatible = "usb-nop-xceiv";
850 status = "okay";
851 };
853 usb0: usb@ffb00000 {
854 compatible = "snps,dwc2";
855 reg = <0xffb00000 0xffff>;
856 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&usb_clk>;
858 clock-names = "otg";
859 resets = <&rst USB0_RESET>;
860 reset-names = "dwc2";
861 phys = <&usbphy0>;
862 phy-names = "usb2-phy";
863 status = "disabled";
864 };
866 usb1: usb@ffb40000 {
867 compatible = "snps,dwc2";
868 reg = <0xffb40000 0xffff>;
869 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&usb_clk>;
871 clock-names = "otg";
872 resets = <&rst USB1_RESET>;
873 reset-names = "dwc2";
874 phys = <&usbphy0>;
875 phy-names = "usb2-phy";
876 status = "disabled";
877 };
879 watchdog0: watchdog@ffd00200 {
880 compatible = "snps,dw-wdt";
881 reg = <0xffd00200 0x100>;
882 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&l4_sys_free_clk>;
884 resets = <&rst L4WD0_RESET>;
885 status = "disabled";
886 };
888 watchdog1: watchdog@ffd00300 {
889 compatible = "snps,dw-wdt";
890 reg = <0xffd00300 0x100>;
891 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&l4_sys_free_clk>;
893 resets = <&rst L4WD1_RESET>;
894 status = "disabled";
895 };
896 };
897 };