arch/arm/boot/dts/tegra20-tamonten.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra20.dtsi"
   3
   4 / {
   5         model = "Avionic Design Tamonten SOM";
   6         compatible = "ad,tamonten", "nvidia,tegra20";
   7
   8         aliases {
   9                 rtc0 = "/i2c@7000d000/tps6586x@34";
  10                 rtc1 = "/rtc@7000e000";
  11                 serial0 = &uartd;
  12         };
  13
  14         chosen {
  15                 stdout-path = "serial0:115200n8";
  16         };
  17
  18         memory@0 {
  19                 reg = <0x00000000 0x20000000>;
  20         };
  21
  22         host1x@50000000 {
  23                 hdmi@54280000 {
  24                         vdd-supply = <&hdmi_vdd_reg>;
  25                         pll-supply = <&hdmi_pll_reg>;
  26
  27                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  28                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  29                                 GPIO_ACTIVE_HIGH>;
  30                 };
  31         };
  32
  33         pinmux@70000014 {
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&state_default>;
  36
  37                 state_default: pinmux {
  38                         ata {
  39                                 nvidia,pins = "ata";
  40                                 nvidia,function = "ide";
  41                         };
  42                         atb {
  43                                 nvidia,pins = "atb", "gma", "gme";
  44                                 nvidia,function = "sdio4";
  45                         };
  46                         atc {
  47                                 nvidia,pins = "atc";
  48                                 nvidia,function = "nand";
  49                         };
  50                         atd {
  51                                 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  52                                         "spia", "spib", "spic";
  53                                 nvidia,function = "gmi";
  54                         };
  55                         cdev1 {
  56                                 nvidia,pins = "cdev1";
  57                                 nvidia,function = "plla_out";
  58                         };
  59                         cdev2 {
  60                                 nvidia,pins = "cdev2";
  61                                 nvidia,function = "pllp_out4";
  62                         };
  63                         crtp {
  64                                 nvidia,pins = "crtp";
  65                                 nvidia,function = "crt";
  66                         };
  67                         csus {
  68                                 nvidia,pins = "csus";
  69                                 nvidia,function = "vi_sensor_clk";
  70                         };
  71                         dap1 {
  72                                 nvidia,pins = "dap1";
  73                                 nvidia,function = "dap1";
  74                         };
  75                         dap2 {
  76                                 nvidia,pins = "dap2";
  77                                 nvidia,function = "dap2";
  78                         };
  79                         dap3 {
  80                                 nvidia,pins = "dap3";
  81                                 nvidia,function = "dap3";
  82                         };
  83                         dap4 {
  84                                 nvidia,pins = "dap4";
  85                                 nvidia,function = "dap4";
  86                         };
  87                         dta {
  88                                 nvidia,pins = "dta", "dtd";
  89                                 nvidia,function = "sdio2";
  90                         };
  91                         dtb {
  92                                 nvidia,pins = "dtb", "dtc", "dte";
  93                                 nvidia,function = "rsvd1";
  94                         };
  95                         dtf {
  96                                 nvidia,pins = "dtf";
  97                                 nvidia,function = "i2c3";
  98                         };
  99                         gmc {
 100                                 nvidia,pins = "gmc";
 101                                 nvidia,function = "uartd";
 102                         };
 103                         gpu7 {
 104                                 nvidia,pins = "gpu7";
 105                                 nvidia,function = "rtck";
 106                         };
 107                         gpv {
 108                                 nvidia,pins = "gpv", "slxa", "slxk";
 109                                 nvidia,function = "pcie";
 110                         };
 111                         hdint {
 112                                 nvidia,pins = "hdint";
 113                                 nvidia,function = "hdmi";
 114                         };
 115                         i2cp {
 116                                 nvidia,pins = "i2cp";
 117                                 nvidia,function = "i2cp";
 118                         };
 119                         irrx {
 120                                 nvidia,pins = "irrx", "irtx";
 121                                 nvidia,function = "uarta";
 122                         };
 123                         kbca {
 124                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 125                                         "kbce", "kbcf";
 126                                 nvidia,function = "kbc";
 127                         };
 128                         lcsn {
 129                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
 130                                         "ld3", "ld4", "ld5", "ld6", "ld7",
 131                                         "ld8", "ld9", "ld10", "ld11", "ld12",
 132                                         "ld13", "ld14", "ld15", "ld16", "ld17",
 133                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
 134                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
 135                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
 136                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
 137                                         "lvs";
 138                                 nvidia,function = "displaya";
 139                         };
 140                         owc {
 141                                 nvidia,pins = "owc", "spdi", "spdo", "uac";
 142                                 nvidia,function = "rsvd2";
 143                         };
 144                         pmc {
 145                                 nvidia,pins = "pmc";
 146                                 nvidia,function = "pwr_on";
 147                         };
 148                         rm {
 149                                 nvidia,pins = "rm";
 150                                 nvidia,function = "i2c1";
 151                         };
 152                         sdb {
 153                                 nvidia,pins = "sdb", "sdc", "sdd";
 154                                 nvidia,function = "pwm";
 155                         };
 156                         sdio1 {
 157                                 nvidia,pins = "sdio1";
 158                                 nvidia,function = "sdio1";
 159                         };
 160                         slxc {
 161                                 nvidia,pins = "slxc", "slxd";
 162                                 nvidia,function = "spdif";
 163                         };
 164                         spid {
 165                                 nvidia,pins = "spid", "spie", "spif";
 166                                 nvidia,function = "spi1";
 167                         };
 168                         spig {
 169                                 nvidia,pins = "spig", "spih";
 170                                 nvidia,function = "spi2_alt";
 171                         };
 172                         uaa {
 173                                 nvidia,pins = "uaa", "uab", "uda";
 174                                 nvidia,function = "ulpi";
 175                         };
 176                         uad {
 177                                 nvidia,pins = "uad";
 178                                 nvidia,function = "irda";
 179                         };
 180                         uca {
 181                                 nvidia,pins = "uca", "ucb";
 182                                 nvidia,function = "uartc";
 183                         };
 184                         conf_ata {
 185                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
 186                                         "cdev1", "cdev2", "dap1", "dtb", "gma",
 187                                         "gmb", "gmc", "gmd", "gme", "gpu7",
 188                                         "gpv", "i2cp", "pta", "rm", "slxa",
 189                                         "slxk", "spia", "spib", "uac";
 190                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 191                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 192                         };
 193                         conf_ck32 {
 194                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 195                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
 196                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 197                         };
 198                         conf_csus {
 199                                 nvidia,pins = "csus", "spid", "spif";
 200                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 201                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 202                         };
 203                         conf_crtp {
 204                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
 205                                         "dtc", "dte", "dtf", "gpu", "sdio1",
 206                                         "slxc", "slxd", "spdi", "spdo", "spig",
 207                                         "uda";
 208                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 209                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 210                         };
 211                         conf_ddc {
 212                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
 213                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
 214                                         "sdc";
 215                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 216                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 217                         };
 218                         conf_hdint {
 219                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
 220                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
 221                                         "lvp0", "owc", "sdb";
 222                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 223                         };
 224                         conf_irrx {
 225                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
 226                                         "spie", "spih", "uaa", "uab", "uad",
 227                                         "uca", "ucb";
 228                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 229                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 230                         };
 231                         conf_lc {
 232                                 nvidia,pins = "lc", "ls";
 233                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 234                         };
 235                         conf_ld0 {
 236                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 237                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 238                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 239                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 240                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
 241                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
 242                                         "lvs", "pmc";
 243                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 244                         };
 245                         conf_ld17_0 {
 246                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 247                                         "ld23_22";
 248                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 249                         };
 250                 };
 251
 252                 state_i2cmux_ddc: pinmux_i2cmux_ddc {
 253                         ddc {
 254                                 nvidia,pins = "ddc";
 255                                 nvidia,function = "i2c2";
 256                         };
 257                         pta {
 258                                 nvidia,pins = "pta";
 259                                 nvidia,function = "rsvd4";
 260                         };
 261                 };
 262
 263                 state_i2cmux_pta: pinmux_i2cmux_pta {
 264                         ddc {
 265                                 nvidia,pins = "ddc";
 266                                 nvidia,function = "rsvd4";
 267                         };
 268                         pta {
 269                                 nvidia,pins = "pta";
 270                                 nvidia,function = "i2c2";
 271                         };
 272                 };
 273
 274                 state_i2cmux_idle: pinmux_i2cmux_idle {
 275                         ddc {
 276                                 nvidia,pins = "ddc";
 277                                 nvidia,function = "rsvd4";
 278                         };
 279                         pta {
 280                                 nvidia,pins = "pta";
 281                                 nvidia,function = "rsvd4";
 282                         };
 283                 };
 284         };
 285
 286         i2s@70002800 {
 287                 status = "okay";
 288         };
 289
 290         serial@70006300 {
 291                 status = "okay";
 292         };
 293
 294         i2c@7000c000 {
 295                 clock-frequency = <400000>;
 296                 status = "okay";
 297         };
 298
 299         i2c@7000c400 {
 300                 clock-frequency = <100000>;
 301                 status = "okay";
 302         };
 303
 304         i2cmux {
 305                 compatible = "i2c-mux-pinctrl";
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308
 309                 i2c-parent = <&{/i2c@7000c400}>;
 310
 311                 pinctrl-names = "ddc", "pta", "idle";
 312                 pinctrl-0 = <&state_i2cmux_ddc>;
 313                 pinctrl-1 = <&state_i2cmux_pta>;
 314                 pinctrl-2 = <&state_i2cmux_idle>;
 315
 316                 hdmi_ddc: i2c@0 {
 317                         reg = <0>;
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                 };
 321
 322                 i2c@1 {
 323                         reg = <1>;
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                 };
 327         };
 328
 329         i2c@7000d000 {
 330                 clock-frequency = <400000>;
 331                 status = "okay";
 332
 333                 pmic: tps6586x@34 {
 334                         compatible = "ti,tps6586x";
 335                         reg = <0x34>;
 336                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 337
 338                         ti,system-power-controller;
 339
 340                         #gpio-cells = <2>;
 341                         gpio-controller;
 342
 343                         /* vdd_5v0_reg must be provided by the base board */
 344                         sys-supply = <&vdd_5v0_reg>;
 345                         vin-sm0-supply = <&sys_reg>;
 346                         vin-sm1-supply = <&sys_reg>;
 347                         vin-sm2-supply = <&sys_reg>;
 348                         vinldo01-supply = <&sm2_reg>;
 349                         vinldo23-supply = <&sm2_reg>;
 350                         vinldo4-supply = <&sm2_reg>;
 351                         vinldo678-supply = <&sm2_reg>;
 352                         vinldo9-supply = <&sm2_reg>;
 353
 354                         regulators {
 355                                 sys_reg: sys {
 356                                         regulator-name = "vdd_sys";
 357                                         regulator-always-on;
 358                                 };
 359
 360                                 sm0 {
 361                                         regulator-name = "vdd_sys_sm0,vdd_core";
 362                                         regulator-min-microvolt = <1200000>;
 363                                         regulator-max-microvolt = <1200000>;
 364                                         regulator-always-on;
 365                                 };
 366
 367                                 sm1 {
 368                                         regulator-name = "vdd_sys_sm1,vdd_cpu";
 369                                         regulator-min-microvolt = <1000000>;
 370                                         regulator-max-microvolt = <1000000>;
 371                                         regulator-always-on;
 372                                 };
 373
 374                                 sm2_reg: sm2 {
 375                                         regulator-name = "vdd_sys_sm2,vin_ldo*";
 376                                         regulator-min-microvolt = <3700000>;
 377                                         regulator-max-microvolt = <3700000>;
 378                                         regulator-always-on;
 379                                 };
 380
 381                                 pci_clk_reg: ldo0 {
 382                                         regulator-name = "vdd_ldo0,vddio_pex_clk";
 383                                         regulator-min-microvolt = <3300000>;
 384                                         regulator-max-microvolt = <3300000>;
 385                                 };
 386
 387                                 ldo1 {
 388                                         regulator-name = "vdd_ldo1,avdd_pll*";
 389                                         regulator-min-microvolt = <1100000>;
 390                                         regulator-max-microvolt = <1100000>;
 391                                         regulator-always-on;
 392                                 };
 393
 394                                 ldo2 {
 395                                         regulator-name = "vdd_ldo2,vdd_rtc";
 396                                         regulator-min-microvolt = <1200000>;
 397                                         regulator-max-microvolt = <1200000>;
 398                                 };
 399
 400                                 ldo3 {
 401                                         regulator-name = "vdd_ldo3,avdd_usb*";
 402                                         regulator-min-microvolt = <3300000>;
 403                                         regulator-max-microvolt = <3300000>;
 404                                         regulator-always-on;
 405                                 };
 406
 407                                 ldo4 {
 408                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 409                                         regulator-min-microvolt = <1800000>;
 410                                         regulator-max-microvolt = <1800000>;
 411                                         regulator-always-on;
 412                                 };
 413
 414                                 ldo5 {
 415                                         regulator-name = "vdd_ldo5,vcore_mmc";
 416                                         regulator-min-microvolt = <2850000>;
 417                                         regulator-max-microvolt = <2850000>;
 418                                 };
 419
 420                                 ldo6 {
 421                                         regulator-name = "vdd_ldo6,avdd_vdac";
 422                                         /*
 423                                          * According to the Tegra 2 Automotive
 424                                          * DataSheet, a typical value for this
 425                                          * would be 2.8V, but the PMIC only
 426                                          * supports 2.85V.
 427                                          */
 428                                         regulator-min-microvolt = <2850000>;
 429                                         regulator-max-microvolt = <2850000>;
 430                                 };
 431
 432                                 hdmi_vdd_reg: ldo7 {
 433                                         regulator-name = "vdd_ldo7,avdd_hdmi";
 434                                         regulator-min-microvolt = <3300000>;
 435                                         regulator-max-microvolt = <3300000>;
 436                                 };
 437
 438                                 hdmi_pll_reg: ldo8 {
 439                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 440                                         regulator-min-microvolt = <1800000>;
 441                                         regulator-max-microvolt = <1800000>;
 442                                 };
 443
 444                                 ldo9 {
 445                                         regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
 446                                         /*
 447                                          * According to the Tegra 2 Automotive
 448                                          * DataSheet, a typical value for this
 449                                          * would be 2.8V, but the PMIC only
 450                                          * supports 2.85V.
 451                                          */
 452                                         regulator-min-microvolt = <2850000>;
 453                                         regulator-max-microvolt = <2850000>;
 454                                         regulator-always-on;
 455                                 };
 456
 457                                 ldo_rtc {
 458                                         regulator-name = "vdd_rtc_out";
 459                                         regulator-min-microvolt = <3300000>;
 460                                         regulator-max-microvolt = <3300000>;
 461                                         regulator-always-on;
 462                                 };
 463                         };
 464                 };
 465
 466                 temperature-sensor@4c {
 467                         compatible = "onnn,nct1008";
 468                         reg = <0x4c>;
 469                 };
 470         };
 471
 472         pmc@7000e400 {
 473                 nvidia,invert-interrupt;
 474                 nvidia,suspend-mode = <1>;
 475                 nvidia,cpu-pwr-good-time = <5000>;
 476                 nvidia,cpu-pwr-off-time = <5000>;
 477                 nvidia,core-pwr-good-time = <3845 3845>;
 478                 nvidia,core-pwr-off-time = <3875>;
 479                 nvidia,sys-clock-req-active-high;
 480         };
 481
 482         pcie@80003000 {
 483                 avdd-pex-supply = <&pci_vdd_reg>;
 484                 vdd-pex-supply = <&pci_vdd_reg>;
 485                 avdd-pex-pll-supply = <&pci_vdd_reg>;
 486                 avdd-plle-supply = <&pci_vdd_reg>;
 487                 vddio-pex-clk-supply = <&pci_clk_reg>;
 488         };
 489
 490         usb@c5008000 {
 491                 status = "okay";
 492         };
 493
 494         usb-phy@c5008000 {
 495                 status = "okay";
 496         };
 497
 498         sdhci@c8000600 {
 499                 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
 500                 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
 501                 bus-width = <4>;
 502                 status = "okay";
 503         };
 504
 505         clocks {
 506                 compatible = "simple-bus";
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509
 510                 clk32k_in: clock@0 {
 511                         compatible = "fixed-clock";
 512                         reg = <0>;
 513                         #clock-cells = <0>;
 514                         clock-frequency = <32768>;
 515                 };
 516         };
 517
 518         regulators {
 519                 compatible = "simple-bus";
 520
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523
 524                 pci_vdd_reg: regulator@1 {
 525                         compatible = "regulator-fixed";
 526                         reg = <1>;
 527                         regulator-name = "vdd_1v05";
 528                         regulator-min-microvolt = <1050000>;
 529                         regulator-max-microvolt = <1050000>;
 530                         gpio = <&pmic 2 0>;
 531                         enable-active-high;
 532                 };
 533         };
 534 };