arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB DTU board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * DTU - Digital Tapping Unit
   8  *
   9  * Copyright (C) 2015-2019 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB DTU Board";
  20         compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                         max-brightness = <1>;
  41                 };
  42         };
  43
  44         reg_vcc_3v3_mcu: regulator {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "vcc_3v3_mcu";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49         };
  50 };
  51
  52 &adc0 {
  53         vref-supply = <&reg_vcc_3v3_mcu>;
  54         status = "okay";
  55 };
  56
  57 &adc1 {
  58         vref-supply = <&reg_vcc_3v3_mcu>;
  59         status = "okay";
  60 };
  61
  62 &edma0 {
  63         status = "okay";
  64 };
  65
  66 &edma1 {
  67         status = "okay";
  68 };
  69
  70 &esdhc0 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_esdhc0>;
  73         bus-width = <8>;
  74         non-removable;
  75         no-1-8-v;
  76         keep-power-in-suspend;
  77         status = "okay";
  78 };
  79
  80 &esdhc1 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_esdhc1>;
  83         bus-width = <4>;
  84         status = "okay";
  85 };
  86
  87 &fec1 {
  88         phy-mode = "rmii";
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_fec1>;
  91         status = "okay";
  92
  93         fixed-link {
  94                 speed = <100>;
  95                 full-duplex;
  96         };
  97
  98         mdio1: mdio {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 status = "okay";
 102
 103                 switch0: switch0@0 {
 104                         compatible = "marvell,mv88e6190";
 105                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 106                         pinctrl-names = "default";
 107                         reg = <0>;
 108                         eeprom-length = <65536>;
 109                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 110                         interrupt-parent = <&gpio3>;
 111                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 112                         interrupt-controller;
 113                         #interrupt-cells = <2>;
 114
 115                         ports {
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118
 119                                 port@0 {
 120                                         reg = <0>;
 121                                         label = "cpu";
 122                                         ethernet = <&fec1>;
 123
 124                                         fixed-link {
 125                                                 speed = <100>;
 126                                                 full-duplex;
 127                                         };
 128                                 };
 129
 130                                 port@1 {
 131                                         reg = <1>;
 132                                         label = "eth_cu_100_3";
 133                                 };
 134
 135                                 port@5 {
 136                                         reg = <5>;
 137                                         label = "eth_cu_1000_4";
 138                                 };
 139
 140                                 port@6 {
 141                                         reg = <6>;
 142                                         label = "eth_cu_1000_5";
 143                                 };
 144
 145                                 port@8 {
 146                                         reg = <8>;
 147                                         label = "eth_cu_1000_1";
 148                                 };
 149
 150                                 port@9 {
 151                                         reg = <9>;
 152                                         label = "eth_cu_1000_2";
 153                                         phy-handle = <&phy9>;
 154                                         phy-mode = "sgmii";
 155                                         managed = "in-band-status";
 156                                 };
 157                         };
 158
 159                         mdio1 {
 160                                 compatible = "marvell,mv88e6xxx-mdio-external";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163
 164                                 phy9: phy9@0 {
 165                                         compatible = "ethernet-phy-ieee802.3-c45";
 166                                         pinctrl-0 = <&pinctrl_gpio_phy9>;
 167                                         pinctrl-names = "default";
 168                                         interrupt-parent = <&gpio2>;
 169                                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 170                                         reg = <0>;
 171                                 };
 172                         };
 173                 };
 174         };
 175 };
 176
 177 &i2c0 {
 178         clock-frequency = <100000>;
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_i2c0>;
 181         status = "okay";
 182
 183         gpio6: gpio-expander@22 {
 184                 compatible = "nxp,pca9554";
 185                 reg = <0x22>;
 186                 gpio-controller;
 187                 #gpio-cells = <2>;
 188         };
 189
 190         /* On SSMB */
 191         temperature-sensor@48 {
 192                 compatible = "national,lm75";
 193                 reg = <0x48>;
 194         };
 195
 196         /* On DSB */
 197         temperature-sensor@4d {
 198                 compatible = "national,lm75";
 199                 reg = <0x4d>;
 200         };
 201
 202         eeprom@50 {
 203                 compatible = "atmel,24c04";
 204                 reg = <0x50>;
 205                 label = "nameplate";
 206         };
 207
 208         eeprom@52 {
 209                 compatible = "atmel,24c04";
 210                 reg = <0x52>;
 211         };
 212 };
 213
 214 &uart0 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_uart0>;
 217         status = "okay";
 218 };
 219
 220 &iomuxc {
 221         pinctrl_dspi1: dspi1grp {
 222                 fsl,pins = <
 223                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 224                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 225                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 226                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 227                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 228                 >;
 229         };
 230
 231         pinctrl_esdhc0: esdhc0grp {
 232                 fsl,pins = <
 233                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 234                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 235                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 236                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 237                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 238                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 239                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 240                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 241                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 242                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 243                 >;
 244         };
 245
 246         pinctrl_esdhc1: esdhc1grp {
 247                 fsl,pins = <
 248                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 249                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 250                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 251                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 252                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 253                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 254                 >;
 255         };
 256
 257         pinctrl_fec1: fec1grp {
 258                 fsl,pins = <
 259                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 260                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 261                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 262                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 263                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 264                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 265                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 266                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 267                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 268                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 269                 >;
 270         };
 271
 272         pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
 273                 fsl,pins = <
 274                         VF610_PAD_PTB24__GPIO_94                0x219d
 275                 >;
 276         };
 277
 278         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 279                 fsl,pins = <
 280                         VF610_PAD_PTE2__GPIO_107                0x31c2
 281                         VF610_PAD_PTB28__GPIO_98                0x219d
 282                 >;
 283         };
 284
 285         pinctrl_i2c0: i2c0grp {
 286                 fsl,pins = <
 287                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 288                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 289                 >;
 290         };
 291
 292         pinctrl_i2c1: i2c1grp {
 293                 fsl,pins = <
 294                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 295                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 296                 >;
 297         };
 298
 299         pinctrl_leds_debug: pinctrl-leds-debug {
 300                 fsl,pins = <
 301                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 302                 >;
 303         };
 304
 305         pinctrl_uart0: uart0grp {
 306                 fsl,pins = <
 307                         VF610_PAD_PTB10__UART0_TX               0x21a2
 308                         VF610_PAD_PTB11__UART0_RX               0x21a1
 309                 >;
 310         };
 311 };