arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB SPU3 board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * SPU - Seat Power Unit
   8  *
   9  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB SPU3 Board";
  20         compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                         max-brightness = <1>;
  41                 };
  42         };
  43
  44         reg_vcc_3v3_mcu: regulator {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "vcc_3v3_mcu";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49         };
  50 };
  51
  52 &adc0 {
  53         vref-supply = <&reg_vcc_3v3_mcu>;
  54         status = "okay";
  55 };
  56
  57 &adc1 {
  58         vref-supply = <&reg_vcc_3v3_mcu>;
  59         status = "okay";
  60 };
  61
  62 &dspi1 {
  63         bus-num = <1>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_dspi1>;
  66         /*
  67          * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
  68          * node disabled by default and rely on bootloader to enable
  69          * it when appropriate.
  70          */
  71         status = "disabled";
  72
  73         m25p128@0 {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 compatible = "m25p128", "jedec,spi-nor";
  77                 reg = <0>;
  78                 spi-max-frequency = <50000000>;
  79
  80                 partition@0 {
  81                         label = "m25p128-0";
  82                         reg = <0x0 0x01000000>;
  83                 };
  84         };
  85 };
  86
  87 &edma0 {
  88         status = "okay";
  89 };
  90
  91 &edma1 {
  92         status = "okay";
  93 };
  94
  95 &esdhc0 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_esdhc0>;
  98         bus-width = <8>;
  99         non-removable;
 100         no-1-8-v;
 101         keep-power-in-suspend;
 102         no-sdio;
 103         no-sd;
 104         status = "okay";
 105 };
 106
 107 &esdhc1 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_esdhc1>;
 110         bus-width = <4>;
 111         no-sdio;
 112         status = "okay";
 113 };
 114
 115 &fec1 {
 116         phy-mode = "rmii";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_fec1>;
 119         status = "okay";
 120
 121         fixed-link {
 122                 speed = <100>;
 123                 full-duplex;
 124         };
 125
 126         mdio1: mdio {
 127                 #address-cells = <1>;
 128                 #size-cells = <0>;
 129                 status = "okay";
 130
 131                 switch0: switch0@0 {
 132                         compatible = "marvell,mv88e6190";
 133                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 134                         pinctrl-names = "default";
 135                         reg = <0>;
 136                         eeprom-length = <65536>;
 137                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 138                         interrupt-parent = <&gpio3>;
 139                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 140                         interrupt-controller;
 141                         #interrupt-cells = <2>;
 142
 143                         ports {
 144                                 #address-cells = <1>;
 145                                 #size-cells = <0>;
 146
 147                                 port@0 {
 148                                         reg = <0>;
 149                                         label = "cpu";
 150                                         ethernet = <&fec1>;
 151
 152                                         fixed-link {
 153                                                 speed = <100>;
 154                                                 full-duplex;
 155                                         };
 156                                 };
 157
 158                                 port@1 {
 159                                         reg = <1>;
 160                                         label = "eth_cu_1000_1";
 161                                 };
 162
 163                                 port@2 {
 164                                         reg = <2>;
 165                                         label = "eth_cu_1000_2";
 166                                 };
 167
 168                                 port@3 {
 169                                         reg = <3>;
 170                                         label = "eth_cu_1000_3";
 171                                 };
 172
 173                                 port@4 {
 174                                         reg = <4>;
 175                                         label = "eth_cu_1000_4";
 176                                 };
 177
 178                                 port@5 {
 179                                         reg = <5>;
 180                                         label = "eth_cu_1000_5";
 181                                 };
 182
 183                                 port@6 {
 184                                         reg = <6>;
 185                                         label = "eth_cu_1000_6";
 186                                 };
 187                         };
 188                 };
 189         };
 190 };
 191
 192 &i2c0 {
 193         clock-frequency = <100000>;
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_i2c0>;
 196         status = "okay";
 197
 198         gpio6: pca9505@22 {
 199                 compatible = "nxp,pca9554";
 200                 reg = <0x22>;
 201                 gpio-controller;
 202                 #gpio-cells = <2>;
 203         };
 204
 205         lm75@48 {
 206                 compatible = "national,lm75";
 207                 reg = <0x48>;
 208         };
 209
 210         at24c04@50 {
 211                 compatible = "atmel,24c04";
 212                 reg = <0x50>;
 213                 label = "nameplate";
 214         };
 215
 216         at24c04@52 {
 217                 compatible = "atmel,24c04";
 218                 reg = <0x52>;
 219         };
 220 };
 221
 222 &uart0 {
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_uart0>;
 225         status = "okay";
 226 };
 227
 228 &uart1 {
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_uart1>;
 231         status = "okay";
 232
 233         rave-sp {
 234                 compatible = "zii,rave-sp-rdu2";
 235                 current-speed = <1000000>;
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238
 239                 watchdog {
 240                         compatible = "zii,rave-sp-watchdog";
 241                 };
 242
 243                 eeprom@a3 {
 244                         compatible = "zii,rave-sp-eeprom";
 245                         reg = <0xa3 0x4000>;
 246                         #address-cells = <1>;
 247                         #size-cells = <1>;
 248                         zii,eeprom-name = "main-eeprom";
 249                 };
 250         };
 251 };
 252
 253 &iomuxc {
 254         pinctrl_dspi1: dspi1grp {
 255                 fsl,pins = <
 256                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 257                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 258                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 259                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 260                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 261                 >;
 262         };
 263
 264         pinctrl_esdhc0: esdhc0grp {
 265                 fsl,pins = <
 266                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 267                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 268                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 269                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 270                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 271                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 272                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 273                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 274                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 275                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 276                 >;
 277         };
 278
 279         pinctrl_esdhc1: esdhc1grp {
 280                 fsl,pins = <
 281                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 282                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 283                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 284                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 285                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 286                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 287                 >;
 288         };
 289
 290         pinctrl_fec1: fec1grp {
 291                 fsl,pins = <
 292                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 293                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 294                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 295                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 296                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 297                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 298                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 299                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 300                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 301                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 302                 >;
 303         };
 304
 305         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 306                 fsl,pins = <
 307                         VF610_PAD_PTE2__GPIO_107                0x31c2
 308                         VF610_PAD_PTB28__GPIO_98                0x219d
 309                 >;
 310         };
 311
 312         pinctrl_i2c0: i2c0grp {
 313                 fsl,pins = <
 314                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 315                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 316                 >;
 317         };
 318
 319         pinctrl_i2c1: i2c1grp {
 320                 fsl,pins = <
 321                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 322                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 323                 >;
 324         };
 325
 326         pinctrl_leds_debug: pinctrl-leds-debug {
 327                 fsl,pins = <
 328                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 329                 >;
 330         };
 331
 332         pinctrl_uart0: uart0grp {
 333                 fsl,pins = <
 334                         VF610_PAD_PTB10__UART0_TX               0x21a2
 335                         VF610_PAD_PTB11__UART0_RX               0x21a1
 336                 >;
 337         };
 338
 339         pinctrl_uart1: uart1grp {
 340                 fsl,pins = <
 341                         VF610_PAD_PTB23__UART1_TX               0x21a2
 342                         VF610_PAD_PTB24__UART1_RX               0x21a1
 343                 >;
 344         };
 345 };