arch/arm/mach-oxnas/platsmp.c

   1 /*
   2  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   3  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
   4  * Copyright (C) 2002 ARM Ltd.
   5  * All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/io.h>
  12 #include <linux/delay.h>
  13 #include <linux/of.h>
  14 #include <linux/of_address.h>
  15
  16 #include <asm/cacheflush.h>
  17 #include <asm/cp15.h>
  18 #include <asm/smp_plat.h>
  19 #include <asm/smp_scu.h>
  20
  21 extern void ox820_secondary_startup(void);
  22
  23 static void __iomem *cpu_ctrl;
  24 static void __iomem *gic_cpu_ctrl;
  25
  26 #define HOLDINGPEN_CPU_OFFSET           0xc8
  27 #define HOLDINGPEN_LOCATION_OFFSET      0xc4
  28
  29 #define GIC_NCPU_OFFSET(cpu)            (0x100 + (cpu)*0x100)
  30 #define GIC_CPU_CTRL                    0x00
  31 #define GIC_CPU_CTRL_ENABLE             1
  32
  33 int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
  34 {
  35         /*
  36          * Write the address of secondary startup into the
  37          * system-wide flags register. The BootMonitor waits
  38          * until it receives a soft interrupt, and then the
  39          * secondary CPU branches to this address.
  40          */
  41         writel(virt_to_phys(ox820_secondary_startup),
  42                         cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
  43
  44         writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
  45
  46         /*
  47          * Enable GIC cpu interface in CPU Interface Control Register
  48          */
  49         writel(GIC_CPU_CTRL_ENABLE,
  50                 gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
  51
  52         /*
  53          * Send the secondary CPU a soft interrupt, thereby causing
  54          * the boot monitor to read the system wide flags register,
  55          * and branch to the address found there.
  56          */
  57         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  58
  59         return 0;
  60 }
  61
  62 static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
  63 {
  64         struct device_node *np;
  65         void __iomem *scu_base;
  66
  67         np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
  68         scu_base = of_iomap(np, 0);
  69         of_node_put(np);
  70         if (!scu_base)
  71                 return;
  72
  73         /* Remap CPU Interrupt Interface Registers */
  74         np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
  75         gic_cpu_ctrl = of_iomap(np, 1);
  76         of_node_put(np);
  77         if (!gic_cpu_ctrl)
  78                 goto unmap_scu;
  79
  80         np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
  81         cpu_ctrl = of_iomap(np, 0);
  82         of_node_put(np);
  83         if (!cpu_ctrl)
  84                 goto unmap_scu;
  85
  86         scu_enable(scu_base);
  87         flush_cache_all();
  88
  89 unmap_scu:
  90         iounmap(scu_base);
  91 }
  92
  93 static const struct smp_operations ox820_smp_ops __initconst = {
  94         .smp_prepare_cpus       = ox820_smp_prepare_cpus,
  95         .smp_boot_secondary     = ox820_boot_secondary,
  96 };
  97
  98 CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);