arch/c6x/boot/dts/tms320c6457.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6
   7         cpus {
   8                 #address-cells = <1>;
   9                 #size-cells = <0>;
  10
  11                 cpu@0 {
  12                         device_type = "cpu";
  13                         model = "ti,c64x+";
  14                         reg = <0>;
  15                 };
  16         };
  17
  18         soc {
  19                 compatible = "simple-bus";
  20                 model = "tms320c6457";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 core_pic: interrupt-controller {
  26                         interrupt-controller;
  27                         #interrupt-cells = <1>;
  28                         compatible = "ti,c64x+core-pic";
  29                 };
  30
  31                 megamod_pic: interrupt-controller@1800000 {
  32                         compatible = "ti,c64x+megamod-pic";
  33                         interrupt-controller;
  34                         #interrupt-cells = <1>;
  35                         interrupt-parent = <&core_pic>;
  36                         reg = <0x1800000 0x1000>;
  37                 };
  38
  39                 cache-controller@1840000 {
  40                         compatible = "ti,c64x+cache";
  41                         reg = <0x01840000 0x8400>;
  42                 };
  43
  44                 device-state-controller@2880800 {
  45                         compatible = "ti,c64x+dscr";
  46                         reg = <0x02880800 0x400>;
  47
  48                         ti,dscr-devstat = <0x20>;
  49                         ti,dscr-silicon-rev = <0x18 28 0xf>;
  50                         ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
  51                                                  0x118 0 0 1 2>;
  52                         ti,dscr-kick-regs = <0x38 0x83E70B13
  53                                              0x3c 0x95A4F1E0>;
  54                 };
  55
  56                 timer0: timer@2940000 {
  57                         compatible = "ti,c64x+timer64";
  58                         reg = <0x2940000 0x40>;
  59                 };
  60
  61                 clock-controller@29a0000 {
  62                         compatible = "ti,c6457-pll", "ti,c64x+pll";
  63                         reg = <0x029a0000 0x200>;
  64                         ti,c64x+pll-bypass-delay = <300>;
  65                         ti,c64x+pll-reset-delay = <24000>;
  66                         ti,c64x+pll-lock-delay = <50000>;
  67                 };
  68         };
  69 };