arch/hexagon/include/asm/pgtable.h

   1 /*
   2  * Page table support for the Hexagon architecture
   3  *
   4  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18  * 02110-1301, USA.
  19  */
  20
  21 #ifndef _ASM_PGTABLE_H
  22 #define _ASM_PGTABLE_H
  23
  24 /*
  25  * Page table definitions for Qualcomm Hexagon processor.
  26  */
  27 #include <asm/page.h>
  28 #define __ARCH_USE_5LEVEL_HACK
  29 #include <asm-generic/pgtable-nopmd.h>
  30
  31 /* A handy thing to have if one has the RAM. Declared in head.S */
  32 extern unsigned long empty_zero_page;
  33
  34 /*
  35  * The PTE model described here is that of the Hexagon Virtual Machine,
  36  * which autonomously walks 2-level page tables.  At a lower level, we
  37  * also describe the RISCish software-loaded TLB entry structure of
  38  * the underlying Hexagon processor. A kernel built to run on the
  39  * virtual machine has no need to know about the underlying hardware.
  40  */
  41 #include <asm/vm_mmu.h>
  42
  43 /*
  44  * To maximize the comfort level for the PTE manipulation macros,
  45  * define the "well known" architecture-specific bits.
  46  */
  47 #define _PAGE_READ      __HVM_PTE_R
  48 #define _PAGE_WRITE     __HVM_PTE_W
  49 #define _PAGE_EXECUTE   __HVM_PTE_X
  50 #define _PAGE_USER      __HVM_PTE_U
  51
  52 /*
  53  * We have a total of 4 "soft" bits available in the abstract PTE.
  54  * The two mandatory software bits are Dirty and Accessed.
  55  * To make nonlinear swap work according to the more recent
  56  * model, we want a low order "Present" bit to indicate whether
  57  * the PTE describes MMU programming or swap space.
  58  */
  59 #define _PAGE_PRESENT   (1<<0)
  60 #define _PAGE_DIRTY     (1<<1)
  61 #define _PAGE_ACCESSED  (1<<2)
  62
  63 /*
  64  * For now, let's say that Valid and Present are the same thing.
  65  * Alternatively, we could say that it's the "or" of R, W, and X
  66  * permissions.
  67  */
  68 #define _PAGE_VALID     _PAGE_PRESENT
  69
  70 /*
  71  * We're not defining _PAGE_GLOBAL here, since there's no concept
  72  * of global pages or ASIDs exposed to the Hexagon Virtual Machine,
  73  * and we want to use the same page table structures and macros in
  74  * the native kernel as we do in the virtual machine kernel.
  75  * So we'll put up with a bit of inefficiency for now...
  76  */
  77
  78 /*
  79  * Top "FOURTH" level (pgd), which for the Hexagon VM is really
  80  * only the second from the bottom, pgd and pud both being collapsed.
  81  * Each entry represents 4MB of virtual address space, 4K of table
  82  * thus maps the full 4GB.
  83  */
  84 #define PGDIR_SHIFT 22
  85 #define PTRS_PER_PGD 1024
  86
  87 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
  88 #define PGDIR_MASK (~(PGDIR_SIZE-1))
  89
  90 #ifdef CONFIG_PAGE_SIZE_4KB
  91 #define PTRS_PER_PTE 1024
  92 #endif
  93
  94 #ifdef CONFIG_PAGE_SIZE_16KB
  95 #define PTRS_PER_PTE 256
  96 #endif
  97
  98 #ifdef CONFIG_PAGE_SIZE_64KB
  99 #define PTRS_PER_PTE 64
 100 #endif
 101
 102 #ifdef CONFIG_PAGE_SIZE_256KB
 103 #define PTRS_PER_PTE 16
 104 #endif
 105
 106 #ifdef CONFIG_PAGE_SIZE_1MB
 107 #define PTRS_PER_PTE 4
 108 #endif
 109
 110 /*  Any bigger and the PTE disappears.  */
 111 #define pgd_ERROR(e) \
 112         printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\
 113                 pgd_val(e))
 114
 115 /*
 116  * Page Protection Constants. Includes (in this variant) cache attributes.
 117  */
 118 extern unsigned long _dflt_cache_att;
 119
 120 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 121                                 _dflt_cache_att)
 122 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 123                                 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
 124 #define PAGE_COPY       PAGE_READONLY
 125 #define PAGE_EXEC       __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 126                                 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att)
 127 #define PAGE_COPY_EXEC  PAGE_EXEC
 128 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 129                                 _PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att)
 130 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_READ | \
 131                                 _PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att)
 132
 133
 134 /*
 135  * Aliases for mapping mmap() protection bits to page protections.
 136  * These get used for static initialization, so using the _dflt_cache_att
 137  * variable for the default cache attribute isn't workable. If the
 138  * default gets changed at boot time, the boot option code has to
 139  * update data structures like the protaction_map[] array.
 140  */
 141 #define CACHEDEF        (CACHE_DEFAULT << 6)
 142
 143 /* Private (copy-on-write) page protections. */
 144 #define __P000 __pgprot(_PAGE_PRESENT | _PAGE_USER | CACHEDEF)
 145 #define __P001 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | CACHEDEF)
 146 #define __P010 __P000   /* Write-only copy-on-write */
 147 #define __P011 __P001   /* Read/Write copy-on-write */
 148 #define __P100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 149                         _PAGE_EXECUTE | CACHEDEF)
 150 #define __P101 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_EXECUTE | \
 151                         _PAGE_READ | CACHEDEF)
 152 #define __P110 __P100   /* Write/execute copy-on-write */
 153 #define __P111 __P101   /* Read/Write/Execute, copy-on-write */
 154
 155 /* Shared page protections. */
 156 #define __S000 __P000
 157 #define __S001 __P001
 158 #define __S010 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 159                         _PAGE_WRITE | CACHEDEF)
 160 #define __S011 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 161                         _PAGE_WRITE | CACHEDEF)
 162 #define __S100 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 163                         _PAGE_EXECUTE | CACHEDEF)
 164 #define __S101 __P101
 165 #define __S110 __pgprot(_PAGE_PRESENT | _PAGE_USER | \
 166                         _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF)
 167 #define __S111 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \
 168                         _PAGE_EXECUTE | _PAGE_WRITE | CACHEDEF)
 169
 170 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];  /* located in head.S */
 171
 172 /* Seems to be zero even in architectures where the zero page is firewalled? */
 173 #define FIRST_USER_ADDRESS 0UL
 174 #define pte_special(pte)        0
 175 #define pte_mkspecial(pte)      (pte)
 176
 177 /*  HUGETLB not working currently  */
 178 #ifdef CONFIG_HUGETLB_PAGE
 179 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE)
 180 #endif
 181
 182 /*
 183  * For now, assume that higher-level code will do TLB/MMU invalidations
 184  * and don't insert that overhead into this low-level function.
 185  */
 186 extern void sync_icache_dcache(pte_t pte);
 187
 188 #define pte_present_exec_user(pte) \
 189         ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \
 190         (_PAGE_EXECUTE | _PAGE_USER))
 191
 192 static inline void set_pte(pte_t *ptep, pte_t pteval)
 193 {
 194         /*  should really be using pte_exec, if it weren't declared later. */
 195         if (pte_present_exec_user(pteval))
 196                 sync_icache_dcache(pteval);
 197
 198         *ptep = pteval;
 199 }
 200
 201 /*
 202  * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid
 203  * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE
 204  * (Linux PTE), the key is to have bits 11..9 all zero.  We'd use 0x7
 205  * as a universal null entry, but some of those least significant bits
 206  * are interpreted by software.
 207  */
 208 #define _NULL_PMD       0x7
 209 #define _NULL_PTE       0x0
 210
 211 static inline void pmd_clear(pmd_t *pmd_entry_ptr)
 212 {
 213          pmd_val(*pmd_entry_ptr) = _NULL_PMD;
 214 }
 215
 216 /*
 217  * Conveniently, a null PTE value is invalid.
 218  */
 219 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 220                                 pte_t *ptep)
 221 {
 222         pte_val(*ptep) = _NULL_PTE;
 223 }
 224
 225 #ifdef NEED_PMD_INDEX_DESPITE_BEING_2_LEVEL
 226 /**
 227  * pmd_index - returns the index of the entry in the PMD page
 228  * which would control the given virtual address
 229  */
 230 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 231
 232 #endif
 233
 234 /**
 235  * pgd_index - returns the index of the entry in the PGD page
 236  * which would control the given virtual address
 237  *
 238  * This returns the *index* for the address in the pgd_t
 239  */
 240 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 241
 242 /*
 243  * pgd_offset - find an offset in a page-table-directory
 244  */
 245 #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
 246
 247 /*
 248  * pgd_offset_k - get kernel (init_mm) pgd entry pointer for addr
 249  */
 250 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 251
 252 /**
 253  * pmd_none - check if pmd_entry is mapped
 254  * @pmd_entry:  pmd entry
 255  *
 256  * MIPS checks it against that "invalid pte table" thing.
 257  */
 258 static inline int pmd_none(pmd_t pmd)
 259 {
 260         return pmd_val(pmd) == _NULL_PMD;
 261 }
 262
 263 /**
 264  * pmd_present - is there a page table behind this?
 265  * Essentially the inverse of pmd_none.  We maybe
 266  * save an inline instruction by defining it this
 267  * way, instead of simply "!pmd_none".
 268  */
 269 static inline int pmd_present(pmd_t pmd)
 270 {
 271         return pmd_val(pmd) != (unsigned long)_NULL_PMD;
 272 }
 273
 274 /**
 275  * pmd_bad - check if a PMD entry is "bad". That might mean swapped out.
 276  * As we have no known cause of badness, it's null, as it is for many
 277  * architectures.
 278  */
 279 static inline int pmd_bad(pmd_t pmd)
 280 {
 281         return 0;
 282 }
 283
 284 /*
 285  * pmd_page - converts a PMD entry to a page pointer
 286  */
 287 #define pmd_page(pmd)  (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 288 #define pmd_pgtable(pmd) pmd_page(pmd)
 289
 290 /**
 291  * pte_none - check if pte is mapped
 292  * @pte: pte_t entry
 293  */
 294 static inline int pte_none(pte_t pte)
 295 {
 296         return pte_val(pte) == _NULL_PTE;
 297 };
 298
 299 /*
 300  * pte_present - check if page is present
 301  */
 302 static inline int pte_present(pte_t pte)
 303 {
 304         return pte_val(pte) & _PAGE_PRESENT;
 305 }
 306
 307 /* mk_pte - make a PTE out of a page pointer and protection bits */
 308 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
 309
 310 /* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */
 311 #define pte_page(x) pfn_to_page(pte_pfn(x))
 312
 313 /* pte_mkold - mark PTE as not recently accessed */
 314 static inline pte_t pte_mkold(pte_t pte)
 315 {
 316         pte_val(pte) &= ~_PAGE_ACCESSED;
 317         return pte;
 318 }
 319
 320 /* pte_mkyoung - mark PTE as recently accessed */
 321 static inline pte_t pte_mkyoung(pte_t pte)
 322 {
 323         pte_val(pte) |= _PAGE_ACCESSED;
 324         return pte;
 325 }
 326
 327 /* pte_mkclean - mark page as in sync with backing store */
 328 static inline pte_t pte_mkclean(pte_t pte)
 329 {
 330         pte_val(pte) &= ~_PAGE_DIRTY;
 331         return pte;
 332 }
 333
 334 /* pte_mkdirty - mark page as modified */
 335 static inline pte_t pte_mkdirty(pte_t pte)
 336 {
 337         pte_val(pte) |= _PAGE_DIRTY;
 338         return pte;
 339 }
 340
 341 /* pte_young - "is PTE marked as accessed"? */
 342 static inline int pte_young(pte_t pte)
 343 {
 344         return pte_val(pte) & _PAGE_ACCESSED;
 345 }
 346
 347 /* pte_dirty - "is PTE dirty?" */
 348 static inline int pte_dirty(pte_t pte)
 349 {
 350         return pte_val(pte) & _PAGE_DIRTY;
 351 }
 352
 353 /* pte_modify - set protection bits on PTE */
 354 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
 355 {
 356         pte_val(pte) &= PAGE_MASK;
 357         pte_val(pte) |= pgprot_val(prot);
 358         return pte;
 359 }
 360
 361 /* pte_wrprotect - mark page as not writable */
 362 static inline pte_t pte_wrprotect(pte_t pte)
 363 {
 364         pte_val(pte) &= ~_PAGE_WRITE;
 365         return pte;
 366 }
 367
 368 /* pte_mkwrite - mark page as writable */
 369 static inline pte_t pte_mkwrite(pte_t pte)
 370 {
 371         pte_val(pte) |= _PAGE_WRITE;
 372         return pte;
 373 }
 374
 375 /* pte_mkexec - mark PTE as executable */
 376 static inline pte_t pte_mkexec(pte_t pte)
 377 {
 378         pte_val(pte) |= _PAGE_EXECUTE;
 379         return pte;
 380 }
 381
 382 /* pte_read - "is PTE marked as readable?" */
 383 static inline int pte_read(pte_t pte)
 384 {
 385         return pte_val(pte) & _PAGE_READ;
 386 }
 387
 388 /* pte_write - "is PTE marked as writable?" */
 389 static inline int pte_write(pte_t pte)
 390 {
 391         return pte_val(pte) & _PAGE_WRITE;
 392 }
 393
 394
 395 /* pte_exec - "is PTE marked as executable?" */
 396 static inline int pte_exec(pte_t pte)
 397 {
 398         return pte_val(pte) & _PAGE_EXECUTE;
 399 }
 400
 401 /* __pte_to_swp_entry - extract swap entry from PTE */
 402 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 403
 404 /* __swp_entry_to_pte - extract PTE from swap entry */
 405 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
 406
 407 /* pfn_pte - convert page number and protection value to page table entry */
 408 #define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot))
 409
 410 /* pte_pfn - convert pte to page frame number */
 411 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
 412 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
 413
 414 /*
 415  * set_pte_at - update page table and do whatever magic may be
 416  * necessary to make the underlying hardware/firmware take note.
 417  *
 418  * VM may require a virtual instruction to alert the MMU.
 419  */
 420 #define set_pte_at(mm, addr, ptep, pte) set_pte(ptep, pte)
 421
 422 /*
 423  * May need to invoke the virtual machine as well...
 424  */
 425 #define pte_unmap(pte)          do { } while (0)
 426 #define pte_unmap_nested(pte)   do { } while (0)
 427
 428 /*
 429  * pte_offset_map - returns the linear address of the page table entry
 430  * corresponding to an address
 431  */
 432 #define pte_offset_map(dir, address)                                    \
 433         ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 434
 435 #define pte_offset_map_nested(pmd, addr) pte_offset_map(pmd, addr)
 436
 437 /* pte_offset_kernel - kernel version of pte_offset */
 438 #define pte_offset_kernel(dir, address) \
 439         ((pte_t *) (unsigned long) __va(pmd_val(*dir) & PAGE_MASK) \
 440                                 +  __pte_offset(address))
 441
 442 /* ZERO_PAGE - returns the globally shared zero page */
 443 #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
 444
 445 #define __pte_offset(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 446
 447 /*  I think this is in case we have page table caches; needed by init/main.c  */
 448 #define pgtable_cache_init()    do { } while (0)
 449
 450 /*
 451  * Swap/file PTE definitions.  If _PAGE_PRESENT is zero, the rest of the PTE is
 452  * interpreted as swap information.  The remaining free bits are interpreted as
 453  * swap type/offset tuple.  Rather than have the TLB fill handler test
 454  * _PAGE_PRESENT, we're going to reserve the permissions bits and set them to
 455  * all zeros for swap entries, which speeds up the miss handler at the cost of
 456  * 3 bits of offset.  That trade-off can be revisited if necessary, but Hexagon
 457  * processor architecture and target applications suggest a lot of TLB misses
 458  * and not much swap space.
 459  *
 460  * Format of swap PTE:
 461  *      bit     0:      Present (zero)
 462  *      bits    1-5:    swap type (arch independent layer uses 5 bits max)
 463  *      bits    6-9:    bits 3:0 of offset
 464  *      bits    10-12:  effectively _PAGE_PROTNONE (all zero)
 465  *      bits    13-31:  bits 22:4 of swap offset
 466  *
 467  * The split offset makes some of the following macros a little gnarly,
 468  * but there's plenty of precedent for this sort of thing.
 469  */
 470
 471 /* Used for swap PTEs */
 472 #define __swp_type(swp_pte)             (((swp_pte).val >> 1) & 0x1f)
 473
 474 #define __swp_offset(swp_pte) \
 475         ((((swp_pte).val >> 6) & 0xf) | (((swp_pte).val >> 9) & 0x7ffff0))
 476
 477 #define __swp_entry(type, offset) \
 478         ((swp_entry_t)  { \
 479                 ((type << 1) | \
 480                  ((offset & 0x7ffff0) << 9) | ((offset & 0xf) << 6)) })
 481
 482 /*  Oh boy.  There are a lot of possible arch overrides found in this file.  */
 483 #include <asm-generic/pgtable.h>
 484
 485 #endif