arch/parisc/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * include/asm-parisc/cache.h
   4  */
   5
   6 #ifndef __ARCH_PARISC_CACHE_H
   7 #define __ARCH_PARISC_CACHE_H
   8
   9 #include <asm/alternative.h>
  10
  11 /*
  12  * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
  13  * have 32-byte cachelines.  The L1 length appears to be 16 bytes but this
  14  * is not clearly documented.
  15  */
  16 #define L1_CACHE_BYTES 16
  17 #define L1_CACHE_SHIFT 4
  18
  19 #ifndef __ASSEMBLY__
  20
  21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
  22
  23 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  24
  25 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
  26
  27 /* Read-only memory is marked before mark_rodata_ro() is called. */
  28 #define __ro_after_init __read_mostly
  29
  30 void parisc_cache_init(void);   /* initializes cache-flushing */
  31 void disable_sr_hashing_asm(int); /* low level support for above */
  32 void disable_sr_hashing(void);   /* turns off space register hashing */
  33 void free_sid(unsigned long);
  34 unsigned long alloc_sid(void);
  35
  36 struct seq_file;
  37 extern void show_cache_info(struct seq_file *m);
  38
  39 extern int split_tlb;
  40 extern int dcache_stride;
  41 extern int icache_stride;
  42 extern struct pdc_cache_info cache_info;
  43 void parisc_setup_cache_timing(void);
  44
  45 #define pdtlb(addr)     asm volatile("pdtlb 0(%%sr1,%0)" \
  46                         ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  47                         : : "r" (addr))
  48 #define pitlb(addr)     asm volatile("pitlb 0(%%sr1,%0)" \
  49                         ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  50                         ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
  51                         : : "r" (addr))
  52 #define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \
  53                         ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  54                         : : "r" (addr))
  55
  56 #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
  57                         ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
  58                         ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
  59                         : : "r" (addr))
  60 #define asm_io_sync()   asm volatile("sync" \
  61                         ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
  62                         ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :: )
  63
  64 #endif /* ! __ASSEMBLY__ */
  65
  66 /* Classes of processor wrt: disabling space register hashing */
  67
  68 #define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
  69 #define SRHASH_PCXL     1   /* pcxl */
  70 #define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
  71
  72 #endif