arch/riscv/include/asm/cacheflush.h

   1 /*
   2  * Copyright (C) 2015 Regents of the University of California
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #ifndef _ASM_RISCV_CACHEFLUSH_H
  15 #define _ASM_RISCV_CACHEFLUSH_H
  16
  17 #include <asm-generic/cacheflush.h>
  18
  19 #undef flush_icache_range
  20 #undef flush_icache_user_range
  21 #undef flush_dcache_page
  22
  23 static inline void local_flush_icache_all(void)
  24 {
  25         asm volatile ("fence.i" ::: "memory");
  26 }
  27
  28 #define PG_dcache_clean PG_arch_1
  29
  30 static inline void flush_dcache_page(struct page *page)
  31 {
  32         if (test_bit(PG_dcache_clean, &page->flags))
  33                 clear_bit(PG_dcache_clean, &page->flags);
  34 }
  35
  36 /*
  37  * RISC-V doesn't have an instruction to flush parts of the instruction cache,
  38  * so instead we just flush the whole thing.
  39  */
  40 #define flush_icache_range(start, end) flush_icache_all()
  41 #define flush_icache_user_range(vma, pg, addr, len) flush_icache_all()
  42
  43 #ifndef CONFIG_SMP
  44
  45 #define flush_icache_all() local_flush_icache_all()
  46 #define flush_icache_mm(mm, local) flush_icache_all()
  47
  48 #else /* CONFIG_SMP */
  49
  50 #define flush_icache_all() sbi_remote_fence_i(NULL)
  51 void flush_icache_mm(struct mm_struct *mm, bool local);
  52
  53 #endif /* CONFIG_SMP */
  54
  55 /*
  56  * Bits in sys_riscv_flush_icache()'s flags argument.
  57  */
  58 #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
  59 #define SYS_RISCV_FLUSH_ICACHE_ALL   (SYS_RISCV_FLUSH_ICACHE_LOCAL)
  60
  61 #endif /* _ASM_RISCV_CACHEFLUSH_H */