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mtd: nand: omap: Fix comment in platform data using wrong Kconfig symbol
[linux/fpc-iii.git] / arch / sparc / kernel / pci_sun4v.c
bloba8af6023c1263f7b43a4a52f52089235493923bd
1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_sun4v.c: SUN4V specific PCI controller support.
3 *
4 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
13 #include <linux/percpu.h>
14 #include <linux/irq.h>
15 #include <linux/msi.h>
16 #include <linux/export.h>
17 #include <linux/log2.h>
18 #include <linux/of_device.h>
19 #include <asm/iommu-common.h>
20
21 #include <asm/iommu.h>
22 #include <asm/irq.h>
23 #include <asm/hypervisor.h>
24 #include <asm/prom.h>
25
26 #include "pci_impl.h"
27 #include "iommu_common.h"
28 #include "kernel.h"
29
30 #include "pci_sun4v.h"
31
32 #define DRIVER_NAME "pci_sun4v"
33 #define PFX DRIVER_NAME ": "
34
35 static unsigned long vpci_major;
36 static unsigned long vpci_minor;
37
38 struct vpci_version {
39 unsigned long major;
40 unsigned long minor;
41 };
42
43 /* Ordered from largest major to lowest */
44 static struct vpci_version vpci_versions[] = {
45 { .major = 2, .minor = 0 },
46 { .major = 1, .minor = 1 },
47 };
48
49 static unsigned long vatu_major = 1;
50 static unsigned long vatu_minor = 1;
51
52 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
53
54 struct iommu_batch {
55 struct device *dev; /* Device mapping is for. */
56 unsigned long prot; /* IOMMU page protections */
57 unsigned long entry; /* Index into IOTSB. */
58 u64 *pglist; /* List of physical pages */
59 unsigned long npages; /* Number of pages in list. */
60 };
61
62 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
63 static int iommu_batch_initialized;
64
65 /* Interrupts must be disabled. */
66 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
67 {
68 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
69
70 p->dev = dev;
71 p->prot = prot;
72 p->entry = entry;
73 p->npages = 0;
74 }
75
76 /* Interrupts must be disabled. */
77 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
78 {
79 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
80 u64 *pglist = p->pglist;
81 u64 index_count;
82 unsigned long devhandle = pbm->devhandle;
83 unsigned long prot = p->prot;
84 unsigned long entry = p->entry;
85 unsigned long npages = p->npages;
86 unsigned long iotsb_num;
87 unsigned long ret;
88 long num;
89
90 /* VPCI maj=1, min=[0,1] only supports read and write */
91 if (vpci_major < 2)
92 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
93
94 while (npages != 0) {
95 if (mask <= DMA_BIT_MASK(32) || !pbm->iommu->atu) {
96 num = pci_sun4v_iommu_map(devhandle,
97 HV_PCI_TSBID(0, entry),
98 npages,
99 prot,
100 __pa(pglist));
101 if (unlikely(num < 0)) {
102 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
103 __func__,
104 devhandle,
105 HV_PCI_TSBID(0, entry),
106 npages, prot, __pa(pglist),
107 num);
108 return -1;
109 }
110 } else {
111 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
112 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
113 ret = pci_sun4v_iotsb_map(devhandle,
114 iotsb_num,
115 index_count,
116 prot,
117 __pa(pglist),
118 &num);
119 if (unlikely(ret != HV_EOK)) {
120 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
121 __func__,
122 devhandle, iotsb_num,
123 index_count, prot,
124 __pa(pglist), ret);
125 return -1;
126 }
127 }
128 entry += num;
129 npages -= num;
130 pglist += num;
131 }
132
133 p->entry = entry;
134 p->npages = 0;
135
136 return 0;
137 }
138
139 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
140 {
141 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
142
143 if (p->entry + p->npages == entry)
144 return;
145 if (p->entry != ~0UL)
146 iommu_batch_flush(p, mask);
147 p->entry = entry;
148 }
149
150 /* Interrupts must be disabled. */
151 static inline long iommu_batch_add(u64 phys_page, u64 mask)
152 {
153 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
154
155 BUG_ON(p->npages >= PGLIST_NENTS);
156
157 p->pglist[p->npages++] = phys_page;
158 if (p->npages == PGLIST_NENTS)
159 return iommu_batch_flush(p, mask);
160
161 return 0;
162 }
163
164 /* Interrupts must be disabled. */
165 static inline long iommu_batch_end(u64 mask)
166 {
167 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
168
169 BUG_ON(p->npages >= PGLIST_NENTS);
170
171 return iommu_batch_flush(p, mask);
172 }
173
174 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
175 dma_addr_t *dma_addrp, gfp_t gfp,
176 unsigned long attrs)
177 {
178 u64 mask;
179 unsigned long flags, order, first_page, npages, n;
180 unsigned long prot = 0;
181 struct iommu *iommu;
182 struct atu *atu;
183 struct iommu_map_table *tbl;
184 struct page *page;
185 void *ret;
186 long entry;
187 int nid;
188
189 size = IO_PAGE_ALIGN(size);
190 order = get_order(size);
191 if (unlikely(order >= MAX_ORDER))
192 return NULL;
193
194 npages = size >> IO_PAGE_SHIFT;
195
196 if (attrs & DMA_ATTR_WEAK_ORDERING)
197 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
198
199 nid = dev->archdata.numa_node;
200 page = alloc_pages_node(nid, gfp, order);
201 if (unlikely(!page))
202 return NULL;
203
204 first_page = (unsigned long) page_address(page);
205 memset((char *)first_page, 0, PAGE_SIZE << order);
206
207 iommu = dev->archdata.iommu;
208 atu = iommu->atu;
209
210 mask = dev->coherent_dma_mask;
211 if (mask <= DMA_BIT_MASK(32) || !atu)
212 tbl = &iommu->tbl;
213 else
214 tbl = &atu->tbl;
215
216 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
217 (unsigned long)(-1), 0);
218
219 if (unlikely(entry == IOMMU_ERROR_CODE))
220 goto range_alloc_fail;
221
222 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
223 ret = (void *) first_page;
224 first_page = __pa(first_page);
225
226 local_irq_save(flags);
227
228 iommu_batch_start(dev,
229 (HV_PCI_MAP_ATTR_READ | prot |
230 HV_PCI_MAP_ATTR_WRITE),
231 entry);
232
233 for (n = 0; n < npages; n++) {
234 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
235 if (unlikely(err < 0L))
236 goto iommu_map_fail;
237 }
238
239 if (unlikely(iommu_batch_end(mask) < 0L))
240 goto iommu_map_fail;
241
242 local_irq_restore(flags);
243
244 return ret;
245
246 iommu_map_fail:
247 local_irq_restore(flags);
248 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
249
250 range_alloc_fail:
251 free_pages(first_page, order);
252 return NULL;
253 }
254
255 unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
256 unsigned long iotsb_num,
257 struct pci_bus *bus_dev)
258 {
259 struct pci_dev *pdev;
260 unsigned long err;
261 unsigned int bus;
262 unsigned int device;
263 unsigned int fun;
264
265 list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
266 if (pdev->subordinate) {
267 /* No need to bind pci bridge */
268 dma_4v_iotsb_bind(devhandle, iotsb_num,
269 pdev->subordinate);
270 } else {
271 bus = bus_dev->number;
272 device = PCI_SLOT(pdev->devfn);
273 fun = PCI_FUNC(pdev->devfn);
274 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
275 HV_PCI_DEVICE_BUILD(bus,
276 device,
277 fun));
278
279 /* If bind fails for one device it is going to fail
280 * for rest of the devices because we are sharing
281 * IOTSB. So in case of failure simply return with
282 * error.
283 */
284 if (err)
285 return err;
286 }
287 }
288
289 return 0;
290 }
291
292 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
293 dma_addr_t dvma, unsigned long iotsb_num,
294 unsigned long entry, unsigned long npages)
295 {
296 unsigned long num, flags;
297 unsigned long ret;
298
299 local_irq_save(flags);
300 do {
301 if (dvma <= DMA_BIT_MASK(32)) {
302 num = pci_sun4v_iommu_demap(devhandle,
303 HV_PCI_TSBID(0, entry),
304 npages);
305 } else {
306 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
307 entry, npages, &num);
308 if (unlikely(ret != HV_EOK)) {
309 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
310 ret);
311 }
312 }
313 entry += num;
314 npages -= num;
315 } while (npages != 0);
316 local_irq_restore(flags);
317 }
318
319 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
320 dma_addr_t dvma, unsigned long attrs)
321 {
322 struct pci_pbm_info *pbm;
323 struct iommu *iommu;
324 struct atu *atu;
325 struct iommu_map_table *tbl;
326 unsigned long order, npages, entry;
327 unsigned long iotsb_num;
328 u32 devhandle;
329
330 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
331 iommu = dev->archdata.iommu;
332 pbm = dev->archdata.host_controller;
333 atu = iommu->atu;
334 devhandle = pbm->devhandle;
335
336 if (dvma <= DMA_BIT_MASK(32)) {
337 tbl = &iommu->tbl;
338 iotsb_num = 0; /* we don't care for legacy iommu */
339 } else {
340 tbl = &atu->tbl;
341 iotsb_num = atu->iotsb->iotsb_num;
342 }
343 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
344 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
345 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
346 order = get_order(size);
347 if (order < 10)
348 free_pages((unsigned long)cpu, order);
349 }
350
351 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
352 unsigned long offset, size_t sz,
353 enum dma_data_direction direction,
354 unsigned long attrs)
355 {
356 struct iommu *iommu;
357 struct atu *atu;
358 struct iommu_map_table *tbl;
359 u64 mask;
360 unsigned long flags, npages, oaddr;
361 unsigned long i, base_paddr;
362 unsigned long prot;
363 dma_addr_t bus_addr, ret;
364 long entry;
365
366 iommu = dev->archdata.iommu;
367 atu = iommu->atu;
368
369 if (unlikely(direction == DMA_NONE))
370 goto bad;
371
372 oaddr = (unsigned long)(page_address(page) + offset);
373 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
374 npages >>= IO_PAGE_SHIFT;
375
376 mask = *dev->dma_mask;
377 if (mask <= DMA_BIT_MASK(32))
378 tbl = &iommu->tbl;
379 else
380 tbl = &atu->tbl;
381
382 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
383 (unsigned long)(-1), 0);
384
385 if (unlikely(entry == IOMMU_ERROR_CODE))
386 goto bad;
387
388 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
389 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
390 base_paddr = __pa(oaddr & IO_PAGE_MASK);
391 prot = HV_PCI_MAP_ATTR_READ;
392 if (direction != DMA_TO_DEVICE)
393 prot |= HV_PCI_MAP_ATTR_WRITE;
394
395 if (attrs & DMA_ATTR_WEAK_ORDERING)
396 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
397
398 local_irq_save(flags);
399
400 iommu_batch_start(dev, prot, entry);
401
402 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
403 long err = iommu_batch_add(base_paddr, mask);
404 if (unlikely(err < 0L))
405 goto iommu_map_fail;
406 }
407 if (unlikely(iommu_batch_end(mask) < 0L))
408 goto iommu_map_fail;
409
410 local_irq_restore(flags);
411
412 return ret;
413
414 bad:
415 if (printk_ratelimit())
416 WARN_ON(1);
417 return DMA_MAPPING_ERROR;
418
419 iommu_map_fail:
420 local_irq_restore(flags);
421 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
422 return DMA_MAPPING_ERROR;
423 }
424
425 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
426 size_t sz, enum dma_data_direction direction,
427 unsigned long attrs)
428 {
429 struct pci_pbm_info *pbm;
430 struct iommu *iommu;
431 struct atu *atu;
432 struct iommu_map_table *tbl;
433 unsigned long npages;
434 unsigned long iotsb_num;
435 long entry;
436 u32 devhandle;
437
438 if (unlikely(direction == DMA_NONE)) {
439 if (printk_ratelimit())
440 WARN_ON(1);
441 return;
442 }
443
444 iommu = dev->archdata.iommu;
445 pbm = dev->archdata.host_controller;
446 atu = iommu->atu;
447 devhandle = pbm->devhandle;
448
449 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
450 npages >>= IO_PAGE_SHIFT;
451 bus_addr &= IO_PAGE_MASK;
452
453 if (bus_addr <= DMA_BIT_MASK(32)) {
454 iotsb_num = 0; /* we don't care for legacy iommu */
455 tbl = &iommu->tbl;
456 } else {
457 iotsb_num = atu->iotsb->iotsb_num;
458 tbl = &atu->tbl;
459 }
460 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
461 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
462 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
463 }
464
465 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
466 int nelems, enum dma_data_direction direction,
467 unsigned long attrs)
468 {
469 struct scatterlist *s, *outs, *segstart;
470 unsigned long flags, handle, prot;
471 dma_addr_t dma_next = 0, dma_addr;
472 unsigned int max_seg_size;
473 unsigned long seg_boundary_size;
474 int outcount, incount, i;
475 struct iommu *iommu;
476 struct atu *atu;
477 struct iommu_map_table *tbl;
478 u64 mask;
479 unsigned long base_shift;
480 long err;
481
482 BUG_ON(direction == DMA_NONE);
483
484 iommu = dev->archdata.iommu;
485 if (nelems == 0 || !iommu)
486 return 0;
487 atu = iommu->atu;
488
489 prot = HV_PCI_MAP_ATTR_READ;
490 if (direction != DMA_TO_DEVICE)
491 prot |= HV_PCI_MAP_ATTR_WRITE;
492
493 if (attrs & DMA_ATTR_WEAK_ORDERING)
494 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
495
496 outs = s = segstart = &sglist[0];
497 outcount = 1;
498 incount = nelems;
499 handle = 0;
500
501 /* Init first segment length for backout at failure */
502 outs->dma_length = 0;
503
504 local_irq_save(flags);
505
506 iommu_batch_start(dev, prot, ~0UL);
507
508 max_seg_size = dma_get_max_seg_size(dev);
509 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
510 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
511
512 mask = *dev->dma_mask;
513 if (mask <= DMA_BIT_MASK(32))
514 tbl = &iommu->tbl;
515 else
516 tbl = &atu->tbl;
517
518 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
519
520 for_each_sg(sglist, s, nelems, i) {
521 unsigned long paddr, npages, entry, out_entry = 0, slen;
522
523 slen = s->length;
524 /* Sanity check */
525 if (slen == 0) {
526 dma_next = 0;
527 continue;
528 }
529 /* Allocate iommu entries for that segment */
530 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
531 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
532 entry = iommu_tbl_range_alloc(dev, tbl, npages,
533 &handle, (unsigned long)(-1), 0);
534
535 /* Handle failure */
536 if (unlikely(entry == IOMMU_ERROR_CODE)) {
537 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
538 tbl, paddr, npages);
539 goto iommu_map_failed;
540 }
541
542 iommu_batch_new_entry(entry, mask);
543
544 /* Convert entry to a dma_addr_t */
545 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
546 dma_addr |= (s->offset & ~IO_PAGE_MASK);
547
548 /* Insert into HW table */
549 paddr &= IO_PAGE_MASK;
550 while (npages--) {
551 err = iommu_batch_add(paddr, mask);
552 if (unlikely(err < 0L))
553 goto iommu_map_failed;
554 paddr += IO_PAGE_SIZE;
555 }
556
557 /* If we are in an open segment, try merging */
558 if (segstart != s) {
559 /* We cannot merge if:
560 * - allocated dma_addr isn't contiguous to previous allocation
561 */
562 if ((dma_addr != dma_next) ||
563 (outs->dma_length + s->length > max_seg_size) ||
564 (is_span_boundary(out_entry, base_shift,
565 seg_boundary_size, outs, s))) {
566 /* Can't merge: create a new segment */
567 segstart = s;
568 outcount++;
569 outs = sg_next(outs);
570 } else {
571 outs->dma_length += s->length;
572 }
573 }
574
575 if (segstart == s) {
576 /* This is a new segment, fill entries */
577 outs->dma_address = dma_addr;
578 outs->dma_length = slen;
579 out_entry = entry;
580 }
581
582 /* Calculate next page pointer for contiguous check */
583 dma_next = dma_addr + slen;
584 }
585
586 err = iommu_batch_end(mask);
587
588 if (unlikely(err < 0L))
589 goto iommu_map_failed;
590
591 local_irq_restore(flags);
592
593 if (outcount < incount) {
594 outs = sg_next(outs);
595 outs->dma_address = DMA_MAPPING_ERROR;
596 outs->dma_length = 0;
597 }
598
599 return outcount;
600
601 iommu_map_failed:
602 for_each_sg(sglist, s, nelems, i) {
603 if (s->dma_length != 0) {
604 unsigned long vaddr, npages;
605
606 vaddr = s->dma_address & IO_PAGE_MASK;
607 npages = iommu_num_pages(s->dma_address, s->dma_length,
608 IO_PAGE_SIZE);
609 iommu_tbl_range_free(tbl, vaddr, npages,
610 IOMMU_ERROR_CODE);
611 /* XXX demap? XXX */
612 s->dma_address = DMA_MAPPING_ERROR;
613 s->dma_length = 0;
614 }
615 if (s == outs)
616 break;
617 }
618 local_irq_restore(flags);
619
620 return 0;
621 }
622
623 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
624 int nelems, enum dma_data_direction direction,
625 unsigned long attrs)
626 {
627 struct pci_pbm_info *pbm;
628 struct scatterlist *sg;
629 struct iommu *iommu;
630 struct atu *atu;
631 unsigned long flags, entry;
632 unsigned long iotsb_num;
633 u32 devhandle;
634
635 BUG_ON(direction == DMA_NONE);
636
637 iommu = dev->archdata.iommu;
638 pbm = dev->archdata.host_controller;
639 atu = iommu->atu;
640 devhandle = pbm->devhandle;
641
642 local_irq_save(flags);
643
644 sg = sglist;
645 while (nelems--) {
646 dma_addr_t dma_handle = sg->dma_address;
647 unsigned int len = sg->dma_length;
648 unsigned long npages;
649 struct iommu_map_table *tbl;
650 unsigned long shift = IO_PAGE_SHIFT;
651
652 if (!len)
653 break;
654 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
655
656 if (dma_handle <= DMA_BIT_MASK(32)) {
657 iotsb_num = 0; /* we don't care for legacy iommu */
658 tbl = &iommu->tbl;
659 } else {
660 iotsb_num = atu->iotsb->iotsb_num;
661 tbl = &atu->tbl;
662 }
663 entry = ((dma_handle - tbl->table_map_base) >> shift);
664 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
665 entry, npages);
666 iommu_tbl_range_free(tbl, dma_handle, npages,
667 IOMMU_ERROR_CODE);
668 sg = sg_next(sg);
669 }
670
671 local_irq_restore(flags);
672 }
673
674 static int dma_4v_supported(struct device *dev, u64 device_mask)
675 {
676 struct iommu *iommu = dev->archdata.iommu;
677
678 if (ali_sound_dma_hack(dev, device_mask))
679 return 1;
680 if (device_mask < iommu->dma_addr_mask)
681 return 0;
682 return 1;
683 }
684
685 static const struct dma_map_ops sun4v_dma_ops = {
686 .alloc = dma_4v_alloc_coherent,
687 .free = dma_4v_free_coherent,
688 .map_page = dma_4v_map_page,
689 .unmap_page = dma_4v_unmap_page,
690 .map_sg = dma_4v_map_sg,
691 .unmap_sg = dma_4v_unmap_sg,
692 .dma_supported = dma_4v_supported,
693 };
694
695 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
696 {
697 struct property *prop;
698 struct device_node *dp;
699
700 dp = pbm->op->dev.of_node;
701 prop = of_find_property(dp, "66mhz-capable", NULL);
702 pbm->is_66mhz_capable = (prop != NULL);
703 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
704
705 /* XXX register error interrupt handlers XXX */
706 }
707
708 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
709 struct iommu_map_table *iommu)
710 {
711 struct iommu_pool *pool;
712 unsigned long i, pool_nr, cnt = 0;
713 u32 devhandle;
714
715 devhandle = pbm->devhandle;
716 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
717 pool = &(iommu->pools[pool_nr]);
718 for (i = pool->start; i <= pool->end; i++) {
719 unsigned long ret, io_attrs, ra;
720
721 ret = pci_sun4v_iommu_getmap(devhandle,
722 HV_PCI_TSBID(0, i),
723 &io_attrs, &ra);
724 if (ret == HV_EOK) {
725 if (page_in_phys_avail(ra)) {
726 pci_sun4v_iommu_demap(devhandle,
727 HV_PCI_TSBID(0,
728 i), 1);
729 } else {
730 cnt++;
731 __set_bit(i, iommu->map);
732 }
733 }
734 }
735 }
736 return cnt;
737 }
738
739 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
740 {
741 struct atu *atu = pbm->iommu->atu;
742 struct atu_iotsb *iotsb;
743 void *table;
744 u64 table_size;
745 u64 iotsb_num;
746 unsigned long order;
747 unsigned long err;
748
749 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
750 if (!iotsb) {
751 err = -ENOMEM;
752 goto out_err;
753 }
754 atu->iotsb = iotsb;
755
756 /* calculate size of IOTSB */
757 table_size = (atu->size / IO_PAGE_SIZE) * 8;
758 order = get_order(table_size);
759 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
760 if (!table) {
761 err = -ENOMEM;
762 goto table_failed;
763 }
764 iotsb->table = table;
765 iotsb->ra = __pa(table);
766 iotsb->dvma_size = atu->size;
767 iotsb->dvma_base = atu->base;
768 iotsb->table_size = table_size;
769 iotsb->page_size = IO_PAGE_SIZE;
770
771 /* configure and register IOTSB with HV */
772 err = pci_sun4v_iotsb_conf(pbm->devhandle,
773 iotsb->ra,
774 iotsb->table_size,
775 iotsb->page_size,
776 iotsb->dvma_base,
777 &iotsb_num);
778 if (err) {
779 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
780 goto iotsb_conf_failed;
781 }
782 iotsb->iotsb_num = iotsb_num;
783
784 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
785 if (err) {
786 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
787 goto iotsb_conf_failed;
788 }
789
790 return 0;
791
792 iotsb_conf_failed:
793 free_pages((unsigned long)table, order);
794 table_failed:
795 kfree(iotsb);
796 out_err:
797 return err;
798 }
799
800 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
801 {
802 struct atu *atu = pbm->iommu->atu;
803 unsigned long err;
804 const u64 *ranges;
805 u64 map_size, num_iotte;
806 u64 dma_mask;
807 const u32 *page_size;
808 int len;
809
810 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
811 &len);
812 if (!ranges) {
813 pr_err(PFX "No iommu-address-ranges\n");
814 return -EINVAL;
815 }
816
817 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
818 NULL);
819 if (!page_size) {
820 pr_err(PFX "No iommu-pagesizes\n");
821 return -EINVAL;
822 }
823
824 /* There are 4 iommu-address-ranges supported. Each range is pair of
825 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
826 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
827 * address ranges to support 64bit addressing. Because 'size' for
828 * address ranges[2] and ranges[3] are same we can select either of
829 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
830 * large for OS to allocate IOTSB we are using fix size 32G
831 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
832 * to share.
833 */
834 atu->ranges = (struct atu_ranges *)ranges;
835 atu->base = atu->ranges[3].base;
836 atu->size = ATU_64_SPACE_SIZE;
837
838 /* Create IOTSB */
839 err = pci_sun4v_atu_alloc_iotsb(pbm);
840 if (err) {
841 pr_err(PFX "Error creating ATU IOTSB\n");
842 return err;
843 }
844
845 /* Create ATU iommu map.
846 * One bit represents one iotte in IOTSB table.
847 */
848 dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
849 num_iotte = atu->size / IO_PAGE_SIZE;
850 map_size = num_iotte / 8;
851 atu->tbl.table_map_base = atu->base;
852 atu->dma_addr_mask = dma_mask;
853 atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
854 if (!atu->tbl.map)
855 return -ENOMEM;
856
857 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
858 NULL, false /* no large_pool */,
859 0 /* default npools */,
860 false /* want span boundary checking */);
861
862 return 0;
863 }
864
865 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
866 {
867 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
868 struct iommu *iommu = pbm->iommu;
869 unsigned long num_tsb_entries, sz;
870 u32 dma_mask, dma_offset;
871 const u32 *vdma;
872
873 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
874 if (!vdma)
875 vdma = vdma_default;
876
877 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
878 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
879 vdma[0], vdma[1]);
880 return -EINVAL;
881 }
882
883 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
884 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
885
886 dma_offset = vdma[0];
887
888 /* Setup initial software IOMMU state. */
889 spin_lock_init(&iommu->lock);
890 iommu->ctx_lowest_free = 1;
891 iommu->tbl.table_map_base = dma_offset;
892 iommu->dma_addr_mask = dma_mask;
893
894 /* Allocate and initialize the free area map. */
895 sz = (num_tsb_entries + 7) / 8;
896 sz = (sz + 7UL) & ~7UL;
897 iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
898 if (!iommu->tbl.map) {
899 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
900 return -ENOMEM;
901 }
902 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
903 NULL, false /* no large_pool */,
904 0 /* default npools */,
905 false /* want span boundary checking */);
906 sz = probe_existing_entries(pbm, &iommu->tbl);
907 if (sz)
908 printk("%s: Imported %lu TSB entries from OBP\n",
909 pbm->name, sz);
910
911 return 0;
912 }
913
914 #ifdef CONFIG_PCI_MSI
915 struct pci_sun4v_msiq_entry {
916 u64 version_type;
917 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
918 #define MSIQ_VERSION_SHIFT 32
919 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
920 #define MSIQ_TYPE_SHIFT 0
921 #define MSIQ_TYPE_NONE 0x00
922 #define MSIQ_TYPE_MSG 0x01
923 #define MSIQ_TYPE_MSI32 0x02
924 #define MSIQ_TYPE_MSI64 0x03
925 #define MSIQ_TYPE_INTX 0x08
926 #define MSIQ_TYPE_NONE2 0xff
927
928 u64 intx_sysino;
929 u64 reserved1;
930 u64 stick;
931 u64 req_id; /* bus/device/func */
932 #define MSIQ_REQID_BUS_MASK 0xff00UL
933 #define MSIQ_REQID_BUS_SHIFT 8
934 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
935 #define MSIQ_REQID_DEVICE_SHIFT 3
936 #define MSIQ_REQID_FUNC_MASK 0x0007UL
937 #define MSIQ_REQID_FUNC_SHIFT 0
938
939 u64 msi_address;
940
941 /* The format of this value is message type dependent.
942 * For MSI bits 15:0 are the data from the MSI packet.
943 * For MSI-X bits 31:0 are the data from the MSI packet.
944 * For MSG, the message code and message routing code where:
945 * bits 39:32 is the bus/device/fn of the msg target-id
946 * bits 18:16 is the message routing code
947 * bits 7:0 is the message code
948 * For INTx the low order 2-bits are:
949 * 00 - INTA
950 * 01 - INTB
951 * 10 - INTC
952 * 11 - INTD
953 */
954 u64 msi_data;
955
956 u64 reserved2;
957 };
958
959 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
960 unsigned long *head)
961 {
962 unsigned long err, limit;
963
964 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
965 if (unlikely(err))
966 return -ENXIO;
967
968 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
969 if (unlikely(*head >= limit))
970 return -EFBIG;
971
972 return 0;
973 }
974
975 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
976 unsigned long msiqid, unsigned long *head,
977 unsigned long *msi)
978 {
979 struct pci_sun4v_msiq_entry *ep;
980 unsigned long err, type;
981
982 /* Note: void pointer arithmetic, 'head' is a byte offset */
983 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
984 (pbm->msiq_ent_count *
985 sizeof(struct pci_sun4v_msiq_entry))) +
986 *head);
987
988 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
989 return 0;
990
991 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
992 if (unlikely(type != MSIQ_TYPE_MSI32 &&
993 type != MSIQ_TYPE_MSI64))
994 return -EINVAL;
995
996 *msi = ep->msi_data;
997
998 err = pci_sun4v_msi_setstate(pbm->devhandle,
999 ep->msi_data /* msi_num */,
1000 HV_MSISTATE_IDLE);
1001 if (unlikely(err))
1002 return -ENXIO;
1003
1004 /* Clear the entry. */
1005 ep->version_type &= ~MSIQ_TYPE_MASK;
1006
1007 (*head) += sizeof(struct pci_sun4v_msiq_entry);
1008 if (*head >=
1009 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1010 *head = 0;
1011
1012 return 1;
1013 }
1014
1015 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1016 unsigned long head)
1017 {
1018 unsigned long err;
1019
1020 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1021 if (unlikely(err))
1022 return -EINVAL;
1023
1024 return 0;
1025 }
1026
1027 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1028 unsigned long msi, int is_msi64)
1029 {
1030 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1031 (is_msi64 ?
1032 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1033 return -ENXIO;
1034 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1035 return -ENXIO;
1036 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1037 return -ENXIO;
1038 return 0;
1039 }
1040
1041 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1042 {
1043 unsigned long err, msiqid;
1044
1045 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1046 if (err)
1047 return -ENXIO;
1048
1049 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1050
1051 return 0;
1052 }
1053
1054 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1055 {
1056 unsigned long q_size, alloc_size, pages, order;
1057 int i;
1058
1059 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1060 alloc_size = (pbm->msiq_num * q_size);
1061 order = get_order(alloc_size);
1062 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1063 if (pages == 0UL) {
1064 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1065 order);
1066 return -ENOMEM;
1067 }
1068 memset((char *)pages, 0, PAGE_SIZE << order);
1069 pbm->msi_queues = (void *) pages;
1070
1071 for (i = 0; i < pbm->msiq_num; i++) {
1072 unsigned long err, base = __pa(pages + (i * q_size));
1073 unsigned long ret1, ret2;
1074
1075 err = pci_sun4v_msiq_conf(pbm->devhandle,
1076 pbm->msiq_first + i,
1077 base, pbm->msiq_ent_count);
1078 if (err) {
1079 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1080 err);
1081 goto h_error;
1082 }
1083
1084 err = pci_sun4v_msiq_info(pbm->devhandle,
1085 pbm->msiq_first + i,
1086 &ret1, &ret2);
1087 if (err) {
1088 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1089 err);
1090 goto h_error;
1091 }
1092 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1093 printk(KERN_ERR "MSI: Bogus qconf "
1094 "expected[%lx:%x] got[%lx:%lx]\n",
1095 base, pbm->msiq_ent_count,
1096 ret1, ret2);
1097 goto h_error;
1098 }
1099 }
1100
1101 return 0;
1102
1103 h_error:
1104 free_pages(pages, order);
1105 return -EINVAL;
1106 }
1107
1108 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1109 {
1110 unsigned long q_size, alloc_size, pages, order;
1111 int i;
1112
1113 for (i = 0; i < pbm->msiq_num; i++) {
1114 unsigned long msiqid = pbm->msiq_first + i;
1115
1116 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1117 }
1118
1119 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1120 alloc_size = (pbm->msiq_num * q_size);
1121 order = get_order(alloc_size);
1122
1123 pages = (unsigned long) pbm->msi_queues;
1124
1125 free_pages(pages, order);
1126
1127 pbm->msi_queues = NULL;
1128 }
1129
1130 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1131 unsigned long msiqid,
1132 unsigned long devino)
1133 {
1134 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1135
1136 if (!irq)
1137 return -ENOMEM;
1138
1139 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1140 return -EINVAL;
1141 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1142 return -EINVAL;
1143
1144 return irq;
1145 }
1146
1147 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1148 .get_head = pci_sun4v_get_head,
1149 .dequeue_msi = pci_sun4v_dequeue_msi,
1150 .set_head = pci_sun4v_set_head,
1151 .msi_setup = pci_sun4v_msi_setup,
1152 .msi_teardown = pci_sun4v_msi_teardown,
1153 .msiq_alloc = pci_sun4v_msiq_alloc,
1154 .msiq_free = pci_sun4v_msiq_free,
1155 .msiq_build_irq = pci_sun4v_msiq_build_irq,
1156 };
1157
1158 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1159 {
1160 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1161 }
1162 #else /* CONFIG_PCI_MSI */
1163 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1164 {
1165 }
1166 #endif /* !(CONFIG_PCI_MSI) */
1167
1168 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1169 struct platform_device *op, u32 devhandle)
1170 {
1171 struct device_node *dp = op->dev.of_node;
1172 int err;
1173
1174 pbm->numa_node = of_node_to_nid(dp);
1175
1176 pbm->pci_ops = &sun4v_pci_ops;
1177 pbm->config_space_reg_bits = 12;
1178
1179 pbm->index = pci_num_pbms++;
1180
1181 pbm->op = op;
1182
1183 pbm->devhandle = devhandle;
1184
1185 pbm->name = dp->full_name;
1186
1187 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1188 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1189
1190 pci_determine_mem_io_space(pbm);
1191
1192 pci_get_pbm_props(pbm);
1193
1194 err = pci_sun4v_iommu_init(pbm);
1195 if (err)
1196 return err;
1197
1198 pci_sun4v_msi_init(pbm);
1199
1200 pci_sun4v_scan_bus(pbm, &op->dev);
1201
1202 /* if atu_init fails its not complete failure.
1203 * we can still continue using legacy iommu.
1204 */
1205 if (pbm->iommu->atu) {
1206 err = pci_sun4v_atu_init(pbm);
1207 if (err) {
1208 kfree(pbm->iommu->atu);
1209 pbm->iommu->atu = NULL;
1210 pr_err(PFX "ATU init failed, err=%d\n", err);
1211 }
1212 }
1213
1214 pbm->next = pci_pbm_root;
1215 pci_pbm_root = pbm;
1216
1217 return 0;
1218 }
1219
1220 static int pci_sun4v_probe(struct platform_device *op)
1221 {
1222 const struct linux_prom64_registers *regs;
1223 static int hvapi_negotiated = 0;
1224 struct pci_pbm_info *pbm;
1225 struct device_node *dp;
1226 struct iommu *iommu;
1227 struct atu *atu;
1228 u32 devhandle;
1229 int i, err = -ENODEV;
1230 static bool hv_atu = true;
1231
1232 dp = op->dev.of_node;
1233
1234 if (!hvapi_negotiated++) {
1235 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1236 vpci_major = vpci_versions[i].major;
1237 vpci_minor = vpci_versions[i].minor;
1238
1239 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1240 &vpci_minor);
1241 if (!err)
1242 break;
1243 }
1244
1245 if (err) {
1246 pr_err(PFX "Could not register hvapi, err=%d\n", err);
1247 return err;
1248 }
1249 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1250 vpci_major, vpci_minor);
1251
1252 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1253 if (err) {
1254 /* don't return an error if we fail to register the
1255 * ATU group, but ATU hcalls won't be available.
1256 */
1257 hv_atu = false;
1258 } else {
1259 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1260 vatu_major, vatu_minor);
1261 }
1262
1263 dma_ops = &sun4v_dma_ops;
1264 }
1265
1266 regs = of_get_property(dp, "reg", NULL);
1267 err = -ENODEV;
1268 if (!regs) {
1269 printk(KERN_ERR PFX "Could not find config registers\n");
1270 goto out_err;
1271 }
1272 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1273
1274 err = -ENOMEM;
1275 if (!iommu_batch_initialized) {
1276 for_each_possible_cpu(i) {
1277 unsigned long page = get_zeroed_page(GFP_KERNEL);
1278
1279 if (!page)
1280 goto out_err;
1281
1282 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1283 }
1284 iommu_batch_initialized = 1;
1285 }
1286
1287 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1288 if (!pbm) {
1289 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1290 goto out_err;
1291 }
1292
1293 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1294 if (!iommu) {
1295 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1296 goto out_free_controller;
1297 }
1298
1299 pbm->iommu = iommu;
1300 iommu->atu = NULL;
1301 if (hv_atu) {
1302 atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1303 if (!atu)
1304 pr_err(PFX "Could not allocate atu\n");
1305 else
1306 iommu->atu = atu;
1307 }
1308
1309 err = pci_sun4v_pbm_init(pbm, op, devhandle);
1310 if (err)
1311 goto out_free_iommu;
1312
1313 dev_set_drvdata(&op->dev, pbm);
1314
1315 return 0;
1316
1317 out_free_iommu:
1318 kfree(iommu->atu);
1319 kfree(pbm->iommu);
1320
1321 out_free_controller:
1322 kfree(pbm);
1323
1324 out_err:
1325 return err;
1326 }
1327
1328 static const struct of_device_id pci_sun4v_match[] = {
1329 {
1330 .name = "pci",
1331 .compatible = "SUNW,sun4v-pci",
1332 },
1333 {},
1334 };
1335
1336 static struct platform_driver pci_sun4v_driver = {
1337 .driver = {
1338 .name = DRIVER_NAME,
1339 .of_match_table = pci_sun4v_match,
1340 },
1341 .probe = pci_sun4v_probe,
1342 };
1343
1344 static int __init pci_sun4v_init(void)
1345 {
1346 return platform_driver_register(&pci_sun4v_driver);
1347 }
1348
1349 subsys_initcall(pci_sun4v_init);
Linux with added FPC-III support