?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
mtd: nand: omap: Fix comment in platform data using wrong Kconfig symbol
[linux/fpc-iii.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
blob1e225528f0d7f4a1226dec1bdfba0920fa7da4d3
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
29 #include <linux/memory.h>
30 #include <linux/numa.h>
31
32 #include <asm/uv/uv_mmrs.h>
33 #include <asm/uv/uv_hub.h>
34 #include <asm/current.h>
35 #include <asm/pgtable.h>
36 #include <asm/uv/bios.h>
37 #include <asm/uv/uv.h>
38 #include <asm/apic.h>
39 #include <asm/e820/api.h>
40 #include <asm/ipi.h>
41 #include <asm/smp.h>
42 #include <asm/x86_init.h>
43 #include <asm/nmi.h>
44
45 DEFINE_PER_CPU(int, x2apic_extra_bits);
46
47 static enum uv_system_type uv_system_type;
48 static bool uv_hubless_system;
49 static u64 gru_start_paddr, gru_end_paddr;
50 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
51 static u64 gru_dist_lmask, gru_dist_umask;
52 static union uvh_apicid uvh_apicid;
53
54 /* Information derived from CPUID: */
55 static struct {
56 unsigned int apicid_shift;
57 unsigned int apicid_mask;
58 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
59 unsigned int pnode_mask;
60 unsigned int gpa_shift;
61 unsigned int gnode_shift;
62 } uv_cpuid;
63
64 int uv_min_hub_revision_id;
65 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
66
67 unsigned int uv_apicid_hibits;
68 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
69
70 static struct apic apic_x2apic_uv_x;
71 static struct uv_hub_info_s uv_hub_info_node0;
72
73 /* Set this to use hardware error handler instead of kernel panic: */
74 static int disable_uv_undefined_panic = 1;
75
76 unsigned long uv_undefined(char *str)
77 {
78 if (likely(!disable_uv_undefined_panic))
79 panic("UV: error: undefined MMR: %s\n", str);
80 else
81 pr_crit("UV: error: undefined MMR: %s\n", str);
82
83 /* Cause a machine fault: */
84 return ~0ul;
85 }
86 EXPORT_SYMBOL(uv_undefined);
87
88 static unsigned long __init uv_early_read_mmr(unsigned long addr)
89 {
90 unsigned long val, *mmr;
91
92 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
93 val = *mmr;
94 early_iounmap(mmr, sizeof(*mmr));
95
96 return val;
97 }
98
99 static inline bool is_GRU_range(u64 start, u64 end)
100 {
101 if (gru_dist_base) {
102 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */
103 u64 sl = start & gru_dist_lmask; /* Base offset bits */
104 u64 eu = end & gru_dist_umask;
105 u64 el = end & gru_dist_lmask;
106
107 /* Must reside completely within a single GRU range: */
108 return (sl == gru_dist_base && el == gru_dist_base &&
109 su >= gru_first_node_paddr &&
110 su <= gru_last_node_paddr &&
111 eu == su);
112 } else {
113 return start >= gru_start_paddr && end <= gru_end_paddr;
114 }
115 }
116
117 static bool uv_is_untracked_pat_range(u64 start, u64 end)
118 {
119 return is_ISA_range(start, end) || is_GRU_range(start, end);
120 }
121
122 static int __init early_get_pnodeid(void)
123 {
124 union uvh_node_id_u node_id;
125 union uvh_rh_gam_config_mmr_u m_n_config;
126 int pnode;
127
128 /* Currently, all blades have same revision number */
129 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
130 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
131 uv_min_hub_revision_id = node_id.s.revision;
132
133 switch (node_id.s.part_number) {
134 case UV2_HUB_PART_NUMBER:
135 case UV2_HUB_PART_NUMBER_X:
136 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
137 break;
138 case UV3_HUB_PART_NUMBER:
139 case UV3_HUB_PART_NUMBER_X:
140 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
141 break;
142
143 /* Update: UV4A has only a modified revision to indicate HUB fixes */
144 case UV4_HUB_PART_NUMBER:
145 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
146 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
147 break;
148 }
149
150 uv_hub_info->hub_revision = uv_min_hub_revision_id;
151 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
152 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
153 uv_cpuid.gpa_shift = 46; /* Default unless changed */
154
155 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
156 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
157 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
158 return pnode;
159 }
160
161 static void __init uv_tsc_check_sync(void)
162 {
163 u64 mmr;
164 int sync_state;
165 int mmr_shift;
166 char *state;
167 bool valid;
168
169 /* Accommodate different UV arch BIOSes */
170 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
171 mmr_shift =
172 is_uv1_hub() ? 0 :
173 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
174 if (mmr_shift)
175 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
176 else
177 sync_state = 0;
178
179 switch (sync_state) {
180 case UVH_TSC_SYNC_VALID:
181 state = "in sync";
182 valid = true;
183 break;
184
185 case UVH_TSC_SYNC_INVALID:
186 state = "unstable";
187 valid = false;
188 break;
189 default:
190 state = "unknown: assuming valid";
191 valid = true;
192 break;
193 }
194 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
195
196 /* Mark flag that says TSC != 0 is valid for socket 0 */
197 if (valid)
198 mark_tsc_async_resets("UV BIOS");
199 else
200 mark_tsc_unstable("UV BIOS");
201 }
202
203 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
204
205 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
206 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
207 #define SMT_TYPE 1
208 #define CORE_TYPE 2
209 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
210 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
211
212 static void set_x2apic_bits(void)
213 {
214 unsigned int eax, ebx, ecx, edx, sub_index;
215 unsigned int sid_shift;
216
217 cpuid(0, &eax, &ebx, &ecx, &edx);
218 if (eax < 0xb) {
219 pr_info("UV: CPU does not have CPUID.11\n");
220 return;
221 }
222
223 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
224 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
225 pr_info("UV: CPUID.11 not implemented\n");
226 return;
227 }
228
229 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
230 sub_index = 1;
231 do {
232 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
233 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
234 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
235 break;
236 }
237 sub_index++;
238 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
239
240 uv_cpuid.apicid_shift = 0;
241 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
242 uv_cpuid.socketid_shift = sid_shift;
243 }
244
245 static void __init early_get_apic_socketid_shift(void)
246 {
247 if (is_uv2_hub() || is_uv3_hub())
248 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
249
250 set_x2apic_bits();
251
252 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
253 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
254 }
255
256 /*
257 * Add an extra bit as dictated by bios to the destination apicid of
258 * interrupts potentially passing through the UV HUB. This prevents
259 * a deadlock between interrupts and IO port operations.
260 */
261 static void __init uv_set_apicid_hibit(void)
262 {
263 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
264
265 if (is_uv1_hub()) {
266 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
267 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
268 }
269 }
270
271 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
272 {
273 int pnodeid;
274 int uv_apic;
275
276 if (strncmp(oem_id, "SGI", 3) != 0) {
277 if (strncmp(oem_id, "NSGI", 4) == 0) {
278 uv_hubless_system = true;
279 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
280 oem_id, oem_table_id);
281 }
282 return 0;
283 }
284
285 if (numa_off) {
286 pr_err("UV: NUMA is off, disabling UV support\n");
287 return 0;
288 }
289
290 /* Set up early hub type field in uv_hub_info for Node 0 */
291 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
292
293 /*
294 * Determine UV arch type.
295 * SGI: UV100/1000
296 * SGI2: UV2000/3000
297 * SGI3: UV300 (truncated to 4 chars because of different varieties)
298 * SGI4: UV400 (truncated to 4 chars because of different varieties)
299 */
300 uv_hub_info->hub_revision =
301 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
302 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
303 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
304 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
305
306 if (uv_hub_info->hub_revision == 0)
307 goto badbios;
308
309 pnodeid = early_get_pnodeid();
310 early_get_apic_socketid_shift();
311
312 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
313 x86_platform.nmi_init = uv_nmi_init;
314
315 if (!strcmp(oem_table_id, "UVX")) {
316 /* This is the most common hardware variant: */
317 uv_system_type = UV_X2APIC;
318 uv_apic = 0;
319
320 } else if (!strcmp(oem_table_id, "UVH")) {
321 /* Only UV1 systems: */
322 uv_system_type = UV_NON_UNIQUE_APIC;
323 x86_platform.legacy.warm_reset = 0;
324 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
325 uv_set_apicid_hibit();
326 uv_apic = 1;
327
328 } else if (!strcmp(oem_table_id, "UVL")) {
329 /* Only used for very small systems: */
330 uv_system_type = UV_LEGACY_APIC;
331 uv_apic = 0;
332
333 } else {
334 goto badbios;
335 }
336
337 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
338 uv_tsc_check_sync();
339
340 return uv_apic;
341
342 badbios:
343 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
344 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
345 BUG();
346 }
347
348 enum uv_system_type get_uv_system_type(void)
349 {
350 return uv_system_type;
351 }
352
353 int is_uv_system(void)
354 {
355 return uv_system_type != UV_NONE;
356 }
357 EXPORT_SYMBOL_GPL(is_uv_system);
358
359 int is_uv_hubless(void)
360 {
361 return uv_hubless_system;
362 }
363 EXPORT_SYMBOL_GPL(is_uv_hubless);
364
365 void **__uv_hub_info_list;
366 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
367
368 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
369 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
370
371 short uv_possible_blades;
372 EXPORT_SYMBOL_GPL(uv_possible_blades);
373
374 unsigned long sn_rtc_cycles_per_second;
375 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
376
377 /* The following values are used for the per node hub info struct */
378 static __initdata unsigned short *_node_to_pnode;
379 static __initdata unsigned short _min_socket, _max_socket;
380 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
381 static __initdata struct uv_gam_range_entry *uv_gre_table;
382 static __initdata struct uv_gam_parameters *uv_gp_table;
383 static __initdata unsigned short *_socket_to_node;
384 static __initdata unsigned short *_socket_to_pnode;
385 static __initdata unsigned short *_pnode_to_socket;
386
387 static __initdata struct uv_gam_range_s *_gr_table;
388
389 #define SOCK_EMPTY ((unsigned short)~0)
390
391 extern int uv_hub_info_version(void)
392 {
393 return UV_HUB_INFO_VERSION;
394 }
395 EXPORT_SYMBOL(uv_hub_info_version);
396
397 /* Default UV memory block size is 2GB */
398 static unsigned long mem_block_size __initdata = (2UL << 30);
399
400 /* Kernel parameter to specify UV mem block size */
401 static int __init parse_mem_block_size(char *ptr)
402 {
403 unsigned long size = memparse(ptr, NULL);
404
405 /* Size will be rounded down by set_block_size() below */
406 mem_block_size = size;
407 return 0;
408 }
409 early_param("uv_memblksize", parse_mem_block_size);
410
411 static __init int adj_blksize(u32 lgre)
412 {
413 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
414 unsigned long size;
415
416 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
417 if (IS_ALIGNED(base, size))
418 break;
419
420 if (size >= mem_block_size)
421 return 0;
422
423 mem_block_size = size;
424 return 1;
425 }
426
427 static __init void set_block_size(void)
428 {
429 unsigned int order = ffs(mem_block_size);
430
431 if (order) {
432 /* adjust for ffs return of 1..64 */
433 set_memory_block_size_order(order - 1);
434 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
435 } else {
436 /* bad or zero value, default to 1UL << 31 (2GB) */
437 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
438 set_memory_block_size_order(31);
439 }
440 }
441
442 /* Build GAM range lookup table: */
443 static __init void build_uv_gr_table(void)
444 {
445 struct uv_gam_range_entry *gre = uv_gre_table;
446 struct uv_gam_range_s *grt;
447 unsigned long last_limit = 0, ram_limit = 0;
448 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
449
450 if (!gre)
451 return;
452
453 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
454 grt = kzalloc(bytes, GFP_KERNEL);
455 BUG_ON(!grt);
456 _gr_table = grt;
457
458 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
459 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
460 if (!ram_limit) {
461 /* Mark hole between RAM/non-RAM: */
462 ram_limit = last_limit;
463 last_limit = gre->limit;
464 lsid++;
465 continue;
466 }
467 last_limit = gre->limit;
468 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
469 continue;
470 }
471 if (_max_socket < gre->sockid) {
472 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
473 continue;
474 }
475 sid = gre->sockid - _min_socket;
476 if (lsid < sid) {
477 /* New range: */
478 grt = &_gr_table[indx];
479 grt->base = lindx;
480 grt->nasid = gre->nasid;
481 grt->limit = last_limit = gre->limit;
482 lsid = sid;
483 lindx = indx++;
484 continue;
485 }
486 /* Update range: */
487 if (lsid == sid && !ram_limit) {
488 /* .. if contiguous: */
489 if (grt->limit == last_limit) {
490 grt->limit = last_limit = gre->limit;
491 continue;
492 }
493 }
494 /* Non-contiguous RAM range: */
495 if (!ram_limit) {
496 grt++;
497 grt->base = lindx;
498 grt->nasid = gre->nasid;
499 grt->limit = last_limit = gre->limit;
500 continue;
501 }
502 /* Non-contiguous/non-RAM: */
503 grt++;
504 /* base is this entry */
505 grt->base = grt - _gr_table;
506 grt->nasid = gre->nasid;
507 grt->limit = last_limit = gre->limit;
508 lsid++;
509 }
510
511 /* Shorten table if possible */
512 grt++;
513 i = grt - _gr_table;
514 if (i < _gr_table_len) {
515 void *ret;
516
517 bytes = i * sizeof(struct uv_gam_range_s);
518 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
519 if (ret) {
520 _gr_table = ret;
521 _gr_table_len = i;
522 }
523 }
524
525 /* Display resultant GAM range table: */
526 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
527 unsigned long start, end;
528 int gb = grt->base;
529
530 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
531 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
532
533 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
534 }
535 }
536
537 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
538 {
539 unsigned long val;
540 int pnode;
541
542 pnode = uv_apicid_to_pnode(phys_apicid);
543 phys_apicid |= uv_apicid_hibits;
544
545 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
546 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
547 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
548 APIC_DM_INIT;
549
550 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
551
552 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
553 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
554 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
555 APIC_DM_STARTUP;
556
557 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
558
559 return 0;
560 }
561
562 static void uv_send_IPI_one(int cpu, int vector)
563 {
564 unsigned long apicid;
565 int pnode;
566
567 apicid = per_cpu(x86_cpu_to_apicid, cpu);
568 pnode = uv_apicid_to_pnode(apicid);
569 uv_hub_send_ipi(pnode, apicid, vector);
570 }
571
572 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
573 {
574 unsigned int cpu;
575
576 for_each_cpu(cpu, mask)
577 uv_send_IPI_one(cpu, vector);
578 }
579
580 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
581 {
582 unsigned int this_cpu = smp_processor_id();
583 unsigned int cpu;
584
585 for_each_cpu(cpu, mask) {
586 if (cpu != this_cpu)
587 uv_send_IPI_one(cpu, vector);
588 }
589 }
590
591 static void uv_send_IPI_allbutself(int vector)
592 {
593 unsigned int this_cpu = smp_processor_id();
594 unsigned int cpu;
595
596 for_each_online_cpu(cpu) {
597 if (cpu != this_cpu)
598 uv_send_IPI_one(cpu, vector);
599 }
600 }
601
602 static void uv_send_IPI_all(int vector)
603 {
604 uv_send_IPI_mask(cpu_online_mask, vector);
605 }
606
607 static int uv_apic_id_valid(u32 apicid)
608 {
609 return 1;
610 }
611
612 static int uv_apic_id_registered(void)
613 {
614 return 1;
615 }
616
617 static void uv_init_apic_ldr(void)
618 {
619 }
620
621 static u32 apic_uv_calc_apicid(unsigned int cpu)
622 {
623 return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
624 }
625
626 static unsigned int x2apic_get_apic_id(unsigned long x)
627 {
628 unsigned int id;
629
630 WARN_ON(preemptible() && num_online_cpus() > 1);
631 id = x | __this_cpu_read(x2apic_extra_bits);
632
633 return id;
634 }
635
636 static u32 set_apic_id(unsigned int id)
637 {
638 /* CHECKME: Do we need to mask out the xapic extra bits? */
639 return id;
640 }
641
642 static unsigned int uv_read_apic_id(void)
643 {
644 return x2apic_get_apic_id(apic_read(APIC_ID));
645 }
646
647 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
648 {
649 return uv_read_apic_id() >> index_msb;
650 }
651
652 static void uv_send_IPI_self(int vector)
653 {
654 apic_write(APIC_SELF_IPI, vector);
655 }
656
657 static int uv_probe(void)
658 {
659 return apic == &apic_x2apic_uv_x;
660 }
661
662 static struct apic apic_x2apic_uv_x __ro_after_init = {
663
664 .name = "UV large system",
665 .probe = uv_probe,
666 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
667 .apic_id_valid = uv_apic_id_valid,
668 .apic_id_registered = uv_apic_id_registered,
669
670 .irq_delivery_mode = dest_Fixed,
671 .irq_dest_mode = 0, /* Physical */
672
673 .disable_esr = 0,
674 .dest_logical = APIC_DEST_LOGICAL,
675 .check_apicid_used = NULL,
676
677 .init_apic_ldr = uv_init_apic_ldr,
678
679 .ioapic_phys_id_map = NULL,
680 .setup_apic_routing = NULL,
681 .cpu_present_to_apicid = default_cpu_present_to_apicid,
682 .apicid_to_cpu_present = NULL,
683 .check_phys_apicid_present = default_check_phys_apicid_present,
684 .phys_pkg_id = uv_phys_pkg_id,
685
686 .get_apic_id = x2apic_get_apic_id,
687 .set_apic_id = set_apic_id,
688
689 .calc_dest_apicid = apic_uv_calc_apicid,
690
691 .send_IPI = uv_send_IPI_one,
692 .send_IPI_mask = uv_send_IPI_mask,
693 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
694 .send_IPI_allbutself = uv_send_IPI_allbutself,
695 .send_IPI_all = uv_send_IPI_all,
696 .send_IPI_self = uv_send_IPI_self,
697
698 .wakeup_secondary_cpu = uv_wakeup_secondary,
699 .inquire_remote_apic = NULL,
700
701 .read = native_apic_msr_read,
702 .write = native_apic_msr_write,
703 .eoi_write = native_apic_msr_eoi_write,
704 .icr_read = native_x2apic_icr_read,
705 .icr_write = native_x2apic_icr_write,
706 .wait_icr_idle = native_x2apic_wait_icr_idle,
707 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
708 };
709
710 static void set_x2apic_extra_bits(int pnode)
711 {
712 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
713 }
714
715 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
716 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
717
718 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
719 {
720 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
721 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
722 unsigned long m_redirect;
723 unsigned long m_overlay;
724 int i;
725
726 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
727 switch (i) {
728 case 0:
729 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
730 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
731 break;
732 case 1:
733 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
734 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
735 break;
736 case 2:
737 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
738 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
739 break;
740 }
741 alias.v = uv_read_local_mmr(m_overlay);
742 if (alias.s.enable && alias.s.base == 0) {
743 *size = (1UL << alias.s.m_alias);
744 redirect.v = uv_read_local_mmr(m_redirect);
745 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
746 return;
747 }
748 }
749 *base = *size = 0;
750 }
751
752 enum map_type {map_wb, map_uc};
753
754 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
755 {
756 unsigned long bytes, paddr;
757
758 paddr = base << pshift;
759 bytes = (1UL << bshift) * (max_pnode + 1);
760 if (!paddr) {
761 pr_info("UV: Map %s_HI base address NULL\n", id);
762 return;
763 }
764 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
765 if (map_type == map_uc)
766 init_extra_mapping_uc(paddr, bytes);
767 else
768 init_extra_mapping_wb(paddr, bytes);
769 }
770
771 static __init void map_gru_distributed(unsigned long c)
772 {
773 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
774 u64 paddr;
775 unsigned long bytes;
776 int nid;
777
778 gru.v = c;
779
780 /* Only base bits 42:28 relevant in dist mode */
781 gru_dist_base = gru.v & 0x000007fff0000000UL;
782 if (!gru_dist_base) {
783 pr_info("UV: Map GRU_DIST base address NULL\n");
784 return;
785 }
786
787 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
788 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
789 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
790 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
791
792 for_each_online_node(nid) {
793 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
794 gru_dist_base;
795 init_extra_mapping_wb(paddr, bytes);
796 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
797 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
798 }
799
800 /* Save upper (63:M) bits of address only for is_GRU_range */
801 gru_first_node_paddr &= gru_dist_umask;
802 gru_last_node_paddr &= gru_dist_umask;
803
804 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
805 }
806
807 static __init void map_gru_high(int max_pnode)
808 {
809 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
810 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
811 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
812 unsigned long base;
813
814 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
815 if (!gru.s.enable) {
816 pr_info("UV: GRU disabled\n");
817 return;
818 }
819
820 /* Only UV3 has distributed GRU mode */
821 if (is_uv3_hub() && gru.s3.mode) {
822 map_gru_distributed(gru.v);
823 return;
824 }
825
826 base = (gru.v & mask) >> shift;
827 map_high("GRU", base, shift, shift, max_pnode, map_wb);
828 gru_start_paddr = ((u64)base << shift);
829 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
830 }
831
832 static __init void map_mmr_high(int max_pnode)
833 {
834 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
835 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
836
837 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
838 if (mmr.s.enable)
839 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
840 else
841 pr_info("UV: MMR disabled\n");
842 }
843
844 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
845 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
846 {
847 unsigned long overlay;
848 unsigned long mmr;
849 unsigned long base;
850 unsigned long nasid_mask;
851 unsigned long m_overlay;
852 int i, n, shift, m_io, max_io;
853 int nasid, lnasid, fi, li;
854 char *id;
855
856 if (index == 0) {
857 id = "MMIOH0";
858 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
859 overlay = uv_read_local_mmr(m_overlay);
860 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
861 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
862 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
863 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
864 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
865 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
866 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
867 } else {
868 id = "MMIOH1";
869 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
870 overlay = uv_read_local_mmr(m_overlay);
871 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
872 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
873 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
874 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
875 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
876 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
877 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
878 }
879 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
880 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
881 pr_info("UV: %s disabled\n", id);
882 return;
883 }
884
885 /* Convert to NASID: */
886 min_pnode *= 2;
887 max_pnode *= 2;
888 max_io = lnasid = fi = li = -1;
889
890 for (i = 0; i < n; i++) {
891 unsigned long m_redirect = mmr + i * 8;
892 unsigned long redirect = uv_read_local_mmr(m_redirect);
893
894 nasid = redirect & nasid_mask;
895 if (i == 0)
896 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
897 id, redirect, m_redirect, nasid);
898
899 /* Invalid NASID: */
900 if (nasid < min_pnode || max_pnode < nasid)
901 nasid = -1;
902
903 if (nasid == lnasid) {
904 li = i;
905 /* Last entry check: */
906 if (i != n-1)
907 continue;
908 }
909
910 /* Check if we have a cached (or last) redirect to print: */
911 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
912 unsigned long addr1, addr2;
913 int f, l;
914
915 if (lnasid == -1) {
916 f = l = i;
917 lnasid = nasid;
918 } else {
919 f = fi;
920 l = li;
921 }
922 addr1 = (base << shift) + f * (1ULL << m_io);
923 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
924 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
925 if (max_io < l)
926 max_io = l;
927 }
928 fi = li = i;
929 lnasid = nasid;
930 }
931
932 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
933
934 if (max_io >= 0)
935 map_high(id, base, shift, m_io, max_io, map_uc);
936 }
937
938 static __init void map_mmioh_high(int min_pnode, int max_pnode)
939 {
940 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
941 unsigned long mmr, base;
942 int shift, enable, m_io, n_io;
943
944 if (is_uv3_hub() || is_uv4_hub()) {
945 /* Map both MMIOH regions: */
946 map_mmioh_high_uv34(0, min_pnode, max_pnode);
947 map_mmioh_high_uv34(1, min_pnode, max_pnode);
948 return;
949 }
950
951 if (is_uv1_hub()) {
952 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
953 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
954 mmioh.v = uv_read_local_mmr(mmr);
955 enable = !!mmioh.s1.enable;
956 base = mmioh.s1.base;
957 m_io = mmioh.s1.m_io;
958 n_io = mmioh.s1.n_io;
959 } else if (is_uv2_hub()) {
960 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
961 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
962 mmioh.v = uv_read_local_mmr(mmr);
963 enable = !!mmioh.s2.enable;
964 base = mmioh.s2.base;
965 m_io = mmioh.s2.m_io;
966 n_io = mmioh.s2.n_io;
967 } else {
968 return;
969 }
970
971 if (enable) {
972 max_pnode &= (1 << n_io) - 1;
973 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
974 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
975 } else {
976 pr_info("UV: MMIOH disabled\n");
977 }
978 }
979
980 static __init void map_low_mmrs(void)
981 {
982 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
983 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
984 }
985
986 static __init void uv_rtc_init(void)
987 {
988 long status;
989 u64 ticks_per_sec;
990
991 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
992
993 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
994 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
995
996 /* BIOS gives wrong value for clock frequency, so guess: */
997 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
998 } else {
999 sn_rtc_cycles_per_second = ticks_per_sec;
1000 }
1001 }
1002
1003 /*
1004 * percpu heartbeat timer
1005 */
1006 static void uv_heartbeat(struct timer_list *timer)
1007 {
1008 unsigned char bits = uv_scir_info->state;
1009
1010 /* Flip heartbeat bit: */
1011 bits ^= SCIR_CPU_HEARTBEAT;
1012
1013 /* Is this CPU idle? */
1014 if (idle_cpu(raw_smp_processor_id()))
1015 bits &= ~SCIR_CPU_ACTIVITY;
1016 else
1017 bits |= SCIR_CPU_ACTIVITY;
1018
1019 /* Update system controller interface reg: */
1020 uv_set_scir_bits(bits);
1021
1022 /* Enable next timer period: */
1023 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1024 }
1025
1026 static int uv_heartbeat_enable(unsigned int cpu)
1027 {
1028 while (!uv_cpu_scir_info(cpu)->enabled) {
1029 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1030
1031 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1032 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
1033 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1034 add_timer_on(timer, cpu);
1035 uv_cpu_scir_info(cpu)->enabled = 1;
1036
1037 /* Also ensure that boot CPU is enabled: */
1038 cpu = 0;
1039 }
1040 return 0;
1041 }
1042
1043 #ifdef CONFIG_HOTPLUG_CPU
1044 static int uv_heartbeat_disable(unsigned int cpu)
1045 {
1046 if (uv_cpu_scir_info(cpu)->enabled) {
1047 uv_cpu_scir_info(cpu)->enabled = 0;
1048 del_timer(&uv_cpu_scir_info(cpu)->timer);
1049 }
1050 uv_set_cpu_scir_bits(cpu, 0xff);
1051 return 0;
1052 }
1053
1054 static __init void uv_scir_register_cpu_notifier(void)
1055 {
1056 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1057 uv_heartbeat_enable, uv_heartbeat_disable);
1058 }
1059
1060 #else /* !CONFIG_HOTPLUG_CPU */
1061
1062 static __init void uv_scir_register_cpu_notifier(void)
1063 {
1064 }
1065
1066 static __init int uv_init_heartbeat(void)
1067 {
1068 int cpu;
1069
1070 if (is_uv_system()) {
1071 for_each_online_cpu(cpu)
1072 uv_heartbeat_enable(cpu);
1073 }
1074
1075 return 0;
1076 }
1077
1078 late_initcall(uv_init_heartbeat);
1079
1080 #endif /* !CONFIG_HOTPLUG_CPU */
1081
1082 /* Direct Legacy VGA I/O traffic to designated IOH */
1083 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1084 {
1085 int domain, bus, rc;
1086
1087 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1088 return 0;
1089
1090 if ((command_bits & PCI_COMMAND_IO) == 0)
1091 return 0;
1092
1093 domain = pci_domain_nr(pdev->bus);
1094 bus = pdev->bus->number;
1095
1096 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1097
1098 return rc;
1099 }
1100
1101 /*
1102 * Called on each CPU to initialize the per_cpu UV data area.
1103 * FIXME: hotplug not supported yet
1104 */
1105 void uv_cpu_init(void)
1106 {
1107 /* CPU 0 initialization will be done via uv_system_init. */
1108 if (smp_processor_id() == 0)
1109 return;
1110
1111 uv_hub_info->nr_online_cpus++;
1112
1113 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1114 set_x2apic_extra_bits(uv_hub_info->pnode);
1115 }
1116
1117 struct mn {
1118 unsigned char m_val;
1119 unsigned char n_val;
1120 unsigned char m_shift;
1121 unsigned char n_lshift;
1122 };
1123
1124 static void get_mn(struct mn *mnp)
1125 {
1126 union uvh_rh_gam_config_mmr_u m_n_config;
1127 union uv3h_gr0_gam_gr_config_u m_gr_config;
1128
1129 /* Make sure the whole structure is well initialized: */
1130 memset(mnp, 0, sizeof(*mnp));
1131
1132 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1133 mnp->n_val = m_n_config.s.n_skt;
1134
1135 if (is_uv4_hub()) {
1136 mnp->m_val = 0;
1137 mnp->n_lshift = 0;
1138 } else if (is_uv3_hub()) {
1139 mnp->m_val = m_n_config.s3.m_skt;
1140 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1141 mnp->n_lshift = m_gr_config.s3.m_skt;
1142 } else if (is_uv2_hub()) {
1143 mnp->m_val = m_n_config.s2.m_skt;
1144 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1145 } else if (is_uv1_hub()) {
1146 mnp->m_val = m_n_config.s1.m_skt;
1147 mnp->n_lshift = mnp->m_val;
1148 }
1149 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1150 }
1151
1152 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1153 {
1154 union uvh_node_id_u node_id;
1155 struct mn mn;
1156
1157 get_mn(&mn);
1158 hi->gpa_mask = mn.m_val ?
1159 (1UL << (mn.m_val + mn.n_val)) - 1 :
1160 (1UL << uv_cpuid.gpa_shift) - 1;
1161
1162 hi->m_val = mn.m_val;
1163 hi->n_val = mn.n_val;
1164 hi->m_shift = mn.m_shift;
1165 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1166 hi->hub_revision = uv_hub_info->hub_revision;
1167 hi->pnode_mask = uv_cpuid.pnode_mask;
1168 hi->min_pnode = _min_pnode;
1169 hi->min_socket = _min_socket;
1170 hi->pnode_to_socket = _pnode_to_socket;
1171 hi->socket_to_node = _socket_to_node;
1172 hi->socket_to_pnode = _socket_to_pnode;
1173 hi->gr_table_len = _gr_table_len;
1174 hi->gr_table = _gr_table;
1175
1176 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1177 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1178 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1179 if (mn.m_val)
1180 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1181
1182 if (uv_gp_table) {
1183 hi->global_mmr_base = uv_gp_table->mmr_base;
1184 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1185 hi->global_gru_base = uv_gp_table->gru_base;
1186 hi->global_gru_shift = uv_gp_table->gru_shift;
1187 hi->gpa_shift = uv_gp_table->gpa_shift;
1188 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1189 } else {
1190 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1191 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1192 }
1193
1194 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1195
1196 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1197
1198 /* Show system specific info: */
1199 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1200 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1201 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1202 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1203 }
1204
1205 static void __init decode_gam_params(unsigned long ptr)
1206 {
1207 uv_gp_table = (struct uv_gam_parameters *)ptr;
1208
1209 pr_info("UV: GAM Params...\n");
1210 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1211 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1212 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1213 uv_gp_table->gpa_shift);
1214 }
1215
1216 static void __init decode_gam_rng_tbl(unsigned long ptr)
1217 {
1218 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1219 unsigned long lgre = 0;
1220 int index = 0;
1221 int sock_min = 999999, pnode_min = 99999;
1222 int sock_max = -1, pnode_max = -1;
1223
1224 uv_gre_table = gre;
1225 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1226 unsigned long size = ((unsigned long)(gre->limit - lgre)
1227 << UV_GAM_RANGE_SHFT);
1228 int order = 0;
1229 char suffix[] = " KMGTPE";
1230 int flag = ' ';
1231
1232 while (size > 9999 && order < sizeof(suffix)) {
1233 size /= 1024;
1234 order++;
1235 }
1236
1237 /* adjust max block size to current range start */
1238 if (gre->type == 1 || gre->type == 2)
1239 if (adj_blksize(lgre))
1240 flag = '*';
1241
1242 if (!index) {
1243 pr_info("UV: GAM Range Table...\n");
1244 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1245 }
1246 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1247 index++,
1248 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1249 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1250 flag, size, suffix[order],
1251 gre->type, gre->nasid, gre->sockid, gre->pnode);
1252
1253 /* update to next range start */
1254 lgre = gre->limit;
1255 if (sock_min > gre->sockid)
1256 sock_min = gre->sockid;
1257 if (sock_max < gre->sockid)
1258 sock_max = gre->sockid;
1259 if (pnode_min > gre->pnode)
1260 pnode_min = gre->pnode;
1261 if (pnode_max < gre->pnode)
1262 pnode_max = gre->pnode;
1263 }
1264 _min_socket = sock_min;
1265 _max_socket = sock_max;
1266 _min_pnode = pnode_min;
1267 _max_pnode = pnode_max;
1268 _gr_table_len = index;
1269
1270 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1271 }
1272
1273 static int __init decode_uv_systab(void)
1274 {
1275 struct uv_systab *st;
1276 int i;
1277
1278 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1279 return 0; /* No extended UVsystab required */
1280
1281 st = uv_systab;
1282 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1283 int rev = st ? st->revision : 0;
1284
1285 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1286 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1287 uv_system_type = UV_NONE;
1288
1289 return -EINVAL;
1290 }
1291
1292 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1293 unsigned long ptr = st->entry[i].offset;
1294
1295 if (!ptr)
1296 continue;
1297
1298 ptr = ptr + (unsigned long)st;
1299
1300 switch (st->entry[i].type) {
1301 case UV_SYSTAB_TYPE_GAM_PARAMS:
1302 decode_gam_params(ptr);
1303 break;
1304
1305 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1306 decode_gam_rng_tbl(ptr);
1307 break;
1308 }
1309 }
1310 return 0;
1311 }
1312
1313 /*
1314 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1315 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1316 * .. being replaced by GAM Range Table
1317 */
1318 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1319 {
1320 int i, uv_pb = 0;
1321
1322 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1323 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1324 unsigned long np;
1325
1326 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1327 if (np)
1328 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1329
1330 uv_pb += hweight64(np);
1331 }
1332 if (uv_possible_blades != uv_pb)
1333 uv_possible_blades = uv_pb;
1334 }
1335
1336 static void __init build_socket_tables(void)
1337 {
1338 struct uv_gam_range_entry *gre = uv_gre_table;
1339 int num, nump;
1340 int cpu, i, lnid;
1341 int minsock = _min_socket;
1342 int maxsock = _max_socket;
1343 int minpnode = _min_pnode;
1344 int maxpnode = _max_pnode;
1345 size_t bytes;
1346
1347 if (!gre) {
1348 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1349 pr_info("UV: No UVsystab socket table, ignoring\n");
1350 return;
1351 }
1352 pr_crit("UV: Error: UVsystab address translations not available!\n");
1353 BUG();
1354 }
1355
1356 /* Build socket id -> node id, pnode */
1357 num = maxsock - minsock + 1;
1358 bytes = num * sizeof(_socket_to_node[0]);
1359 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1360 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1361
1362 nump = maxpnode - minpnode + 1;
1363 bytes = nump * sizeof(_pnode_to_socket[0]);
1364 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1365 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1366
1367 for (i = 0; i < num; i++)
1368 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1369
1370 for (i = 0; i < nump; i++)
1371 _pnode_to_socket[i] = SOCK_EMPTY;
1372
1373 /* Fill in pnode/node/addr conversion list values: */
1374 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1375 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1376 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1377 continue;
1378 i = gre->sockid - minsock;
1379 /* Duplicate: */
1380 if (_socket_to_pnode[i] != SOCK_EMPTY)
1381 continue;
1382 _socket_to_pnode[i] = gre->pnode;
1383
1384 i = gre->pnode - minpnode;
1385 _pnode_to_socket[i] = gre->sockid;
1386
1387 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1388 gre->sockid, gre->type, gre->nasid,
1389 _socket_to_pnode[gre->sockid - minsock],
1390 _pnode_to_socket[gre->pnode - minpnode]);
1391 }
1392
1393 /* Set socket -> node values: */
1394 lnid = NUMA_NO_NODE;
1395 for_each_present_cpu(cpu) {
1396 int nid = cpu_to_node(cpu);
1397 int apicid, sockid;
1398
1399 if (lnid == nid)
1400 continue;
1401 lnid = nid;
1402 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1403 sockid = apicid >> uv_cpuid.socketid_shift;
1404 _socket_to_node[sockid - minsock] = nid;
1405 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1406 sockid, apicid, nid);
1407 }
1408
1409 /* Set up physical blade to pnode translation from GAM Range Table: */
1410 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1411 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1412 BUG_ON(!_node_to_pnode);
1413
1414 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1415 unsigned short sockid;
1416
1417 for (sockid = minsock; sockid <= maxsock; sockid++) {
1418 if (lnid == _socket_to_node[sockid - minsock]) {
1419 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1420 break;
1421 }
1422 }
1423 if (sockid > maxsock) {
1424 pr_err("UV: socket for node %d not found!\n", lnid);
1425 BUG();
1426 }
1427 }
1428
1429 /*
1430 * If socket id == pnode or socket id == node for all nodes,
1431 * system runs faster by removing corresponding conversion table.
1432 */
1433 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1434 if (minsock == 0) {
1435 for (i = 0; i < num; i++)
1436 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1437 break;
1438 if (i >= num) {
1439 kfree(_socket_to_node);
1440 _socket_to_node = NULL;
1441 pr_info("UV: 1:1 socket_to_node table removed\n");
1442 }
1443 }
1444 if (minsock == minpnode) {
1445 for (i = 0; i < num; i++)
1446 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1447 _socket_to_pnode[i] != i + minpnode)
1448 break;
1449 if (i >= num) {
1450 kfree(_socket_to_pnode);
1451 _socket_to_pnode = NULL;
1452 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1453 }
1454 }
1455 }
1456
1457 static void __init uv_system_init_hub(void)
1458 {
1459 struct uv_hub_info_s hub_info = {0};
1460 int bytes, cpu, nodeid;
1461 unsigned short min_pnode = 9999, max_pnode = 0;
1462 char *hub = is_uv4_hub() ? "UV400" :
1463 is_uv3_hub() ? "UV300" :
1464 is_uv2_hub() ? "UV2000/3000" :
1465 is_uv1_hub() ? "UV100/1000" : NULL;
1466
1467 if (!hub) {
1468 pr_err("UV: Unknown/unsupported UV hub\n");
1469 return;
1470 }
1471 pr_info("UV: Found %s hub\n", hub);
1472
1473 map_low_mmrs();
1474
1475 /* Get uv_systab for decoding: */
1476 uv_bios_init();
1477
1478 /* If there's an UVsystab problem then abort UV init: */
1479 if (decode_uv_systab() < 0)
1480 return;
1481
1482 build_socket_tables();
1483 build_uv_gr_table();
1484 set_block_size();
1485 uv_init_hub_info(&hub_info);
1486 uv_possible_blades = num_possible_nodes();
1487 if (!_node_to_pnode)
1488 boot_init_possible_blades(&hub_info);
1489
1490 /* uv_num_possible_blades() is really the hub count: */
1491 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1492
1493 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1494 hub_info.coherency_domain_number = sn_coherency_id;
1495 uv_rtc_init();
1496
1497 bytes = sizeof(void *) * uv_num_possible_blades();
1498 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1499 BUG_ON(!__uv_hub_info_list);
1500
1501 bytes = sizeof(struct uv_hub_info_s);
1502 for_each_node(nodeid) {
1503 struct uv_hub_info_s *new_hub;
1504
1505 if (__uv_hub_info_list[nodeid]) {
1506 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1507 BUG();
1508 }
1509
1510 /* Allocate new per hub info list */
1511 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1512 BUG_ON(!new_hub);
1513 __uv_hub_info_list[nodeid] = new_hub;
1514 new_hub = uv_hub_info_list(nodeid);
1515 BUG_ON(!new_hub);
1516 *new_hub = hub_info;
1517
1518 /* Use information from GAM table if available: */
1519 if (_node_to_pnode)
1520 new_hub->pnode = _node_to_pnode[nodeid];
1521 else /* Or fill in during CPU loop: */
1522 new_hub->pnode = 0xffff;
1523
1524 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1525 new_hub->memory_nid = NUMA_NO_NODE;
1526 new_hub->nr_possible_cpus = 0;
1527 new_hub->nr_online_cpus = 0;
1528 }
1529
1530 /* Initialize per CPU info: */
1531 for_each_possible_cpu(cpu) {
1532 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1533 int numa_node_id;
1534 unsigned short pnode;
1535
1536 nodeid = cpu_to_node(cpu);
1537 numa_node_id = numa_cpu_node(cpu);
1538 pnode = uv_apicid_to_pnode(apicid);
1539
1540 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1541 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1542 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1543 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1544
1545 /* Init memoryless node: */
1546 if (nodeid != numa_node_id &&
1547 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1548 uv_hub_info_list(numa_node_id)->pnode = pnode;
1549 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1550 uv_cpu_hub_info(cpu)->pnode = pnode;
1551
1552 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1553 }
1554
1555 for_each_node(nodeid) {
1556 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1557
1558 /* Add pnode info for pre-GAM list nodes without CPUs: */
1559 if (pnode == 0xffff) {
1560 unsigned long paddr;
1561
1562 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1563 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1564 uv_hub_info_list(nodeid)->pnode = pnode;
1565 }
1566 min_pnode = min(pnode, min_pnode);
1567 max_pnode = max(pnode, max_pnode);
1568 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1569 nodeid,
1570 uv_hub_info_list(nodeid)->pnode,
1571 uv_hub_info_list(nodeid)->nr_possible_cpus);
1572 }
1573
1574 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1575 map_gru_high(max_pnode);
1576 map_mmr_high(max_pnode);
1577 map_mmioh_high(min_pnode, max_pnode);
1578
1579 uv_nmi_setup();
1580 uv_cpu_init();
1581 uv_scir_register_cpu_notifier();
1582 proc_mkdir("sgi_uv", NULL);
1583
1584 /* Register Legacy VGA I/O redirection handler: */
1585 pci_register_set_vga_state(uv_set_vga_state);
1586
1587 /*
1588 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1589 * EFI is not enabled in the kdump kernel:
1590 */
1591 if (is_kdump_kernel())
1592 reboot_type = BOOT_ACPI;
1593 }
1594
1595 /*
1596 * There is a small amount of UV specific code needed to initialize a
1597 * UV system that does not have a "UV HUB" (referred to as "hubless").
1598 */
1599 void __init uv_system_init(void)
1600 {
1601 if (likely(!is_uv_system() && !is_uv_hubless()))
1602 return;
1603
1604 if (is_uv_system())
1605 uv_system_init_hub();
1606 else
1607 uv_nmi_setup_hubless();
1608 }
1609
1610 apic_driver(apic_x2apic_uv_x);
Linux with added FPC-III support