2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
9 * This file handles the architecture-dependent parts of process handling..
12 #include <linux/cpu.h>
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/task.h>
16 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/elfcore.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/reboot.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/ptrace.h>
33 #include <linux/personality.h>
34 #include <linux/percpu.h>
35 #include <linux/prctl.h>
36 #include <linux/ftrace.h>
37 #include <linux/uaccess.h>
39 #include <linux/kdebug.h>
40 #include <linux/syscalls.h>
42 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/fpu/internal.h>
48 #include <linux/err.h>
50 #include <asm/tlbflush.h>
52 #include <asm/syscalls.h>
53 #include <asm/debugreg.h>
54 #include <asm/switch_to.h>
56 #include <asm/resctrl_sched.h>
57 #include <asm/proto.h>
61 void __show_regs(struct pt_regs
*regs
, enum show_regs_mode mode
)
63 unsigned long cr0
= 0L, cr2
= 0L, cr3
= 0L, cr4
= 0L;
64 unsigned long d0
, d1
, d2
, d3
, d6
, d7
;
66 unsigned short ss
, gs
;
68 if (user_mode(regs
)) {
71 gs
= get_user_gs(regs
);
73 sp
= kernel_stack_pointer(regs
);
78 show_ip(regs
, KERN_DEFAULT
);
80 printk(KERN_DEFAULT
"EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
81 regs
->ax
, regs
->bx
, regs
->cx
, regs
->dx
);
82 printk(KERN_DEFAULT
"ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
83 regs
->si
, regs
->di
, regs
->bp
, sp
);
84 printk(KERN_DEFAULT
"DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
85 (u16
)regs
->ds
, (u16
)regs
->es
, (u16
)regs
->fs
, gs
, ss
, regs
->flags
);
87 if (mode
!= SHOW_REGS_ALL
)
94 printk(KERN_DEFAULT
"CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
104 /* Only print out debug registers if they are in their non-default state. */
105 if ((d0
== 0) && (d1
== 0) && (d2
== 0) && (d3
== 0) &&
106 (d6
== DR6_RESERVED
) && (d7
== 0x400))
109 printk(KERN_DEFAULT
"DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
111 printk(KERN_DEFAULT
"DR6: %08lx DR7: %08lx\n",
115 void release_thread(struct task_struct
*dead_task
)
117 BUG_ON(dead_task
->mm
);
118 release_vm86_irqs(dead_task
);
121 int copy_thread_tls(unsigned long clone_flags
, unsigned long sp
,
122 unsigned long arg
, struct task_struct
*p
, unsigned long tls
)
124 struct pt_regs
*childregs
= task_pt_regs(p
);
125 struct fork_frame
*fork_frame
= container_of(childregs
, struct fork_frame
, regs
);
126 struct inactive_task_frame
*frame
= &fork_frame
->frame
;
127 struct task_struct
*tsk
;
131 frame
->ret_addr
= (unsigned long) ret_from_fork
;
132 p
->thread
.sp
= (unsigned long) fork_frame
;
133 p
->thread
.sp0
= (unsigned long) (childregs
+1);
134 memset(p
->thread
.ptrace_bps
, 0, sizeof(p
->thread
.ptrace_bps
));
136 if (unlikely(p
->flags
& PF_KTHREAD
)) {
138 memset(childregs
, 0, sizeof(struct pt_regs
));
139 frame
->bx
= sp
; /* function */
141 p
->thread
.io_bitmap_ptr
= NULL
;
145 *childregs
= *current_pt_regs();
150 task_user_gs(p
) = get_user_gs(current_pt_regs());
152 p
->thread
.io_bitmap_ptr
= NULL
;
156 if (unlikely(test_tsk_thread_flag(tsk
, TIF_IO_BITMAP
))) {
157 p
->thread
.io_bitmap_ptr
= kmemdup(tsk
->thread
.io_bitmap_ptr
,
158 IO_BITMAP_BYTES
, GFP_KERNEL
);
159 if (!p
->thread
.io_bitmap_ptr
) {
160 p
->thread
.io_bitmap_max
= 0;
163 set_tsk_thread_flag(p
, TIF_IO_BITMAP
);
169 * Set a new TLS for the child thread?
171 if (clone_flags
& CLONE_SETTLS
)
172 err
= do_set_thread_area(p
, -1,
173 (struct user_desc __user
*)tls
, 0);
175 if (err
&& p
->thread
.io_bitmap_ptr
) {
176 kfree(p
->thread
.io_bitmap_ptr
);
177 p
->thread
.io_bitmap_max
= 0;
183 start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
185 set_user_gs(regs
, 0);
187 regs
->ds
= __USER_DS
;
188 regs
->es
= __USER_DS
;
189 regs
->ss
= __USER_DS
;
190 regs
->cs
= __USER_CS
;
193 regs
->flags
= X86_EFLAGS_IF
;
196 EXPORT_SYMBOL_GPL(start_thread
);
200 * switch_to(x,y) should switch tasks from x to y.
202 * We fsave/fwait so that an exception goes off at the right time
203 * (as a call from the fsave or fwait in effect) rather than to
204 * the wrong process. Lazy FP saving no longer makes any sense
205 * with modern CPU's, and this simplifies a lot of things (SMP
206 * and UP become the same).
208 * NOTE! We used to use the x86 hardware context switching. The
209 * reason for not using it any more becomes apparent when you
210 * try to recover gracefully from saved state that is no longer
211 * valid (stale segment register values in particular). With the
212 * hardware task-switch, there is no way to fix up bad state in
213 * a reasonable manner.
215 * The fact that Intel documents the hardware task-switching to
216 * be slow is a fairly red herring - this code is not noticeably
217 * faster. However, there _is_ some room for improvement here,
218 * so the performance issues may eventually be a valid point.
219 * More important, however, is the fact that this allows us much
222 * The return value (in %ax) will be the "prev" task after
223 * the task-switch, and shows up in ret_from_fork in entry.S,
226 __visible __notrace_funcgraph
struct task_struct
*
227 __switch_to(struct task_struct
*prev_p
, struct task_struct
*next_p
)
229 struct thread_struct
*prev
= &prev_p
->thread
,
230 *next
= &next_p
->thread
;
231 struct fpu
*prev_fpu
= &prev
->fpu
;
232 struct fpu
*next_fpu
= &next
->fpu
;
233 int cpu
= smp_processor_id();
235 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
237 switch_fpu_prepare(prev_fpu
, cpu
);
240 * Save away %gs. No need to save %fs, as it was saved on the
241 * stack on entry. No need to save %es and %ds, as those are
242 * always kernel segments while inside the kernel. Doing this
243 * before setting the new TLS descriptors avoids the situation
244 * where we temporarily have non-reloadable segments in %fs
245 * and %gs. This could be an issue if the NMI handler ever
246 * used %fs or %gs (it does not today), or if the kernel is
247 * running inside of a hypervisor layer.
249 lazy_save_gs(prev
->gs
);
252 * Load the per-thread Thread-Local Storage descriptor.
257 * Restore IOPL if needed. In normal use, the flags restore
258 * in the switch assembly will handle this. But if the kernel
259 * is running virtualized at a non-zero CPL, the popf will
260 * not restore flags, so it must be done in a separate step.
262 if (get_kernel_rpl() && unlikely(prev
->iopl
!= next
->iopl
))
263 set_iopl_mask(next
->iopl
);
265 switch_to_extra(prev_p
, next_p
);
268 * Leave lazy mode, flushing any hypercalls made here.
269 * This must be done before restoring TLS segments so
270 * the GDT and LDT are properly updated, and must be
271 * done before fpu__restore(), so the TS bit is up
274 arch_end_context_switch(next_p
);
277 * Reload esp0 and cpu_current_top_of_stack. This changes
278 * current_thread_info(). Refresh the SYSENTER configuration in
279 * case prev or next is vm86.
281 update_task_stack(next_p
);
282 refresh_sysenter_cs(next
);
283 this_cpu_write(cpu_current_top_of_stack
,
284 (unsigned long)task_stack_page(next_p
) +
288 * Restore %gs if needed (which is common)
290 if (prev
->gs
| next
->gs
)
291 lazy_load_gs(next
->gs
);
293 switch_fpu_finish(next_fpu
, cpu
);
295 this_cpu_write(current_task
, next_p
);
297 /* Load the Intel cache allocation PQR MSR. */
303 SYSCALL_DEFINE2(arch_prctl
, int, option
, unsigned long, arg2
)
305 return do_arch_prctl_common(current
, option
, arg2
);