drivers/spi/spi-omap-100k.c

   1 /*
   2  * OMAP7xx SPI 100k controller driver
   3  * Author: Fabrice Crohas <fcrohas@gmail.com>
   4  * from original omap1_mcspi driver
   5  *
   6  * Copyright (C) 2005, 2006 Nokia Corporation
   7  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   8  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/err.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/gpio.h>
  32 #include <linux/slab.h>
  33
  34 #include <linux/spi/spi.h>
  35
  36 #define OMAP1_SPI100K_MAX_FREQ          48000000
  37
  38 #define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
  39
  40 #define SPI_SETUP1      0x00
  41 #define SPI_SETUP2      0x02
  42 #define SPI_CTRL        0x04
  43 #define SPI_STATUS      0x06
  44 #define SPI_TX_LSB      0x08
  45 #define SPI_TX_MSB      0x0a
  46 #define SPI_RX_LSB      0x0c
  47 #define SPI_RX_MSB      0x0e
  48
  49 #define SPI_SETUP1_INT_READ_ENABLE      (1UL << 5)
  50 #define SPI_SETUP1_INT_WRITE_ENABLE     (1UL << 4)
  51 #define SPI_SETUP1_CLOCK_DIVISOR(x)     ((x) << 1)
  52 #define SPI_SETUP1_CLOCK_ENABLE         (1UL << 0)
  53
  54 #define SPI_SETUP2_ACTIVE_EDGE_FALLING  (0UL << 0)
  55 #define SPI_SETUP2_ACTIVE_EDGE_RISING   (1UL << 0)
  56 #define SPI_SETUP2_NEGATIVE_LEVEL       (0UL << 5)
  57 #define SPI_SETUP2_POSITIVE_LEVEL       (1UL << 5)
  58 #define SPI_SETUP2_LEVEL_TRIGGER        (0UL << 10)
  59 #define SPI_SETUP2_EDGE_TRIGGER         (1UL << 10)
  60
  61 #define SPI_CTRL_SEN(x)                 ((x) << 7)
  62 #define SPI_CTRL_WORD_SIZE(x)           (((x) - 1) << 2)
  63 #define SPI_CTRL_WR                     (1UL << 1)
  64 #define SPI_CTRL_RD                     (1UL << 0)
  65
  66 #define SPI_STATUS_WE                   (1UL << 1)
  67 #define SPI_STATUS_RD                   (1UL << 0)
  68
  69 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  70  * cache operations; better heuristics consider wordsize and bitrate.
  71  */
  72 #define DMA_MIN_BYTES                   8
  73
  74 #define SPI_RUNNING     0
  75 #define SPI_SHUTDOWN    1
  76
  77 struct omap1_spi100k {
  78         struct clk              *ick;
  79         struct clk              *fck;
  80
  81         /* Virtual base address of the controller */
  82         void __iomem            *base;
  83 };
  84
  85 struct omap1_spi100k_cs {
  86         void __iomem            *base;
  87         int                     word_len;
  88 };
  89
  90 static void spi100k_enable_clock(struct spi_master *master)
  91 {
  92         unsigned int val;
  93         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
  94
  95         /* enable SPI */
  96         val = readw(spi100k->base + SPI_SETUP1);
  97         val |= SPI_SETUP1_CLOCK_ENABLE;
  98         writew(val, spi100k->base + SPI_SETUP1);
  99 }
 100
 101 static void spi100k_disable_clock(struct spi_master *master)
 102 {
 103         unsigned int val;
 104         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 105
 106         /* disable SPI */
 107         val = readw(spi100k->base + SPI_SETUP1);
 108         val &= ~SPI_SETUP1_CLOCK_ENABLE;
 109         writew(val, spi100k->base + SPI_SETUP1);
 110 }
 111
 112 static void spi100k_write_data(struct spi_master *master, int len, int data)
 113 {
 114         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 115
 116         /* write 16-bit word, shifting 8-bit data if necessary */
 117         if (len <= 8) {
 118                 data <<= 8;
 119                 len = 16;
 120         }
 121
 122         spi100k_enable_clock(master);
 123         writew(data , spi100k->base + SPI_TX_MSB);
 124
 125         writew(SPI_CTRL_SEN(0) |
 126                SPI_CTRL_WORD_SIZE(len) |
 127                SPI_CTRL_WR,
 128                spi100k->base + SPI_CTRL);
 129
 130         /* Wait for bit ack send change */
 131         while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
 132                 ;
 133         udelay(1000);
 134
 135         spi100k_disable_clock(master);
 136 }
 137
 138 static int spi100k_read_data(struct spi_master *master, int len)
 139 {
 140         int dataH, dataL;
 141         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 142
 143         /* Always do at least 16 bits */
 144         if (len <= 8)
 145                 len = 16;
 146
 147         spi100k_enable_clock(master);
 148         writew(SPI_CTRL_SEN(0) |
 149                SPI_CTRL_WORD_SIZE(len) |
 150                SPI_CTRL_RD,
 151                spi100k->base + SPI_CTRL);
 152
 153         while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
 154                 ;
 155         udelay(1000);
 156
 157         dataL = readw(spi100k->base + SPI_RX_LSB);
 158         dataH = readw(spi100k->base + SPI_RX_MSB);
 159         spi100k_disable_clock(master);
 160
 161         return dataL;
 162 }
 163
 164 static void spi100k_open(struct spi_master *master)
 165 {
 166         /* get control of SPI */
 167         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 168
 169         writew(SPI_SETUP1_INT_READ_ENABLE |
 170                SPI_SETUP1_INT_WRITE_ENABLE |
 171                SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
 172
 173         /* configure clock and interrupts */
 174         writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
 175                SPI_SETUP2_NEGATIVE_LEVEL |
 176                SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
 177 }
 178
 179 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
 180 {
 181         if (enable)
 182                 writew(0x05fc, spi100k->base + SPI_CTRL);
 183         else
 184                 writew(0x05fd, spi100k->base + SPI_CTRL);
 185 }
 186
 187 static unsigned
 188 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 189 {
 190         struct omap1_spi100k_cs *cs = spi->controller_state;
 191         unsigned int            count, c;
 192         int                     word_len;
 193
 194         count = xfer->len;
 195         c = count;
 196         word_len = cs->word_len;
 197
 198         if (word_len <= 8) {
 199                 u8              *rx;
 200                 const u8        *tx;
 201
 202                 rx = xfer->rx_buf;
 203                 tx = xfer->tx_buf;
 204                 do {
 205                         c -= 1;
 206                         if (xfer->tx_buf != NULL)
 207                                 spi100k_write_data(spi->master, word_len, *tx++);
 208                         if (xfer->rx_buf != NULL)
 209                                 *rx++ = spi100k_read_data(spi->master, word_len);
 210                 } while (c);
 211         } else if (word_len <= 16) {
 212                 u16             *rx;
 213                 const u16       *tx;
 214
 215                 rx = xfer->rx_buf;
 216                 tx = xfer->tx_buf;
 217                 do {
 218                         c -= 2;
 219                         if (xfer->tx_buf != NULL)
 220                                 spi100k_write_data(spi->master, word_len, *tx++);
 221                         if (xfer->rx_buf != NULL)
 222                                 *rx++ = spi100k_read_data(spi->master, word_len);
 223                 } while (c);
 224         } else if (word_len <= 32) {
 225                 u32             *rx;
 226                 const u32       *tx;
 227
 228                 rx = xfer->rx_buf;
 229                 tx = xfer->tx_buf;
 230                 do {
 231                         c -= 4;
 232                         if (xfer->tx_buf != NULL)
 233                                 spi100k_write_data(spi->master, word_len, *tx);
 234                         if (xfer->rx_buf != NULL)
 235                                 *rx = spi100k_read_data(spi->master, word_len);
 236                 } while (c);
 237         }
 238         return count - c;
 239 }
 240
 241 /* called only when no transfer is active to this device */
 242 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
 243                 struct spi_transfer *t)
 244 {
 245         struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
 246         struct omap1_spi100k_cs *cs = spi->controller_state;
 247         u8 word_len = spi->bits_per_word;
 248
 249         if (t != NULL && t->bits_per_word)
 250                 word_len = t->bits_per_word;
 251         if (!word_len)
 252                 word_len = 8;
 253
 254         if (spi->bits_per_word > 32)
 255                 return -EINVAL;
 256         cs->word_len = word_len;
 257
 258         /* SPI init before transfer */
 259         writew(0x3e , spi100k->base + SPI_SETUP1);
 260         writew(0x00 , spi100k->base + SPI_STATUS);
 261         writew(0x3e , spi100k->base + SPI_CTRL);
 262
 263         return 0;
 264 }
 265
 266 /* the spi->mode bits understood by this driver: */
 267 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 268
 269 static int omap1_spi100k_setup(struct spi_device *spi)
 270 {
 271         int                     ret;
 272         struct omap1_spi100k    *spi100k;
 273         struct omap1_spi100k_cs *cs = spi->controller_state;
 274
 275         spi100k = spi_master_get_devdata(spi->master);
 276
 277         if (!cs) {
 278                 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
 279                 if (!cs)
 280                         return -ENOMEM;
 281                 cs->base = spi100k->base + spi->chip_select * 0x14;
 282                 spi->controller_state = cs;
 283         }
 284
 285         spi100k_open(spi->master);
 286
 287         clk_prepare_enable(spi100k->ick);
 288         clk_prepare_enable(spi100k->fck);
 289
 290         ret = omap1_spi100k_setup_transfer(spi, NULL);
 291
 292         clk_disable_unprepare(spi100k->ick);
 293         clk_disable_unprepare(spi100k->fck);
 294
 295         return ret;
 296 }
 297
 298 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
 299                                               struct spi_message *m)
 300 {
 301         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 302         struct spi_device *spi = m->spi;
 303         struct spi_transfer *t = NULL;
 304         int cs_active = 0;
 305         int par_override = 0;
 306         int status = 0;
 307
 308         list_for_each_entry(t, &m->transfers, transfer_list) {
 309                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 310                         status = -EINVAL;
 311                         break;
 312                 }
 313                 if (par_override || t->speed_hz || t->bits_per_word) {
 314                         par_override = 1;
 315                         status = omap1_spi100k_setup_transfer(spi, t);
 316                         if (status < 0)
 317                                 break;
 318                         if (!t->speed_hz && !t->bits_per_word)
 319                                 par_override = 0;
 320                 }
 321
 322                 if (!cs_active) {
 323                         omap1_spi100k_force_cs(spi100k, 1);
 324                         cs_active = 1;
 325                 }
 326
 327                 if (t->len) {
 328                         unsigned count;
 329
 330                         count = omap1_spi100k_txrx_pio(spi, t);
 331                         m->actual_length += count;
 332
 333                         if (count != t->len) {
 334                                 status = -EIO;
 335                                 break;
 336                         }
 337                 }
 338
 339                 if (t->delay_usecs)
 340                         udelay(t->delay_usecs);
 341
 342                 /* ignore the "leave it on after last xfer" hint */
 343
 344                 if (t->cs_change) {
 345                         omap1_spi100k_force_cs(spi100k, 0);
 346                         cs_active = 0;
 347                 }
 348         }
 349
 350         /* Restore defaults if they were overriden */
 351         if (par_override) {
 352                 par_override = 0;
 353                 status = omap1_spi100k_setup_transfer(spi, NULL);
 354         }
 355
 356         if (cs_active)
 357                 omap1_spi100k_force_cs(spi100k, 0);
 358
 359         m->status = status;
 360
 361         spi_finalize_current_message(master);
 362
 363         return status;
 364 }
 365
 366 static int omap1_spi100k_probe(struct platform_device *pdev)
 367 {
 368         struct spi_master       *master;
 369         struct omap1_spi100k    *spi100k;
 370         int                     status = 0;
 371
 372         if (!pdev->id)
 373                 return -EINVAL;
 374
 375         master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
 376         if (master == NULL) {
 377                 dev_dbg(&pdev->dev, "master allocation failed\n");
 378                 return -ENOMEM;
 379         }
 380
 381         if (pdev->id != -1)
 382                 master->bus_num = pdev->id;
 383
 384         master->setup = omap1_spi100k_setup;
 385         master->transfer_one_message = omap1_spi100k_transfer_one_message;
 386         master->num_chipselect = 2;
 387         master->mode_bits = MODEBITS;
 388         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 389         master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
 390         master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
 391         master->auto_runtime_pm = true;
 392
 393         spi100k = spi_master_get_devdata(master);
 394
 395         /*
 396          * The memory region base address is taken as the platform_data.
 397          * You should allocate this with ioremap() before initializing
 398          * the SPI.
 399          */
 400         spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
 401
 402         spi100k->ick = devm_clk_get(&pdev->dev, "ick");
 403         if (IS_ERR(spi100k->ick)) {
 404                 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
 405                 status = PTR_ERR(spi100k->ick);
 406                 goto err;
 407         }
 408
 409         spi100k->fck = devm_clk_get(&pdev->dev, "fck");
 410         if (IS_ERR(spi100k->fck)) {
 411                 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
 412                 status = PTR_ERR(spi100k->fck);
 413                 goto err;
 414         }
 415
 416         status = clk_prepare_enable(spi100k->ick);
 417         if (status != 0) {
 418                 dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
 419                 goto err;
 420         }
 421
 422         status = clk_prepare_enable(spi100k->fck);
 423         if (status != 0) {
 424                 dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
 425                 goto err_ick;
 426         }
 427
 428         pm_runtime_enable(&pdev->dev);
 429         pm_runtime_set_active(&pdev->dev);
 430
 431         status = devm_spi_register_master(&pdev->dev, master);
 432         if (status < 0)
 433                 goto err_fck;
 434
 435         return status;
 436
 437 err_fck:
 438         clk_disable_unprepare(spi100k->fck);
 439 err_ick:
 440         clk_disable_unprepare(spi100k->ick);
 441 err:
 442         spi_master_put(master);
 443         return status;
 444 }
 445
 446 static int omap1_spi100k_remove(struct platform_device *pdev)
 447 {
 448         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 449         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 450
 451         pm_runtime_disable(&pdev->dev);
 452
 453         clk_disable_unprepare(spi100k->fck);
 454         clk_disable_unprepare(spi100k->ick);
 455
 456         return 0;
 457 }
 458
 459 #ifdef CONFIG_PM
 460 static int omap1_spi100k_runtime_suspend(struct device *dev)
 461 {
 462         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
 463         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 464
 465         clk_disable_unprepare(spi100k->ick);
 466         clk_disable_unprepare(spi100k->fck);
 467
 468         return 0;
 469 }
 470
 471 static int omap1_spi100k_runtime_resume(struct device *dev)
 472 {
 473         struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
 474         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 475         int ret;
 476
 477         ret = clk_prepare_enable(spi100k->ick);
 478         if (ret != 0) {
 479                 dev_err(dev, "Failed to enable ick: %d\n", ret);
 480                 return ret;
 481         }
 482
 483         ret = clk_prepare_enable(spi100k->fck);
 484         if (ret != 0) {
 485                 dev_err(dev, "Failed to enable fck: %d\n", ret);
 486                 clk_disable_unprepare(spi100k->ick);
 487                 return ret;
 488         }
 489
 490         return 0;
 491 }
 492 #endif
 493
 494 static const struct dev_pm_ops omap1_spi100k_pm = {
 495         SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
 496                            omap1_spi100k_runtime_resume, NULL)
 497 };
 498
 499 static struct platform_driver omap1_spi100k_driver = {
 500         .driver = {
 501                 .name           = "omap1_spi100k",
 502                 .pm             = &omap1_spi100k_pm,
 503         },
 504         .probe          = omap1_spi100k_probe,
 505         .remove         = omap1_spi100k_remove,
 506 };
 507
 508 module_platform_driver(omap1_spi100k_driver);
 509
 510 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
 511 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
 512 MODULE_LICENSE("GPL");