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udf: improve error management in udf_CS0toUTF8()
[linux/fpc-iii.git] / drivers / spi / spi-topcliff-pch.c
blob93dfcee0f987b705be1329893c950ad19989ccd8
1 /*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 *
4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/delay.h>
17 #include <linux/pci.h>
18 #include <linux/wait.h>
19 #include <linux/spi/spi.h>
20 #include <linux/interrupt.h>
21 #include <linux/sched.h>
22 #include <linux/spi/spidev.h>
23 #include <linux/module.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include <linux/dmaengine.h>
28 #include <linux/pch_dma.h>
29
30 /* Register offsets */
31 #define PCH_SPCR 0x00 /* SPI control register */
32 #define PCH_SPBRR 0x04 /* SPI baud rate register */
33 #define PCH_SPSR 0x08 /* SPI status register */
34 #define PCH_SPDWR 0x0C /* SPI write data register */
35 #define PCH_SPDRR 0x10 /* SPI read data register */
36 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
37 #define PCH_SRST 0x1C /* SPI reset register */
38 #define PCH_ADDRESS_SIZE 0x20
39
40 #define PCH_SPSR_TFD 0x000007C0
41 #define PCH_SPSR_RFD 0x0000F800
42
43 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
44 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
45
46 #define PCH_RX_THOLD 7
47 #define PCH_RX_THOLD_MAX 15
48
49 #define PCH_TX_THOLD 2
50
51 #define PCH_MAX_BAUDRATE 5000000
52 #define PCH_MAX_FIFO_DEPTH 16
53
54 #define STATUS_RUNNING 1
55 #define STATUS_EXITING 2
56 #define PCH_SLEEP_TIME 10
57
58 #define SSN_LOW 0x02U
59 #define SSN_HIGH 0x03U
60 #define SSN_NO_CONTROL 0x00U
61 #define PCH_MAX_CS 0xFF
62 #define PCI_DEVICE_ID_GE_SPI 0x8816
63
64 #define SPCR_SPE_BIT (1 << 0)
65 #define SPCR_MSTR_BIT (1 << 1)
66 #define SPCR_LSBF_BIT (1 << 4)
67 #define SPCR_CPHA_BIT (1 << 5)
68 #define SPCR_CPOL_BIT (1 << 6)
69 #define SPCR_TFIE_BIT (1 << 8)
70 #define SPCR_RFIE_BIT (1 << 9)
71 #define SPCR_FIE_BIT (1 << 10)
72 #define SPCR_ORIE_BIT (1 << 11)
73 #define SPCR_MDFIE_BIT (1 << 12)
74 #define SPCR_FICLR_BIT (1 << 24)
75 #define SPSR_TFI_BIT (1 << 0)
76 #define SPSR_RFI_BIT (1 << 1)
77 #define SPSR_FI_BIT (1 << 2)
78 #define SPSR_ORF_BIT (1 << 3)
79 #define SPBRR_SIZE_BIT (1 << 10)
80
81 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
82 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
83
84 #define SPCR_RFIC_FIELD 20
85 #define SPCR_TFIC_FIELD 16
86
87 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
88 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
89 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
90
91 #define PCH_CLOCK_HZ 50000000
92 #define PCH_MAX_SPBR 1023
93
94 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
95 #define PCI_VENDOR_ID_ROHM 0x10DB
96 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
97 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
98 #define PCI_DEVICE_ID_ML7831_SPI 0x8816
99
100 /*
101 * Set the number of SPI instance max
102 * Intel EG20T PCH : 1ch
103 * LAPIS Semiconductor ML7213 IOH : 2ch
104 * LAPIS Semiconductor ML7223 IOH : 1ch
105 * LAPIS Semiconductor ML7831 IOH : 1ch
106 */
107 #define PCH_SPI_MAX_DEV 2
108
109 #define PCH_BUF_SIZE 4096
110 #define PCH_DMA_TRANS_SIZE 12
111
112 static int use_dma = 1;
113
114 struct pch_spi_dma_ctrl {
115 struct dma_async_tx_descriptor *desc_tx;
116 struct dma_async_tx_descriptor *desc_rx;
117 struct pch_dma_slave param_tx;
118 struct pch_dma_slave param_rx;
119 struct dma_chan *chan_tx;
120 struct dma_chan *chan_rx;
121 struct scatterlist *sg_tx_p;
122 struct scatterlist *sg_rx_p;
123 struct scatterlist sg_tx;
124 struct scatterlist sg_rx;
125 int nent;
126 void *tx_buf_virt;
127 void *rx_buf_virt;
128 dma_addr_t tx_buf_dma;
129 dma_addr_t rx_buf_dma;
130 };
131 /**
132 * struct pch_spi_data - Holds the SPI channel specific details
133 * @io_remap_addr: The remapped PCI base address
134 * @master: Pointer to the SPI master structure
135 * @work: Reference to work queue handler
136 * @wk: Workqueue for carrying out execution of the
137 * requests
138 * @wait: Wait queue for waking up upon receiving an
139 * interrupt.
140 * @transfer_complete: Status of SPI Transfer
141 * @bcurrent_msg_processing: Status flag for message processing
142 * @lock: Lock for protecting this structure
143 * @queue: SPI Message queue
144 * @status: Status of the SPI driver
145 * @bpw_len: Length of data to be transferred in bits per
146 * word
147 * @transfer_active: Flag showing active transfer
148 * @tx_index: Transmit data count; for bookkeeping during
149 * transfer
150 * @rx_index: Receive data count; for bookkeeping during
151 * transfer
152 * @tx_buff: Buffer for data to be transmitted
153 * @rx_index: Buffer for Received data
154 * @n_curnt_chip: The chip number that this SPI driver currently
155 * operates on
156 * @current_chip: Reference to the current chip that this SPI
157 * driver currently operates on
158 * @current_msg: The current message that this SPI driver is
159 * handling
160 * @cur_trans: The current transfer that this SPI driver is
161 * handling
162 * @board_dat: Reference to the SPI device data structure
163 * @plat_dev: platform_device structure
164 * @ch: SPI channel number
165 * @irq_reg_sts: Status of IRQ registration
166 */
167 struct pch_spi_data {
168 void __iomem *io_remap_addr;
169 unsigned long io_base_addr;
170 struct spi_master *master;
171 struct work_struct work;
172 struct workqueue_struct *wk;
173 wait_queue_head_t wait;
174 u8 transfer_complete;
175 u8 bcurrent_msg_processing;
176 spinlock_t lock;
177 struct list_head queue;
178 u8 status;
179 u32 bpw_len;
180 u8 transfer_active;
181 u32 tx_index;
182 u32 rx_index;
183 u16 *pkt_tx_buff;
184 u16 *pkt_rx_buff;
185 u8 n_curnt_chip;
186 struct spi_device *current_chip;
187 struct spi_message *current_msg;
188 struct spi_transfer *cur_trans;
189 struct pch_spi_board_data *board_dat;
190 struct platform_device *plat_dev;
191 int ch;
192 struct pch_spi_dma_ctrl dma;
193 int use_dma;
194 u8 irq_reg_sts;
195 int save_total_len;
196 };
197
198 /**
199 * struct pch_spi_board_data - Holds the SPI device specific details
200 * @pdev: Pointer to the PCI device
201 * @suspend_sts: Status of suspend
202 * @num: The number of SPI device instance
203 */
204 struct pch_spi_board_data {
205 struct pci_dev *pdev;
206 u8 suspend_sts;
207 int num;
208 };
209
210 struct pch_pd_dev_save {
211 int num;
212 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
213 struct pch_spi_board_data *board_dat;
214 };
215
216 static const struct pci_device_id pch_spi_pcidev_id[] = {
217 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
218 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
219 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
220 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
221 { }
222 };
223
224 /**
225 * pch_spi_writereg() - Performs register writes
226 * @master: Pointer to struct spi_master.
227 * @idx: Register offset.
228 * @val: Value to be written to register.
229 */
230 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
231 {
232 struct pch_spi_data *data = spi_master_get_devdata(master);
233 iowrite32(val, (data->io_remap_addr + idx));
234 }
235
236 /**
237 * pch_spi_readreg() - Performs register reads
238 * @master: Pointer to struct spi_master.
239 * @idx: Register offset.
240 */
241 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
242 {
243 struct pch_spi_data *data = spi_master_get_devdata(master);
244 return ioread32(data->io_remap_addr + idx);
245 }
246
247 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
248 u32 set, u32 clr)
249 {
250 u32 tmp = pch_spi_readreg(master, idx);
251 tmp = (tmp & ~clr) | set;
252 pch_spi_writereg(master, idx, tmp);
253 }
254
255 static void pch_spi_set_master_mode(struct spi_master *master)
256 {
257 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
258 }
259
260 /**
261 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
262 * @master: Pointer to struct spi_master.
263 */
264 static void pch_spi_clear_fifo(struct spi_master *master)
265 {
266 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
267 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
268 }
269
270 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
271 void __iomem *io_remap_addr)
272 {
273 u32 n_read, tx_index, rx_index, bpw_len;
274 u16 *pkt_rx_buffer, *pkt_tx_buff;
275 int read_cnt;
276 u32 reg_spcr_val;
277 void __iomem *spsr;
278 void __iomem *spdrr;
279 void __iomem *spdwr;
280
281 spsr = io_remap_addr + PCH_SPSR;
282 iowrite32(reg_spsr_val, spsr);
283
284 if (data->transfer_active) {
285 rx_index = data->rx_index;
286 tx_index = data->tx_index;
287 bpw_len = data->bpw_len;
288 pkt_rx_buffer = data->pkt_rx_buff;
289 pkt_tx_buff = data->pkt_tx_buff;
290
291 spdrr = io_remap_addr + PCH_SPDRR;
292 spdwr = io_remap_addr + PCH_SPDWR;
293
294 n_read = PCH_READABLE(reg_spsr_val);
295
296 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
297 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
298 if (tx_index < bpw_len)
299 iowrite32(pkt_tx_buff[tx_index++], spdwr);
300 }
301
302 /* disable RFI if not needed */
303 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
304 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
305 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
306
307 /* reset rx threshold */
308 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
309 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
310
311 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
312 }
313
314 /* update counts */
315 data->tx_index = tx_index;
316 data->rx_index = rx_index;
317
318 /* if transfer complete interrupt */
319 if (reg_spsr_val & SPSR_FI_BIT) {
320 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
321 /* disable interrupts */
322 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
323 PCH_ALL);
324
325 /* transfer is completed;
326 inform pch_spi_process_messages */
327 data->transfer_complete = true;
328 data->transfer_active = false;
329 wake_up(&data->wait);
330 } else {
331 dev_vdbg(&data->master->dev,
332 "%s : Transfer is not completed",
333 __func__);
334 }
335 }
336 }
337 }
338
339 /**
340 * pch_spi_handler() - Interrupt handler
341 * @irq: The interrupt number.
342 * @dev_id: Pointer to struct pch_spi_board_data.
343 */
344 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
345 {
346 u32 reg_spsr_val;
347 void __iomem *spsr;
348 void __iomem *io_remap_addr;
349 irqreturn_t ret = IRQ_NONE;
350 struct pch_spi_data *data = dev_id;
351 struct pch_spi_board_data *board_dat = data->board_dat;
352
353 if (board_dat->suspend_sts) {
354 dev_dbg(&board_dat->pdev->dev,
355 "%s returning due to suspend\n", __func__);
356 return IRQ_NONE;
357 }
358
359 io_remap_addr = data->io_remap_addr;
360 spsr = io_remap_addr + PCH_SPSR;
361
362 reg_spsr_val = ioread32(spsr);
363
364 if (reg_spsr_val & SPSR_ORF_BIT) {
365 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
366 if (data->current_msg->complete) {
367 data->transfer_complete = true;
368 data->current_msg->status = -EIO;
369 data->current_msg->complete(data->current_msg->context);
370 data->bcurrent_msg_processing = false;
371 data->current_msg = NULL;
372 data->cur_trans = NULL;
373 }
374 }
375
376 if (data->use_dma)
377 return IRQ_NONE;
378
379 /* Check if the interrupt is for SPI device */
380 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
381 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
382 ret = IRQ_HANDLED;
383 }
384
385 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
386 __func__, ret);
387
388 return ret;
389 }
390
391 /**
392 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
393 * @master: Pointer to struct spi_master.
394 * @speed_hz: Baud rate.
395 */
396 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
397 {
398 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
399
400 /* if baud rate is less than we can support limit it */
401 if (n_spbr > PCH_MAX_SPBR)
402 n_spbr = PCH_MAX_SPBR;
403
404 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
405 }
406
407 /**
408 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
409 * @master: Pointer to struct spi_master.
410 * @bits_per_word: Bits per word for SPI transfer.
411 */
412 static void pch_spi_set_bits_per_word(struct spi_master *master,
413 u8 bits_per_word)
414 {
415 if (bits_per_word == 8)
416 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
417 else
418 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
419 }
420
421 /**
422 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
423 * @spi: Pointer to struct spi_device.
424 */
425 static void pch_spi_setup_transfer(struct spi_device *spi)
426 {
427 u32 flags = 0;
428
429 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
430 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
431 spi->max_speed_hz);
432 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
433
434 /* set bits per word */
435 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
436
437 if (!(spi->mode & SPI_LSB_FIRST))
438 flags |= SPCR_LSBF_BIT;
439 if (spi->mode & SPI_CPOL)
440 flags |= SPCR_CPOL_BIT;
441 if (spi->mode & SPI_CPHA)
442 flags |= SPCR_CPHA_BIT;
443 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
444 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
445
446 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
447 pch_spi_clear_fifo(spi->master);
448 }
449
450 /**
451 * pch_spi_reset() - Clears SPI registers
452 * @master: Pointer to struct spi_master.
453 */
454 static void pch_spi_reset(struct spi_master *master)
455 {
456 /* write 1 to reset SPI */
457 pch_spi_writereg(master, PCH_SRST, 0x1);
458
459 /* clear reset */
460 pch_spi_writereg(master, PCH_SRST, 0x0);
461 }
462
463 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
464 {
465
466 struct spi_transfer *transfer;
467 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
468 int retval;
469 unsigned long flags;
470
471 spin_lock_irqsave(&data->lock, flags);
472 /* validate Tx/Rx buffers and Transfer length */
473 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
474 if (!transfer->tx_buf && !transfer->rx_buf) {
475 dev_err(&pspi->dev,
476 "%s Tx and Rx buffer NULL\n", __func__);
477 retval = -EINVAL;
478 goto err_return_spinlock;
479 }
480
481 if (!transfer->len) {
482 dev_err(&pspi->dev, "%s Transfer length invalid\n",
483 __func__);
484 retval = -EINVAL;
485 goto err_return_spinlock;
486 }
487
488 dev_dbg(&pspi->dev,
489 "%s Tx/Rx buffer valid. Transfer length valid\n",
490 __func__);
491 }
492 spin_unlock_irqrestore(&data->lock, flags);
493
494 /* We won't process any messages if we have been asked to terminate */
495 if (data->status == STATUS_EXITING) {
496 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
497 retval = -ESHUTDOWN;
498 goto err_out;
499 }
500
501 /* If suspended ,return -EINVAL */
502 if (data->board_dat->suspend_sts) {
503 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
504 retval = -EINVAL;
505 goto err_out;
506 }
507
508 /* set status of message */
509 pmsg->actual_length = 0;
510 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
511
512 pmsg->status = -EINPROGRESS;
513 spin_lock_irqsave(&data->lock, flags);
514 /* add message to queue */
515 list_add_tail(&pmsg->queue, &data->queue);
516 spin_unlock_irqrestore(&data->lock, flags);
517
518 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
519
520 /* schedule work queue to run */
521 queue_work(data->wk, &data->work);
522 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
523
524 retval = 0;
525
526 err_out:
527 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
528 return retval;
529 err_return_spinlock:
530 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
531 spin_unlock_irqrestore(&data->lock, flags);
532 return retval;
533 }
534
535 static inline void pch_spi_select_chip(struct pch_spi_data *data,
536 struct spi_device *pspi)
537 {
538 if (data->current_chip != NULL) {
539 if (pspi->chip_select != data->n_curnt_chip) {
540 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
541 data->current_chip = NULL;
542 }
543 }
544
545 data->current_chip = pspi;
546
547 data->n_curnt_chip = data->current_chip->chip_select;
548
549 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
550 pch_spi_setup_transfer(pspi);
551 }
552
553 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
554 {
555 int size;
556 u32 n_writes;
557 int j;
558 struct spi_message *pmsg, *tmp;
559 const u8 *tx_buf;
560 const u16 *tx_sbuf;
561
562 /* set baud rate if needed */
563 if (data->cur_trans->speed_hz) {
564 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
565 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
566 }
567
568 /* set bits per word if needed */
569 if (data->cur_trans->bits_per_word &&
570 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
571 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
572 pch_spi_set_bits_per_word(data->master,
573 data->cur_trans->bits_per_word);
574 *bpw = data->cur_trans->bits_per_word;
575 } else {
576 *bpw = data->current_msg->spi->bits_per_word;
577 }
578
579 /* reset Tx/Rx index */
580 data->tx_index = 0;
581 data->rx_index = 0;
582
583 data->bpw_len = data->cur_trans->len / (*bpw / 8);
584
585 /* find alloc size */
586 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
587
588 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
589 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
590 if (data->pkt_tx_buff != NULL) {
591 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
592 if (!data->pkt_rx_buff)
593 kfree(data->pkt_tx_buff);
594 }
595
596 if (!data->pkt_rx_buff) {
597 /* flush queue and set status of all transfers to -ENOMEM */
598 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
599 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
600 pmsg->status = -ENOMEM;
601
602 if (pmsg->complete)
603 pmsg->complete(pmsg->context);
604
605 /* delete from queue */
606 list_del_init(&pmsg->queue);
607 }
608 return;
609 }
610
611 /* copy Tx Data */
612 if (data->cur_trans->tx_buf != NULL) {
613 if (*bpw == 8) {
614 tx_buf = data->cur_trans->tx_buf;
615 for (j = 0; j < data->bpw_len; j++)
616 data->pkt_tx_buff[j] = *tx_buf++;
617 } else {
618 tx_sbuf = data->cur_trans->tx_buf;
619 for (j = 0; j < data->bpw_len; j++)
620 data->pkt_tx_buff[j] = *tx_sbuf++;
621 }
622 }
623
624 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
625 n_writes = data->bpw_len;
626 if (n_writes > PCH_MAX_FIFO_DEPTH)
627 n_writes = PCH_MAX_FIFO_DEPTH;
628
629 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
630 "0x2 to SSNXCR\n", __func__);
631 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
632
633 for (j = 0; j < n_writes; j++)
634 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
635
636 /* update tx_index */
637 data->tx_index = j;
638
639 /* reset transfer complete flag */
640 data->transfer_complete = false;
641 data->transfer_active = true;
642 }
643
644 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
645 {
646 struct spi_message *pmsg, *tmp;
647 dev_dbg(&data->master->dev, "%s called\n", __func__);
648 /* Invoke complete callback
649 * [To the spi core..indicating end of transfer] */
650 data->current_msg->status = 0;
651
652 if (data->current_msg->complete) {
653 dev_dbg(&data->master->dev,
654 "%s:Invoking callback of SPI core\n", __func__);
655 data->current_msg->complete(data->current_msg->context);
656 }
657
658 /* update status in global variable */
659 data->bcurrent_msg_processing = false;
660
661 dev_dbg(&data->master->dev,
662 "%s:data->bcurrent_msg_processing = false\n", __func__);
663
664 data->current_msg = NULL;
665 data->cur_trans = NULL;
666
667 /* check if we have items in list and not suspending
668 * return 1 if list empty */
669 if ((list_empty(&data->queue) == 0) &&
670 (!data->board_dat->suspend_sts) &&
671 (data->status != STATUS_EXITING)) {
672 /* We have some more work to do (either there is more tranint
673 * bpw;sfer requests in the current message or there are
674 *more messages)
675 */
676 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
677 queue_work(data->wk, &data->work);
678 } else if (data->board_dat->suspend_sts ||
679 data->status == STATUS_EXITING) {
680 dev_dbg(&data->master->dev,
681 "%s suspend/remove initiated, flushing queue\n",
682 __func__);
683 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
684 pmsg->status = -EIO;
685
686 if (pmsg->complete)
687 pmsg->complete(pmsg->context);
688
689 /* delete from queue */
690 list_del_init(&pmsg->queue);
691 }
692 }
693 }
694
695 static void pch_spi_set_ir(struct pch_spi_data *data)
696 {
697 /* enable interrupts, set threshold, enable SPI */
698 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
699 /* set receive threshold to PCH_RX_THOLD */
700 pch_spi_setclr_reg(data->master, PCH_SPCR,
701 PCH_RX_THOLD << SPCR_RFIC_FIELD |
702 SPCR_FIE_BIT | SPCR_RFIE_BIT |
703 SPCR_ORIE_BIT | SPCR_SPE_BIT,
704 MASK_RFIC_SPCR_BITS | PCH_ALL);
705 else
706 /* set receive threshold to maximum */
707 pch_spi_setclr_reg(data->master, PCH_SPCR,
708 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
709 SPCR_FIE_BIT | SPCR_ORIE_BIT |
710 SPCR_SPE_BIT,
711 MASK_RFIC_SPCR_BITS | PCH_ALL);
712
713 /* Wait until the transfer completes; go to sleep after
714 initiating the transfer. */
715 dev_dbg(&data->master->dev,
716 "%s:waiting for transfer to get over\n", __func__);
717
718 wait_event_interruptible(data->wait, data->transfer_complete);
719
720 /* clear all interrupts */
721 pch_spi_writereg(data->master, PCH_SPSR,
722 pch_spi_readreg(data->master, PCH_SPSR));
723 /* Disable interrupts and SPI transfer */
724 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
725 /* clear FIFO */
726 pch_spi_clear_fifo(data->master);
727 }
728
729 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
730 {
731 int j;
732 u8 *rx_buf;
733 u16 *rx_sbuf;
734
735 /* copy Rx Data */
736 if (!data->cur_trans->rx_buf)
737 return;
738
739 if (bpw == 8) {
740 rx_buf = data->cur_trans->rx_buf;
741 for (j = 0; j < data->bpw_len; j++)
742 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
743 } else {
744 rx_sbuf = data->cur_trans->rx_buf;
745 for (j = 0; j < data->bpw_len; j++)
746 *rx_sbuf++ = data->pkt_rx_buff[j];
747 }
748 }
749
750 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
751 {
752 int j;
753 u8 *rx_buf;
754 u16 *rx_sbuf;
755 const u8 *rx_dma_buf;
756 const u16 *rx_dma_sbuf;
757
758 /* copy Rx Data */
759 if (!data->cur_trans->rx_buf)
760 return;
761
762 if (bpw == 8) {
763 rx_buf = data->cur_trans->rx_buf;
764 rx_dma_buf = data->dma.rx_buf_virt;
765 for (j = 0; j < data->bpw_len; j++)
766 *rx_buf++ = *rx_dma_buf++ & 0xFF;
767 data->cur_trans->rx_buf = rx_buf;
768 } else {
769 rx_sbuf = data->cur_trans->rx_buf;
770 rx_dma_sbuf = data->dma.rx_buf_virt;
771 for (j = 0; j < data->bpw_len; j++)
772 *rx_sbuf++ = *rx_dma_sbuf++;
773 data->cur_trans->rx_buf = rx_sbuf;
774 }
775 }
776
777 static int pch_spi_start_transfer(struct pch_spi_data *data)
778 {
779 struct pch_spi_dma_ctrl *dma;
780 unsigned long flags;
781 int rtn;
782
783 dma = &data->dma;
784
785 spin_lock_irqsave(&data->lock, flags);
786
787 /* disable interrupts, SPI set enable */
788 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
789
790 spin_unlock_irqrestore(&data->lock, flags);
791
792 /* Wait until the transfer completes; go to sleep after
793 initiating the transfer. */
794 dev_dbg(&data->master->dev,
795 "%s:waiting for transfer to get over\n", __func__);
796 rtn = wait_event_interruptible_timeout(data->wait,
797 data->transfer_complete,
798 msecs_to_jiffies(2 * HZ));
799 if (!rtn)
800 dev_err(&data->master->dev,
801 "%s wait-event timeout\n", __func__);
802
803 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
804 DMA_FROM_DEVICE);
805
806 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
807 DMA_FROM_DEVICE);
808 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
809
810 async_tx_ack(dma->desc_rx);
811 async_tx_ack(dma->desc_tx);
812 kfree(dma->sg_tx_p);
813 kfree(dma->sg_rx_p);
814
815 spin_lock_irqsave(&data->lock, flags);
816
817 /* clear fifo threshold, disable interrupts, disable SPI transfer */
818 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
819 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
820 SPCR_SPE_BIT);
821 /* clear all interrupts */
822 pch_spi_writereg(data->master, PCH_SPSR,
823 pch_spi_readreg(data->master, PCH_SPSR));
824 /* clear FIFO */
825 pch_spi_clear_fifo(data->master);
826
827 spin_unlock_irqrestore(&data->lock, flags);
828
829 return rtn;
830 }
831
832 static void pch_dma_rx_complete(void *arg)
833 {
834 struct pch_spi_data *data = arg;
835
836 /* transfer is completed;inform pch_spi_process_messages_dma */
837 data->transfer_complete = true;
838 wake_up_interruptible(&data->wait);
839 }
840
841 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
842 {
843 struct pch_dma_slave *param = slave;
844
845 if ((chan->chan_id == param->chan_id) &&
846 (param->dma_dev == chan->device->dev)) {
847 chan->private = param;
848 return true;
849 } else {
850 return false;
851 }
852 }
853
854 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
855 {
856 dma_cap_mask_t mask;
857 struct dma_chan *chan;
858 struct pci_dev *dma_dev;
859 struct pch_dma_slave *param;
860 struct pch_spi_dma_ctrl *dma;
861 unsigned int width;
862
863 if (bpw == 8)
864 width = PCH_DMA_WIDTH_1_BYTE;
865 else
866 width = PCH_DMA_WIDTH_2_BYTES;
867
868 dma = &data->dma;
869 dma_cap_zero(mask);
870 dma_cap_set(DMA_SLAVE, mask);
871
872 /* Get DMA's dev information */
873 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
874 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
875
876 /* Set Tx DMA */
877 param = &dma->param_tx;
878 param->dma_dev = &dma_dev->dev;
879 param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
880 param->tx_reg = data->io_base_addr + PCH_SPDWR;
881 param->width = width;
882 chan = dma_request_channel(mask, pch_spi_filter, param);
883 if (!chan) {
884 dev_err(&data->master->dev,
885 "ERROR: dma_request_channel FAILS(Tx)\n");
886 data->use_dma = 0;
887 return;
888 }
889 dma->chan_tx = chan;
890
891 /* Set Rx DMA */
892 param = &dma->param_rx;
893 param->dma_dev = &dma_dev->dev;
894 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
895 param->rx_reg = data->io_base_addr + PCH_SPDRR;
896 param->width = width;
897 chan = dma_request_channel(mask, pch_spi_filter, param);
898 if (!chan) {
899 dev_err(&data->master->dev,
900 "ERROR: dma_request_channel FAILS(Rx)\n");
901 dma_release_channel(dma->chan_tx);
902 dma->chan_tx = NULL;
903 data->use_dma = 0;
904 return;
905 }
906 dma->chan_rx = chan;
907 }
908
909 static void pch_spi_release_dma(struct pch_spi_data *data)
910 {
911 struct pch_spi_dma_ctrl *dma;
912
913 dma = &data->dma;
914 if (dma->chan_tx) {
915 dma_release_channel(dma->chan_tx);
916 dma->chan_tx = NULL;
917 }
918 if (dma->chan_rx) {
919 dma_release_channel(dma->chan_rx);
920 dma->chan_rx = NULL;
921 }
922 return;
923 }
924
925 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
926 {
927 const u8 *tx_buf;
928 const u16 *tx_sbuf;
929 u8 *tx_dma_buf;
930 u16 *tx_dma_sbuf;
931 struct scatterlist *sg;
932 struct dma_async_tx_descriptor *desc_tx;
933 struct dma_async_tx_descriptor *desc_rx;
934 int num;
935 int i;
936 int size;
937 int rem;
938 int head;
939 unsigned long flags;
940 struct pch_spi_dma_ctrl *dma;
941
942 dma = &data->dma;
943
944 /* set baud rate if needed */
945 if (data->cur_trans->speed_hz) {
946 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
947 spin_lock_irqsave(&data->lock, flags);
948 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
949 spin_unlock_irqrestore(&data->lock, flags);
950 }
951
952 /* set bits per word if needed */
953 if (data->cur_trans->bits_per_word &&
954 (data->current_msg->spi->bits_per_word !=
955 data->cur_trans->bits_per_word)) {
956 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
957 spin_lock_irqsave(&data->lock, flags);
958 pch_spi_set_bits_per_word(data->master,
959 data->cur_trans->bits_per_word);
960 spin_unlock_irqrestore(&data->lock, flags);
961 *bpw = data->cur_trans->bits_per_word;
962 } else {
963 *bpw = data->current_msg->spi->bits_per_word;
964 }
965 data->bpw_len = data->cur_trans->len / (*bpw / 8);
966
967 if (data->bpw_len > PCH_BUF_SIZE) {
968 data->bpw_len = PCH_BUF_SIZE;
969 data->cur_trans->len -= PCH_BUF_SIZE;
970 }
971
972 /* copy Tx Data */
973 if (data->cur_trans->tx_buf != NULL) {
974 if (*bpw == 8) {
975 tx_buf = data->cur_trans->tx_buf;
976 tx_dma_buf = dma->tx_buf_virt;
977 for (i = 0; i < data->bpw_len; i++)
978 *tx_dma_buf++ = *tx_buf++;
979 } else {
980 tx_sbuf = data->cur_trans->tx_buf;
981 tx_dma_sbuf = dma->tx_buf_virt;
982 for (i = 0; i < data->bpw_len; i++)
983 *tx_dma_sbuf++ = *tx_sbuf++;
984 }
985 }
986
987 /* Calculate Rx parameter for DMA transmitting */
988 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
989 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
990 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
991 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
992 } else {
993 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
994 rem = PCH_DMA_TRANS_SIZE;
995 }
996 size = PCH_DMA_TRANS_SIZE;
997 } else {
998 num = 1;
999 size = data->bpw_len;
1000 rem = data->bpw_len;
1001 }
1002 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1003 __func__, num, size, rem);
1004 spin_lock_irqsave(&data->lock, flags);
1005
1006 /* set receive fifo threshold and transmit fifo threshold */
1007 pch_spi_setclr_reg(data->master, PCH_SPCR,
1008 ((size - 1) << SPCR_RFIC_FIELD) |
1009 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1010 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1011
1012 spin_unlock_irqrestore(&data->lock, flags);
1013
1014 /* RX */
1015 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1016 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1017 /* offset, length setting */
1018 sg = dma->sg_rx_p;
1019 for (i = 0; i < num; i++, sg++) {
1020 if (i == (num - 2)) {
1021 sg->offset = size * i;
1022 sg->offset = sg->offset * (*bpw / 8);
1023 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1024 sg->offset);
1025 sg_dma_len(sg) = rem;
1026 } else if (i == (num - 1)) {
1027 sg->offset = size * (i - 1) + rem;
1028 sg->offset = sg->offset * (*bpw / 8);
1029 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1030 sg->offset);
1031 sg_dma_len(sg) = size;
1032 } else {
1033 sg->offset = size * i;
1034 sg->offset = sg->offset * (*bpw / 8);
1035 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1036 sg->offset);
1037 sg_dma_len(sg) = size;
1038 }
1039 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1040 }
1041 sg = dma->sg_rx_p;
1042 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1043 num, DMA_DEV_TO_MEM,
1044 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1045 if (!desc_rx) {
1046 dev_err(&data->master->dev,
1047 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1048 return;
1049 }
1050 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1051 desc_rx->callback = pch_dma_rx_complete;
1052 desc_rx->callback_param = data;
1053 dma->nent = num;
1054 dma->desc_rx = desc_rx;
1055
1056 /* Calculate Tx parameter for DMA transmitting */
1057 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1058 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1059 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1060 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1061 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1062 } else {
1063 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1064 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1065 PCH_DMA_TRANS_SIZE - head;
1066 }
1067 size = PCH_DMA_TRANS_SIZE;
1068 } else {
1069 num = 1;
1070 size = data->bpw_len;
1071 rem = data->bpw_len;
1072 head = 0;
1073 }
1074
1075 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1076 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1077 /* offset, length setting */
1078 sg = dma->sg_tx_p;
1079 for (i = 0; i < num; i++, sg++) {
1080 if (i == 0) {
1081 sg->offset = 0;
1082 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1083 sg->offset);
1084 sg_dma_len(sg) = size + head;
1085 } else if (i == (num - 1)) {
1086 sg->offset = head + size * i;
1087 sg->offset = sg->offset * (*bpw / 8);
1088 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1089 sg->offset);
1090 sg_dma_len(sg) = rem;
1091 } else {
1092 sg->offset = head + size * i;
1093 sg->offset = sg->offset * (*bpw / 8);
1094 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1095 sg->offset);
1096 sg_dma_len(sg) = size;
1097 }
1098 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1099 }
1100 sg = dma->sg_tx_p;
1101 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1102 sg, num, DMA_MEM_TO_DEV,
1103 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1104 if (!desc_tx) {
1105 dev_err(&data->master->dev,
1106 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1107 return;
1108 }
1109 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1110 desc_tx->callback = NULL;
1111 desc_tx->callback_param = data;
1112 dma->nent = num;
1113 dma->desc_tx = desc_tx;
1114
1115 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1116
1117 spin_lock_irqsave(&data->lock, flags);
1118 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1119 desc_rx->tx_submit(desc_rx);
1120 desc_tx->tx_submit(desc_tx);
1121 spin_unlock_irqrestore(&data->lock, flags);
1122
1123 /* reset transfer complete flag */
1124 data->transfer_complete = false;
1125 }
1126
1127 static void pch_spi_process_messages(struct work_struct *pwork)
1128 {
1129 struct spi_message *pmsg, *tmp;
1130 struct pch_spi_data *data;
1131 int bpw;
1132
1133 data = container_of(pwork, struct pch_spi_data, work);
1134 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1135
1136 spin_lock(&data->lock);
1137 /* check if suspend has been initiated;if yes flush queue */
1138 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1139 dev_dbg(&data->master->dev,
1140 "%s suspend/remove initiated, flushing queue\n", __func__);
1141 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1142 pmsg->status = -EIO;
1143
1144 if (pmsg->complete) {
1145 spin_unlock(&data->lock);
1146 pmsg->complete(pmsg->context);
1147 spin_lock(&data->lock);
1148 }
1149
1150 /* delete from queue */
1151 list_del_init(&pmsg->queue);
1152 }
1153
1154 spin_unlock(&data->lock);
1155 return;
1156 }
1157
1158 data->bcurrent_msg_processing = true;
1159 dev_dbg(&data->master->dev,
1160 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1161
1162 /* Get the message from the queue and delete it from there. */
1163 data->current_msg = list_entry(data->queue.next, struct spi_message,
1164 queue);
1165
1166 list_del_init(&data->current_msg->queue);
1167
1168 data->current_msg->status = 0;
1169
1170 pch_spi_select_chip(data, data->current_msg->spi);
1171
1172 spin_unlock(&data->lock);
1173
1174 if (data->use_dma)
1175 pch_spi_request_dma(data,
1176 data->current_msg->spi->bits_per_word);
1177 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1178 do {
1179 int cnt;
1180 /* If we are already processing a message get the next
1181 transfer structure from the message otherwise retrieve
1182 the 1st transfer request from the message. */
1183 spin_lock(&data->lock);
1184 if (data->cur_trans == NULL) {
1185 data->cur_trans =
1186 list_entry(data->current_msg->transfers.next,
1187 struct spi_transfer, transfer_list);
1188 dev_dbg(&data->master->dev, "%s "
1189 ":Getting 1st transfer message\n", __func__);
1190 } else {
1191 data->cur_trans =
1192 list_entry(data->cur_trans->transfer_list.next,
1193 struct spi_transfer, transfer_list);
1194 dev_dbg(&data->master->dev, "%s "
1195 ":Getting next transfer message\n", __func__);
1196 }
1197 spin_unlock(&data->lock);
1198
1199 if (!data->cur_trans->len)
1200 goto out;
1201 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1202 data->save_total_len = data->cur_trans->len;
1203 if (data->use_dma) {
1204 int i;
1205 char *save_rx_buf = data->cur_trans->rx_buf;
1206 for (i = 0; i < cnt; i ++) {
1207 pch_spi_handle_dma(data, &bpw);
1208 if (!pch_spi_start_transfer(data)) {
1209 data->transfer_complete = true;
1210 data->current_msg->status = -EIO;
1211 data->current_msg->complete
1212 (data->current_msg->context);
1213 data->bcurrent_msg_processing = false;
1214 data->current_msg = NULL;
1215 data->cur_trans = NULL;
1216 goto out;
1217 }
1218 pch_spi_copy_rx_data_for_dma(data, bpw);
1219 }
1220 data->cur_trans->rx_buf = save_rx_buf;
1221 } else {
1222 pch_spi_set_tx(data, &bpw);
1223 pch_spi_set_ir(data);
1224 pch_spi_copy_rx_data(data, bpw);
1225 kfree(data->pkt_rx_buff);
1226 data->pkt_rx_buff = NULL;
1227 kfree(data->pkt_tx_buff);
1228 data->pkt_tx_buff = NULL;
1229 }
1230 /* increment message count */
1231 data->cur_trans->len = data->save_total_len;
1232 data->current_msg->actual_length += data->cur_trans->len;
1233
1234 dev_dbg(&data->master->dev,
1235 "%s:data->current_msg->actual_length=%d\n",
1236 __func__, data->current_msg->actual_length);
1237
1238 /* check for delay */
1239 if (data->cur_trans->delay_usecs) {
1240 dev_dbg(&data->master->dev, "%s:"
1241 "delay in usec=%d\n", __func__,
1242 data->cur_trans->delay_usecs);
1243 udelay(data->cur_trans->delay_usecs);
1244 }
1245
1246 spin_lock(&data->lock);
1247
1248 /* No more transfer in this message. */
1249 if ((data->cur_trans->transfer_list.next) ==
1250 &(data->current_msg->transfers)) {
1251 pch_spi_nomore_transfer(data);
1252 }
1253
1254 spin_unlock(&data->lock);
1255
1256 } while (data->cur_trans != NULL);
1257
1258 out:
1259 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1260 if (data->use_dma)
1261 pch_spi_release_dma(data);
1262 }
1263
1264 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1265 struct pch_spi_data *data)
1266 {
1267 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1268
1269 /* free workqueue */
1270 if (data->wk != NULL) {
1271 destroy_workqueue(data->wk);
1272 data->wk = NULL;
1273 dev_dbg(&board_dat->pdev->dev,
1274 "%s destroy_workqueue invoked successfully\n",
1275 __func__);
1276 }
1277 }
1278
1279 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1280 struct pch_spi_data *data)
1281 {
1282 int retval = 0;
1283
1284 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1285
1286 /* create workqueue */
1287 data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1288 if (!data->wk) {
1289 dev_err(&board_dat->pdev->dev,
1290 "%s create_singlet hread_workqueue failed\n", __func__);
1291 retval = -EBUSY;
1292 goto err_return;
1293 }
1294
1295 /* reset PCH SPI h/w */
1296 pch_spi_reset(data->master);
1297 dev_dbg(&board_dat->pdev->dev,
1298 "%s pch_spi_reset invoked successfully\n", __func__);
1299
1300 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1301
1302 err_return:
1303 if (retval != 0) {
1304 dev_err(&board_dat->pdev->dev,
1305 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1306 pch_spi_free_resources(board_dat, data);
1307 }
1308
1309 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1310
1311 return retval;
1312 }
1313
1314 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1315 struct pch_spi_data *data)
1316 {
1317 struct pch_spi_dma_ctrl *dma;
1318
1319 dma = &data->dma;
1320 if (dma->tx_buf_dma)
1321 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1322 dma->tx_buf_virt, dma->tx_buf_dma);
1323 if (dma->rx_buf_dma)
1324 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1325 dma->rx_buf_virt, dma->rx_buf_dma);
1326 return;
1327 }
1328
1329 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1330 struct pch_spi_data *data)
1331 {
1332 struct pch_spi_dma_ctrl *dma;
1333
1334 dma = &data->dma;
1335 /* Get Consistent memory for Tx DMA */
1336 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1337 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1338 /* Get Consistent memory for Rx DMA */
1339 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1340 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1341 }
1342
1343 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1344 {
1345 int ret;
1346 struct spi_master *master;
1347 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1348 struct pch_spi_data *data;
1349
1350 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1351
1352 master = spi_alloc_master(&board_dat->pdev->dev,
1353 sizeof(struct pch_spi_data));
1354 if (!master) {
1355 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1356 plat_dev->id);
1357 return -ENOMEM;
1358 }
1359
1360 data = spi_master_get_devdata(master);
1361 data->master = master;
1362
1363 platform_set_drvdata(plat_dev, data);
1364
1365 /* baseaddress + address offset) */
1366 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1367 PCH_ADDRESS_SIZE * plat_dev->id;
1368 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1369 if (!data->io_remap_addr) {
1370 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1371 ret = -ENOMEM;
1372 goto err_pci_iomap;
1373 }
1374 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1375
1376 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1377 plat_dev->id, data->io_remap_addr);
1378
1379 /* initialize members of SPI master */
1380 master->num_chipselect = PCH_MAX_CS;
1381 master->transfer = pch_spi_transfer;
1382 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1383 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1384 master->max_speed_hz = PCH_MAX_BAUDRATE;
1385
1386 data->board_dat = board_dat;
1387 data->plat_dev = plat_dev;
1388 data->n_curnt_chip = 255;
1389 data->status = STATUS_RUNNING;
1390 data->ch = plat_dev->id;
1391 data->use_dma = use_dma;
1392
1393 INIT_LIST_HEAD(&data->queue);
1394 spin_lock_init(&data->lock);
1395 INIT_WORK(&data->work, pch_spi_process_messages);
1396 init_waitqueue_head(&data->wait);
1397
1398 ret = pch_spi_get_resources(board_dat, data);
1399 if (ret) {
1400 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1401 goto err_spi_get_resources;
1402 }
1403
1404 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1405 IRQF_SHARED, KBUILD_MODNAME, data);
1406 if (ret) {
1407 dev_err(&plat_dev->dev,
1408 "%s request_irq failed\n", __func__);
1409 goto err_request_irq;
1410 }
1411 data->irq_reg_sts = true;
1412
1413 pch_spi_set_master_mode(master);
1414
1415 if (use_dma) {
1416 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1417 pch_alloc_dma_buf(board_dat, data);
1418 }
1419
1420 ret = spi_register_master(master);
1421 if (ret != 0) {
1422 dev_err(&plat_dev->dev,
1423 "%s spi_register_master FAILED\n", __func__);
1424 goto err_spi_register_master;
1425 }
1426
1427 return 0;
1428
1429 err_spi_register_master:
1430 pch_free_dma_buf(board_dat, data);
1431 free_irq(board_dat->pdev->irq, data);
1432 err_request_irq:
1433 pch_spi_free_resources(board_dat, data);
1434 err_spi_get_resources:
1435 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1436 err_pci_iomap:
1437 spi_master_put(master);
1438
1439 return ret;
1440 }
1441
1442 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1443 {
1444 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1445 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1446 int count;
1447 unsigned long flags;
1448
1449 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1450 __func__, plat_dev->id, board_dat->pdev->irq);
1451
1452 if (use_dma)
1453 pch_free_dma_buf(board_dat, data);
1454
1455 /* check for any pending messages; no action is taken if the queue
1456 * is still full; but at least we tried. Unload anyway */
1457 count = 500;
1458 spin_lock_irqsave(&data->lock, flags);
1459 data->status = STATUS_EXITING;
1460 while ((list_empty(&data->queue) == 0) && --count) {
1461 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1462 __func__);
1463 spin_unlock_irqrestore(&data->lock, flags);
1464 msleep(PCH_SLEEP_TIME);
1465 spin_lock_irqsave(&data->lock, flags);
1466 }
1467 spin_unlock_irqrestore(&data->lock, flags);
1468
1469 pch_spi_free_resources(board_dat, data);
1470 /* disable interrupts & free IRQ */
1471 if (data->irq_reg_sts) {
1472 /* disable interrupts */
1473 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1474 data->irq_reg_sts = false;
1475 free_irq(board_dat->pdev->irq, data);
1476 }
1477
1478 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1479 spi_unregister_master(data->master);
1480
1481 return 0;
1482 }
1483 #ifdef CONFIG_PM
1484 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1485 pm_message_t state)
1486 {
1487 u8 count;
1488 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1489 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1490
1491 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1492
1493 if (!board_dat) {
1494 dev_err(&pd_dev->dev,
1495 "%s pci_get_drvdata returned NULL\n", __func__);
1496 return -EFAULT;
1497 }
1498
1499 /* check if the current message is processed:
1500 Only after thats done the transfer will be suspended */
1501 count = 255;
1502 while ((--count) > 0) {
1503 if (!(data->bcurrent_msg_processing))
1504 break;
1505 msleep(PCH_SLEEP_TIME);
1506 }
1507
1508 /* Free IRQ */
1509 if (data->irq_reg_sts) {
1510 /* disable all interrupts */
1511 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1512 pch_spi_reset(data->master);
1513 free_irq(board_dat->pdev->irq, data);
1514
1515 data->irq_reg_sts = false;
1516 dev_dbg(&pd_dev->dev,
1517 "%s free_irq invoked successfully.\n", __func__);
1518 }
1519
1520 return 0;
1521 }
1522
1523 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1524 {
1525 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1526 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1527 int retval;
1528
1529 if (!board_dat) {
1530 dev_err(&pd_dev->dev,
1531 "%s pci_get_drvdata returned NULL\n", __func__);
1532 return -EFAULT;
1533 }
1534
1535 if (!data->irq_reg_sts) {
1536 /* register IRQ */
1537 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1538 IRQF_SHARED, KBUILD_MODNAME, data);
1539 if (retval < 0) {
1540 dev_err(&pd_dev->dev,
1541 "%s request_irq failed\n", __func__);
1542 return retval;
1543 }
1544
1545 /* reset PCH SPI h/w */
1546 pch_spi_reset(data->master);
1547 pch_spi_set_master_mode(data->master);
1548 data->irq_reg_sts = true;
1549 }
1550 return 0;
1551 }
1552 #else
1553 #define pch_spi_pd_suspend NULL
1554 #define pch_spi_pd_resume NULL
1555 #endif
1556
1557 static struct platform_driver pch_spi_pd_driver = {
1558 .driver = {
1559 .name = "pch-spi",
1560 },
1561 .probe = pch_spi_pd_probe,
1562 .remove = pch_spi_pd_remove,
1563 .suspend = pch_spi_pd_suspend,
1564 .resume = pch_spi_pd_resume
1565 };
1566
1567 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1568 {
1569 struct pch_spi_board_data *board_dat;
1570 struct platform_device *pd_dev = NULL;
1571 int retval;
1572 int i;
1573 struct pch_pd_dev_save *pd_dev_save;
1574
1575 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1576 if (!pd_dev_save)
1577 return -ENOMEM;
1578
1579 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1580 if (!board_dat) {
1581 retval = -ENOMEM;
1582 goto err_no_mem;
1583 }
1584
1585 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1586 if (retval) {
1587 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1588 goto pci_request_regions;
1589 }
1590
1591 board_dat->pdev = pdev;
1592 board_dat->num = id->driver_data;
1593 pd_dev_save->num = id->driver_data;
1594 pd_dev_save->board_dat = board_dat;
1595
1596 retval = pci_enable_device(pdev);
1597 if (retval) {
1598 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1599 goto pci_enable_device;
1600 }
1601
1602 for (i = 0; i < board_dat->num; i++) {
1603 pd_dev = platform_device_alloc("pch-spi", i);
1604 if (!pd_dev) {
1605 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1606 retval = -ENOMEM;
1607 goto err_platform_device;
1608 }
1609 pd_dev_save->pd_save[i] = pd_dev;
1610 pd_dev->dev.parent = &pdev->dev;
1611
1612 retval = platform_device_add_data(pd_dev, board_dat,
1613 sizeof(*board_dat));
1614 if (retval) {
1615 dev_err(&pdev->dev,
1616 "platform_device_add_data failed\n");
1617 platform_device_put(pd_dev);
1618 goto err_platform_device;
1619 }
1620
1621 retval = platform_device_add(pd_dev);
1622 if (retval) {
1623 dev_err(&pdev->dev, "platform_device_add failed\n");
1624 platform_device_put(pd_dev);
1625 goto err_platform_device;
1626 }
1627 }
1628
1629 pci_set_drvdata(pdev, pd_dev_save);
1630
1631 return 0;
1632
1633 err_platform_device:
1634 while (--i >= 0)
1635 platform_device_unregister(pd_dev_save->pd_save[i]);
1636 pci_disable_device(pdev);
1637 pci_enable_device:
1638 pci_release_regions(pdev);
1639 pci_request_regions:
1640 kfree(board_dat);
1641 err_no_mem:
1642 kfree(pd_dev_save);
1643
1644 return retval;
1645 }
1646
1647 static void pch_spi_remove(struct pci_dev *pdev)
1648 {
1649 int i;
1650 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1651
1652 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1653
1654 for (i = 0; i < pd_dev_save->num; i++)
1655 platform_device_unregister(pd_dev_save->pd_save[i]);
1656
1657 pci_disable_device(pdev);
1658 pci_release_regions(pdev);
1659 kfree(pd_dev_save->board_dat);
1660 kfree(pd_dev_save);
1661 }
1662
1663 #ifdef CONFIG_PM
1664 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1665 {
1666 int retval;
1667 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1668
1669 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1670
1671 pd_dev_save->board_dat->suspend_sts = true;
1672
1673 /* save config space */
1674 retval = pci_save_state(pdev);
1675 if (retval == 0) {
1676 pci_enable_wake(pdev, PCI_D3hot, 0);
1677 pci_disable_device(pdev);
1678 pci_set_power_state(pdev, PCI_D3hot);
1679 } else {
1680 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1681 }
1682
1683 return retval;
1684 }
1685
1686 static int pch_spi_resume(struct pci_dev *pdev)
1687 {
1688 int retval;
1689 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1690 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1691
1692 pci_set_power_state(pdev, PCI_D0);
1693 pci_restore_state(pdev);
1694
1695 retval = pci_enable_device(pdev);
1696 if (retval < 0) {
1697 dev_err(&pdev->dev,
1698 "%s pci_enable_device failed\n", __func__);
1699 } else {
1700 pci_enable_wake(pdev, PCI_D3hot, 0);
1701
1702 /* set suspend status to false */
1703 pd_dev_save->board_dat->suspend_sts = false;
1704 }
1705
1706 return retval;
1707 }
1708 #else
1709 #define pch_spi_suspend NULL
1710 #define pch_spi_resume NULL
1711
1712 #endif
1713
1714 static struct pci_driver pch_spi_pcidev_driver = {
1715 .name = "pch_spi",
1716 .id_table = pch_spi_pcidev_id,
1717 .probe = pch_spi_probe,
1718 .remove = pch_spi_remove,
1719 .suspend = pch_spi_suspend,
1720 .resume = pch_spi_resume,
1721 };
1722
1723 static int __init pch_spi_init(void)
1724 {
1725 int ret;
1726 ret = platform_driver_register(&pch_spi_pd_driver);
1727 if (ret)
1728 return ret;
1729
1730 ret = pci_register_driver(&pch_spi_pcidev_driver);
1731 if (ret) {
1732 platform_driver_unregister(&pch_spi_pd_driver);
1733 return ret;
1734 }
1735
1736 return 0;
1737 }
1738 module_init(pch_spi_init);
1739
1740 static void __exit pch_spi_exit(void)
1741 {
1742 pci_unregister_driver(&pch_spi_pcidev_driver);
1743 platform_driver_unregister(&pch_spi_pd_driver);
1744 }
1745 module_exit(pch_spi_exit);
1746
1747 module_param(use_dma, int, 0644);
1748 MODULE_PARM_DESC(use_dma,
1749 "to use DMA for data transfers pass 1 else 0; default 1");
1750
1751 MODULE_LICENSE("GPL");
1752 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1753 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1754
Linux with added FPC-III support