drivers/video/aty/atyfb.h

   1 /*
   2  *  ATI Frame Buffer Device Driver Core Definitions
   3  */
   4
   5 #include <linux/config.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/wait.h>
   8     /*
   9      *  Elements of the hardware specific atyfb_par structure
  10      */
  11
  12 struct crtc {
  13         u32 vxres;
  14         u32 vyres;
  15         u32 xoffset;
  16         u32 yoffset;
  17         u32 bpp;
  18         u32 h_tot_disp;
  19         u32 h_sync_strt_wid;
  20         u32 v_tot_disp;
  21         u32 v_sync_strt_wid;
  22         u32 vline_crnt_vline;
  23         u32 off_pitch;
  24         u32 gen_cntl;
  25         u32 dp_pix_width;       /* acceleration */
  26         u32 dp_chain_mask;      /* acceleration */
  27 #ifdef CONFIG_FB_ATY_GENERIC_LCD
  28         u32 horz_stretching;
  29         u32 vert_stretching;
  30         u32 ext_vert_stretch;
  31         u32 shadow_h_tot_disp;
  32         u32 shadow_h_sync_strt_wid;
  33         u32 shadow_v_tot_disp;
  34         u32 shadow_v_sync_strt_wid;
  35         u32 lcd_gen_cntl;
  36         u32 lcd_config_panel;
  37         u32 lcd_index;
  38 #endif
  39 };
  40
  41 struct aty_interrupt {
  42         wait_queue_head_t wait;
  43         unsigned int count;
  44         int pan_display;
  45 };
  46
  47 struct pll_info {
  48         int pll_max;
  49         int pll_min;
  50         int sclk, mclk, mclk_pm, xclk;
  51         int ref_div;
  52         int ref_clk;
  53         int ecp_max;
  54 };
  55
  56 typedef struct {
  57         u16 unknown1;
  58         u16 PCLK_min_freq;
  59         u16 PCLK_max_freq;
  60         u16 unknown2;
  61         u16 ref_freq;
  62         u16 ref_divider;
  63         u16 unknown3;
  64         u16 MCLK_pwd;
  65         u16 MCLK_max_freq;
  66         u16 XCLK_max_freq;
  67         u16 SCLK_freq;
  68 } __attribute__ ((packed)) PLL_BLOCK_MACH64;
  69
  70 struct pll_514 {
  71         u8 m;
  72         u8 n;
  73 };
  74
  75 struct pll_18818 {
  76         u32 program_bits;
  77         u32 locationAddr;
  78         u32 period_in_ps;
  79         u32 post_divider;
  80 };
  81
  82 struct pll_ct {
  83         u8 pll_ref_div;
  84         u8 pll_gen_cntl;
  85         u8 mclk_fb_div;
  86         u8 mclk_fb_mult; /* 2 ro 4 */
  87         u8 sclk_fb_div;
  88         u8 pll_vclk_cntl;
  89         u8 vclk_post_div;
  90         u8 vclk_fb_div;
  91         u8 pll_ext_cntl;
  92         u8 ext_vpll_cntl;
  93         u8 spll_cntl2;
  94         u32 dsp_config; /* Mach64 GTB DSP */
  95         u32 dsp_on_off; /* Mach64 GTB DSP */
  96         u32 dsp_loop_latency;
  97         u32 fifo_size;
  98         u32 xclkpagefaultdelay;
  99         u32 xclkmaxrasdelay;
 100         u8 xclk_ref_div;
 101         u8 xclk_post_div;
 102         u8 mclk_post_div_real;
 103         u8 xclk_post_div_real;
 104         u8 vclk_post_div_real;
 105         u8 features;
 106 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 107         u32 xres; /* use for LCD stretching/scaling */
 108 #endif
 109 };
 110
 111 /*
 112         for pll_ct.features
 113 */
 114 #define DONT_USE_SPLL 0x1
 115 #define DONT_USE_XDLL 0x2
 116 #define USE_CPUCLK    0x4
 117 #define POWERDOWN_PLL 0x8
 118
 119 union aty_pll {
 120         struct pll_ct ct;
 121         struct pll_514 ibm514;
 122         struct pll_18818 ics2595;
 123 };
 124
 125     /*
 126      *  The hardware parameters for each card
 127      */
 128
 129 struct atyfb_par {
 130         struct aty_cmap_regs __iomem *aty_cmap_regs;
 131         struct { u8 red, green, blue; } palette[256];
 132         const struct aty_dac_ops *dac_ops;
 133         const struct aty_pll_ops *pll_ops;
 134         void __iomem *ati_regbase;
 135         unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
 136         struct crtc crtc;
 137         union aty_pll pll;
 138         struct pll_info pll_limits;
 139         u32 features;
 140         u32 ref_clk_per;
 141         u32 pll_per;
 142         u32 mclk_per;
 143         u32 xclk_per;
 144         u8 bus_type;
 145         u8 ram_type;
 146         u8 mem_refresh_rate;
 147         u16 pci_id;
 148         u32 accel_flags;
 149         int blitter_may_be_busy;
 150         int asleep;
 151         int lock_blank;
 152         unsigned long res_start;
 153         unsigned long res_size;
 154 #ifdef __sparc__
 155         struct pci_mmap_map *mmap_map;
 156         u8 mmaped;
 157 #endif
 158         int open;
 159 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 160         unsigned long bios_base_phys;
 161         unsigned long bios_base;
 162         unsigned long lcd_table;
 163         u16 lcd_width;
 164         u16 lcd_height;
 165         u32 lcd_pixclock;
 166         u16 lcd_refreshrate;
 167         u16 lcd_htotal;
 168         u16 lcd_hdisp;
 169         u16 lcd_hsync_dly;
 170         u16 lcd_hsync_len;
 171         u16 lcd_vtotal;
 172         u16 lcd_vdisp;
 173         u16 lcd_vsync_len;
 174         u16 lcd_right_margin;
 175         u16 lcd_lower_margin;
 176         u16 lcd_hblank_len;
 177         u16 lcd_vblank_len;
 178 #endif
 179         unsigned long aux_start; /* auxiliary aperture */
 180         unsigned long aux_size;
 181         struct aty_interrupt vblank;
 182         unsigned long irq_flags;
 183         unsigned int irq;
 184         spinlock_t int_lock;
 185 #ifdef CONFIG_MTRR
 186         int mtrr_aper;
 187         int mtrr_reg;
 188 #endif
 189 };
 190
 191     /*
 192      *  ATI Mach64 features
 193      */
 194
 195 #define M64_HAS(feature)        ((par)->features & (M64F_##feature))
 196
 197 #define M64F_RESET_3D           0x00000001
 198 #define M64F_MAGIC_FIFO         0x00000002
 199 #define M64F_GTB_DSP            0x00000004
 200 #define M64F_FIFO_32            0x00000008
 201 #define M64F_SDRAM_MAGIC_PLL    0x00000010
 202 #define M64F_MAGIC_POSTDIV      0x00000020
 203 #define M64F_INTEGRATED         0x00000040
 204 #define M64F_CT_BUS             0x00000080
 205 #define M64F_VT_BUS             0x00000100
 206 #define M64F_MOBIL_BUS          0x00000200
 207 #define M64F_GX                 0x00000400
 208 #define M64F_CT                 0x00000800
 209 #define M64F_VT                 0x00001000
 210 #define M64F_GT                 0x00002000
 211 #define M64F_MAGIC_VRAM_SIZE    0x00004000
 212 #define M64F_G3_PB_1_1          0x00008000
 213 #define M64F_G3_PB_1024x768     0x00010000
 214 #define M64F_EXTRA_BRIGHT       0x00020000
 215 #define M64F_LT_LCD_REGS        0x00040000
 216 #define M64F_XL_DLL             0x00080000
 217 #define M64F_MFB_FORCE_4        0x00100000
 218 #define M64F_HW_TRIPLE          0x00200000
 219     /*
 220      *  Register access
 221      */
 222
 223 static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
 224 {
 225         /* Hack for bloc 1, should be cleanly optimized by compiler */
 226         if (regindex >= 0x400)
 227                 regindex -= 0x800;
 228
 229 #ifdef CONFIG_ATARI
 230         return in_le32((volatile u32 *)(par->ati_regbase + regindex));
 231 #else
 232         return readl(par->ati_regbase + regindex);
 233 #endif
 234 }
 235
 236 static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
 237 {
 238         /* Hack for bloc 1, should be cleanly optimized by compiler */
 239         if (regindex >= 0x400)
 240                 regindex -= 0x800;
 241
 242 #ifdef CONFIG_ATARI
 243         out_le32((volatile u32 *)(par->ati_regbase + regindex), val);
 244 #else
 245         writel(val, par->ati_regbase + regindex);
 246 #endif
 247 }
 248
 249 static inline void aty_st_le16(int regindex, u16 val,
 250                                const struct atyfb_par *par)
 251 {
 252         /* Hack for bloc 1, should be cleanly optimized by compiler */
 253         if (regindex >= 0x400)
 254                 regindex -= 0x800;
 255 #ifdef CONFIG_ATARI
 256         out_le16((volatile u16 *)(par->ati_regbase + regindex), val);
 257 #else
 258         writel(val, par->ati_regbase + regindex);
 259 #endif
 260 }
 261
 262 static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
 263 {
 264         /* Hack for bloc 1, should be cleanly optimized by compiler */
 265         if (regindex >= 0x400)
 266                 regindex -= 0x800;
 267 #ifdef CONFIG_ATARI
 268         return in_8(par->ati_regbase + regindex);
 269 #else
 270         return readb(par->ati_regbase + regindex);
 271 #endif
 272 }
 273
 274 static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
 275 {
 276         /* Hack for bloc 1, should be cleanly optimized by compiler */
 277         if (regindex >= 0x400)
 278                 regindex -= 0x800;
 279
 280 #ifdef CONFIG_ATARI
 281         out_8(par->ati_regbase + regindex, val);
 282 #else
 283         writeb(val, par->ati_regbase + regindex);
 284 #endif
 285 }
 286
 287 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 288 extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
 289 extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
 290 #endif
 291
 292     /*
 293      *  DAC operations
 294      */
 295
 296 struct aty_dac_ops {
 297         int (*set_dac) (const struct fb_info * info,
 298                 const union aty_pll * pll, u32 bpp, u32 accel);
 299 };
 300
 301 extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
 302 extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
 303 extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
 304 extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
 305 extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
 306
 307
 308     /*
 309      *  Clock operations
 310      */
 311
 312 struct aty_pll_ops {
 313         int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
 314         u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
 315         void (*set_pll)   (const struct fb_info * info, const union aty_pll * pll);
 316         void (*get_pll)   (const struct fb_info *info, union aty_pll * pll);
 317         int (*init_pll)   (const struct fb_info * info, union aty_pll * pll);
 318 };
 319
 320 extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
 321 extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
 322 extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
 323 extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
 324 extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
 325 extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
 326 extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
 327
 328
 329 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
 330 extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
 331
 332
 333     /*
 334      *  Hardware cursor support
 335      */
 336
 337 extern int aty_init_cursor(struct fb_info *info);
 338
 339     /*
 340      *  Hardware acceleration
 341      */
 342
 343 static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
 344 {
 345         while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
 346                ((u32) (0x8000 >> entries)));
 347 }
 348
 349 static inline void wait_for_idle(struct atyfb_par *par)
 350 {
 351         wait_for_fifo(16, par);
 352         while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
 353         par->blitter_may_be_busy = 0;
 354 }
 355
 356 extern void aty_reset_engine(const struct atyfb_par *par);
 357 extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
 358 extern void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par);
 359 extern u8   aty_ld_pll_ct(int offset, const struct atyfb_par *par);