include/asm-ppc/mpc10x.h

   1 /*
   2  * arch/ppc/kernel/mpc10x.h
   3  *
   4  * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
   5  * ctlr/EPIC/etc.
   6  *
   7  * Author: Mark A. Greer
   8  *         mgreer@mvista.com
   9  *
  10  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  11  * the terms of the GNU General Public License version 2.  This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15 #ifndef __PPC_KERNEL_MPC10X_H
  16 #define __PPC_KERNEL_MPC10X_H
  17
  18 #include <linux/pci_ids.h>
  19 #include <asm/pci-bridge.h>
  20
  21 /*
  22  * The values here don't completely map everything but should work in most
  23  * cases.
  24  *
  25  * MAP A (PReP Map)
  26  *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
  27  *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
  28  *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
  29  *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
  30  *
  31  * MAP B (CHRP Map)
  32  *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
  33  *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
  34  *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
  35  *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
  36  */
  37
  38 /*
  39  * Define the vendor/device IDs for the various bridges--should be added to
  40  * <linux/pci_ids.h>
  41  */
  42 #define MPC10X_BRIDGE_106       ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) |  \
  43                                   PCI_VENDOR_ID_MOTOROLA)
  44 #define MPC10X_BRIDGE_8240      ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
  45 #define MPC10X_BRIDGE_107       ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
  46 #define MPC10X_BRIDGE_8245      ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
  47
  48 /* Define the type of map to use */
  49 #define MPC10X_MEM_MAP_A                1
  50 #define MPC10X_MEM_MAP_B                2
  51
  52 /* Map A (PReP Map) Defines */
  53 #define MPC10X_MAPA_CNFG_ADDR           0x80000cf8
  54 #define MPC10X_MAPA_CNFG_DATA           0x80000cfc
  55
  56 #define MPC10X_MAPA_ISA_IO_BASE         0x80000000
  57 #define MPC10X_MAPA_ISA_MEM_BASE        0xc0000000
  58 #define MPC10X_MAPA_DRAM_OFFSET         0x80000000
  59
  60 #define MPC10X_MAPA_PCI_INTACK_ADDR     0xbffffff0
  61 #define MPC10X_MAPA_PCI_IO_START        0x00000000
  62 #define MPC10X_MAPA_PCI_IO_END         (0x00800000 - 1)
  63 #define MPC10X_MAPA_PCI_MEM_START       0x00000000
  64 #define MPC10X_MAPA_PCI_MEM_END        (0x20000000 - 1)
  65
  66 #define MPC10X_MAPA_PCI_MEM_OFFSET      (MPC10X_MAPA_ISA_MEM_BASE -     \
  67                                          MPC10X_MAPA_PCI_MEM_START)
  68
  69 /* Map B (CHRP Map) Defines */
  70 #define MPC10X_MAPB_CNFG_ADDR           0xfec00000
  71 #define MPC10X_MAPB_CNFG_DATA           0xfee00000
  72
  73 #define MPC10X_MAPB_ISA_IO_BASE         0xfe000000
  74 #define MPC10X_MAPB_ISA_MEM_BASE        0x80000000
  75 #define MPC10X_MAPB_DRAM_OFFSET         0x00000000
  76
  77 #define MPC10X_MAPB_PCI_INTACK_ADDR     0xfef00000
  78 #define MPC10X_MAPB_PCI_IO_START        0x00000000
  79 #define MPC10X_MAPB_PCI_IO_END         (0x00c00000 - 1)
  80 #define MPC10X_MAPB_PCI_MEM_START       0x80000000
  81 #define MPC10X_MAPB_PCI_MEM_END        (0xc0000000 - 1)
  82
  83 #define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
  84                                          MPC10X_MAPB_PCI_MEM_START)
  85
  86 /* Set hose members to values appropriate for the mem map used */
  87 #define MPC10X_SETUP_HOSE(hose, map) {                                  \
  88         (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;      \
  89         (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;        \
  90         (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;            \
  91         (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;      \
  92         (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;          \
  93         (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;   \
  94 }
  95
  96
  97 /* Miscellaneous Configuration register offsets */
  98 #define MPC10X_CFG_PIR_REG              0x09
  99 #define MPC10X_CFG_PIR_HOST_BRIDGE      0x00
 100 #define MPC10X_CFG_PIR_AGENT            0x01
 101
 102 #define MPC10X_CFG_EUMBBAR              0x78
 103
 104 #define MPC10X_CFG_PICR1_REG            0xa8
 105 #define MPC10X_CFG_PICR1_ADDR_MAP_MASK  0x00010000
 106 #define MPC10X_CFG_PICR1_ADDR_MAP_A     0x00010000
 107 #define MPC10X_CFG_PICR1_ADDR_MAP_B     0x00000000
 108 #define MPC10X_CFG_PICR1_SPEC_PCI_RD    0x00000004
 109 #define MPC10X_CFG_PICR1_ST_GATH_EN     0x00000040
 110
 111 #define MPC10X_CFG_PICR2_REG            0xac
 112 #define MPC10X_CFG_PICR2_COPYBACK_OPT   0x00000001
 113
 114 #define MPC10X_CFG_MAPB_OPTIONS_REG     0xe0
 115 #define MPC10X_CFG_MAPB_OPTIONS_CFAE    0x80    /* CPU_FD_ALIAS_EN */
 116 #define MPC10X_CFG_MAPB_OPTIONS_PFAE    0x40    /* PCI_FD_ALIAS_EN */
 117 #define MPC10X_CFG_MAPB_OPTIONS_DR      0x20    /* DLL_RESET */
 118 #define MPC10X_CFG_MAPB_OPTIONS_PCICH   0x08    /* PCI_COMPATIBILITY_HOLE */
 119 #define MPC10X_CFG_MAPB_OPTIONS_PROCCH  0x04    /* PROC_COMPATIBILITY_HOLE */
 120
 121 /* Define offsets for the memory controller registers in the config space */
 122 #define MPC10X_MCTLR_MEM_START_1        0x80    /* Banks 0-3 */
 123 #define MPC10X_MCTLR_MEM_START_2        0x84    /* Banks 4-7 */
 124 #define MPC10X_MCTLR_EXT_MEM_START_1    0x88    /* Banks 0-3 */
 125 #define MPC10X_MCTLR_EXT_MEM_START_2    0x8c    /* Banks 4-7 */
 126
 127 #define MPC10X_MCTLR_MEM_END_1          0x90    /* Banks 0-3 */
 128 #define MPC10X_MCTLR_MEM_END_2          0x94    /* Banks 4-7 */
 129 #define MPC10X_MCTLR_EXT_MEM_END_1      0x98    /* Banks 0-3 */
 130 #define MPC10X_MCTLR_EXT_MEM_END_2      0x9c    /* Banks 4-7 */
 131
 132 #define MPC10X_MCTLR_MEM_BANK_ENABLES   0xa0
 133
 134 /* Define some offset in the EUMB */
 135 #define MPC10X_EUMB_SIZE                0x00100000 /* Total EUMB size (1MB) */
 136
 137 #define MPC10X_EUMB_MU_OFFSET           0x00000000 /* Msg Unit reg offset */
 138 #define MPC10X_EUMB_MU_SIZE             0x00001000 /* Msg Unit reg size */
 139 #define MPC10X_EUMB_DMA_OFFSET          0x00001000 /* DMA Unit reg offset */
 140 #define MPC10X_EUMB_DMA_SIZE            0x00001000 /* DMA Unit reg size  */
 141 #define MPC10X_EUMB_ATU_OFFSET          0x00002000 /* Addr xlate reg offset */
 142 #define MPC10X_EUMB_ATU_SIZE            0x00001000 /* Addr xlate reg size  */
 143 #define MPC10X_EUMB_I2C_OFFSET          0x00003000 /* I2C Unit reg offset */
 144 #define MPC10X_EUMB_I2C_SIZE            0x00001000 /* I2C Unit reg size  */
 145 #define MPC10X_EUMB_DUART_OFFSET        0x00004000 /* DUART Unit reg offset (8245) */
 146 #define MPC10X_EUMB_DUART_SIZE          0x00001000 /* DUART Unit reg size (8245) */
 147 #define MPC10X_EUMB_EPIC_OFFSET         0x00040000 /* EPIC offset in EUMB */
 148 #define MPC10X_EUMB_EPIC_SIZE           0x00030000 /* EPIC size */
 149 #define MPC10X_EUMB_PM_OFFSET           0x000fe000 /* Performance Monitor reg offset (8245) */
 150 #define MPC10X_EUMB_PM_SIZE             0x00001000 /* Performance Monitor reg size (8245) */
 151 #define MPC10X_EUMB_WP_OFFSET           0x000ff000 /* Data path diagnostic, watchpoint reg offset */
 152 #define MPC10X_EUMB_WP_SIZE             0x00001000 /* Data path diagnostic, watchpoint reg size */
 153
 154 /*
 155  * Define some recommended places to put the EUMB regs.
 156  * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
 157  */
 158 extern unsigned long                    ioremap_base;
 159 #define MPC10X_MAPA_EUMB_BASE           (ioremap_base - MPC10X_EUMB_SIZE)
 160 #define MPC10X_MAPB_EUMB_BASE           MPC10X_MAPA_EUMB_BASE
 161
 162 enum ppc_sys_devices {
 163         MPC10X_IIC1,
 164         MPC10X_DMA0,
 165         MPC10X_DMA1,
 166         MPC10X_UART0,
 167         MPC10X_UART1,
 168 };
 169
 170 int mpc10x_bridge_init(struct pci_controller *hose,
 171                        uint current_map,
 172                        uint new_map,
 173                        uint phys_eumb_base);
 174 unsigned long mpc10x_get_mem_size(uint mem_map);
 175 int mpc10x_enable_store_gathering(struct pci_controller *hose);
 176 int mpc10x_disable_store_gathering(struct pci_controller *hose);
 177
 178 /* For MPC107 boards that use the built-in openpic */
 179 void mpc10x_set_openpic(void);
 180
 181 #endif  /* __PPC_KERNEL_MPC10X_H */