Merge tag 'locking-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel...
[linux/fpc-iii.git] / arch / powerpc / mm / pgtable.c
blob9c0547d77af3599847849625c565299b3562d561
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * This file contains common routines for dealing with free of page tables
4 * Along with common page table handling code
6 * Derived from arch/powerpc/mm/tlb_64.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 * Dave Engebretsen <engebret@us.ibm.com>
17 * Rework for PPC64 port.
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
22 #include <linux/mm.h>
23 #include <linux/percpu.h>
24 #include <linux/hardirq.h>
25 #include <linux/hugetlb.h>
26 #include <asm/tlbflush.h>
27 #include <asm/tlb.h>
28 #include <asm/hugetlb.h>
30 static inline int is_exec_fault(void)
32 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
35 /* We only try to do i/d cache coherency on stuff that looks like
36 * reasonably "normal" PTEs. We currently require a PTE to be present
37 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
38 * on userspace PTEs
40 static inline int pte_looks_normal(pte_t pte)
43 if (pte_present(pte) && !pte_special(pte)) {
44 if (pte_ci(pte))
45 return 0;
46 if (pte_user(pte))
47 return 1;
49 return 0;
52 static struct page *maybe_pte_to_page(pte_t pte)
54 unsigned long pfn = pte_pfn(pte);
55 struct page *page;
57 if (unlikely(!pfn_valid(pfn)))
58 return NULL;
59 page = pfn_to_page(pfn);
60 if (PageReserved(page))
61 return NULL;
62 return page;
65 #ifdef CONFIG_PPC_BOOK3S
67 /* Server-style MMU handles coherency when hashing if HW exec permission
68 * is supposed per page (currently 64-bit only). If not, then, we always
69 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
70 * support falls into the same category.
73 static pte_t set_pte_filter_hash(pte_t pte)
75 if (radix_enabled())
76 return pte;
78 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
79 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
80 cpu_has_feature(CPU_FTR_NOEXECUTE))) {
81 struct page *pg = maybe_pte_to_page(pte);
82 if (!pg)
83 return pte;
84 if (!test_bit(PG_arch_1, &pg->flags)) {
85 flush_dcache_icache_page(pg);
86 set_bit(PG_arch_1, &pg->flags);
89 return pte;
92 #else /* CONFIG_PPC_BOOK3S */
94 static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
96 #endif /* CONFIG_PPC_BOOK3S */
98 /* Embedded type MMU with HW exec support. This is a bit more complicated
99 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
100 * instead we "filter out" the exec permission for non clean pages.
102 static inline pte_t set_pte_filter(pte_t pte)
104 struct page *pg;
106 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
107 return set_pte_filter_hash(pte);
109 /* No exec permission in the first place, move on */
110 if (!pte_exec(pte) || !pte_looks_normal(pte))
111 return pte;
113 /* If you set _PAGE_EXEC on weird pages you're on your own */
114 pg = maybe_pte_to_page(pte);
115 if (unlikely(!pg))
116 return pte;
118 /* If the page clean, we move on */
119 if (test_bit(PG_arch_1, &pg->flags))
120 return pte;
122 /* If it's an exec fault, we flush the cache and make it clean */
123 if (is_exec_fault()) {
124 flush_dcache_icache_page(pg);
125 set_bit(PG_arch_1, &pg->flags);
126 return pte;
129 /* Else, we filter out _PAGE_EXEC */
130 return pte_exprotect(pte);
133 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
134 int dirty)
136 struct page *pg;
138 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
139 return pte;
141 /* So here, we only care about exec faults, as we use them
142 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
143 * if necessary. Also if _PAGE_EXEC is already set, same deal,
144 * we just bail out
146 if (dirty || pte_exec(pte) || !is_exec_fault())
147 return pte;
149 #ifdef CONFIG_DEBUG_VM
150 /* So this is an exec fault, _PAGE_EXEC is not set. If it was
151 * an error we would have bailed out earlier in do_page_fault()
152 * but let's make sure of it
154 if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
155 return pte;
156 #endif /* CONFIG_DEBUG_VM */
158 /* If you set _PAGE_EXEC on weird pages you're on your own */
159 pg = maybe_pte_to_page(pte);
160 if (unlikely(!pg))
161 goto bail;
163 /* If the page is already clean, we move on */
164 if (test_bit(PG_arch_1, &pg->flags))
165 goto bail;
167 /* Clean the page and set PG_arch_1 */
168 flush_dcache_icache_page(pg);
169 set_bit(PG_arch_1, &pg->flags);
171 bail:
172 return pte_mkexec(pte);
176 * set_pte stores a linux PTE into the linux page table.
178 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
179 pte_t pte)
182 * Make sure hardware valid bit is not set. We don't do
183 * tlb flush for this update.
185 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
187 /* Add the pte bit when trying to set a pte */
188 pte = pte_mkpte(pte);
190 /* Note: mm->context.id might not yet have been assigned as
191 * this context might not have been activated yet when this
192 * is called.
194 pte = set_pte_filter(pte);
196 /* Perform the setting of the PTE */
197 __set_pte_at(mm, addr, ptep, pte, 0);
201 * This is called when relaxing access to a PTE. It's also called in the page
202 * fault path when we don't hit any of the major fault cases, ie, a minor
203 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
204 * handled those two for us, we additionally deal with missing execute
205 * permission here on some processors
207 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
208 pte_t *ptep, pte_t entry, int dirty)
210 int changed;
211 entry = set_access_flags_filter(entry, vma, dirty);
212 changed = !pte_same(*(ptep), entry);
213 if (changed) {
214 assert_pte_locked(vma->vm_mm, address);
215 __ptep_set_access_flags(vma, ptep, entry,
216 address, mmu_virtual_psize);
218 return changed;
221 #ifdef CONFIG_HUGETLB_PAGE
222 int huge_ptep_set_access_flags(struct vm_area_struct *vma,
223 unsigned long addr, pte_t *ptep,
224 pte_t pte, int dirty)
226 #ifdef HUGETLB_NEED_PRELOAD
228 * The "return 1" forces a call of update_mmu_cache, which will write a
229 * TLB entry. Without this, platforms that don't do a write of the TLB
230 * entry in the TLB miss handler asm will fault ad infinitum.
232 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
233 return 1;
234 #else
235 int changed, psize;
237 pte = set_access_flags_filter(pte, vma, dirty);
238 changed = !pte_same(*(ptep), pte);
239 if (changed) {
241 #ifdef CONFIG_PPC_BOOK3S_64
242 struct hstate *h = hstate_vma(vma);
244 psize = hstate_get_psize(h);
245 #ifdef CONFIG_DEBUG_VM
246 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
247 #endif
249 #else
251 * Not used on non book3s64 platforms.
252 * 8xx compares it with mmu_virtual_psize to
253 * know if it is a huge page or not.
255 psize = MMU_PAGE_COUNT;
256 #endif
257 __ptep_set_access_flags(vma, ptep, pte, addr, psize);
259 return changed;
260 #endif
263 #if defined(CONFIG_PPC_8xx)
264 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
266 pmd_t *pmd = pmd_off(mm, addr);
267 pte_basic_t val;
268 pte_basic_t *entry = &ptep->pte;
269 int num = is_hugepd(*((hugepd_t *)pmd)) ? 1 : SZ_512K / SZ_4K;
270 int i;
273 * Make sure hardware valid bit is not set. We don't do
274 * tlb flush for this update.
276 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
278 pte = pte_mkpte(pte);
280 pte = set_pte_filter(pte);
282 val = pte_val(pte);
283 for (i = 0; i < num; i++, entry++, val += SZ_4K)
284 *entry = val;
286 #endif
287 #endif /* CONFIG_HUGETLB_PAGE */
289 #ifdef CONFIG_DEBUG_VM
290 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
292 pgd_t *pgd;
293 p4d_t *p4d;
294 pud_t *pud;
295 pmd_t *pmd;
297 if (mm == &init_mm)
298 return;
299 pgd = mm->pgd + pgd_index(addr);
300 BUG_ON(pgd_none(*pgd));
301 p4d = p4d_offset(pgd, addr);
302 BUG_ON(p4d_none(*p4d));
303 pud = pud_offset(p4d, addr);
304 BUG_ON(pud_none(*pud));
305 pmd = pmd_offset(pud, addr);
307 * khugepaged to collapse normal pages to hugepage, first set
308 * pmd to none to force page fault/gup to take mmap_lock. After
309 * pmd is set to none, we do a pte_clear which does this assertion
310 * so if we find pmd none, return.
312 if (pmd_none(*pmd))
313 return;
314 BUG_ON(!pmd_present(*pmd));
315 assert_spin_locked(pte_lockptr(mm, pmd));
317 #endif /* CONFIG_DEBUG_VM */
319 unsigned long vmalloc_to_phys(void *va)
321 unsigned long pfn = vmalloc_to_pfn(va);
323 BUG_ON(!pfn);
324 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
326 EXPORT_SYMBOL_GPL(vmalloc_to_phys);
329 * We have 4 cases for pgds and pmds:
330 * (1) invalid (all zeroes)
331 * (2) pointer to next table, as normal; bottom 6 bits == 0
332 * (3) leaf pte for huge page _PAGE_PTE set
333 * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
335 * So long as we atomically load page table pointers we are safe against teardown,
336 * we can follow the address down to the the page and take a ref on it.
337 * This function need to be called with interrupts disabled. We use this variant
338 * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
340 pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
341 bool *is_thp, unsigned *hpage_shift)
343 pgd_t *pgdp;
344 p4d_t p4d, *p4dp;
345 pud_t pud, *pudp;
346 pmd_t pmd, *pmdp;
347 pte_t *ret_pte;
348 hugepd_t *hpdp = NULL;
349 unsigned pdshift;
351 if (hpage_shift)
352 *hpage_shift = 0;
354 if (is_thp)
355 *is_thp = false;
358 * Always operate on the local stack value. This make sure the
359 * value don't get updated by a parallel THP split/collapse,
360 * page fault or a page unmap. The return pte_t * is still not
361 * stable. So should be checked there for above conditions.
362 * Top level is an exception because it is folded into p4d.
364 pgdp = pgdir + pgd_index(ea);
365 p4dp = p4d_offset(pgdp, ea);
366 p4d = READ_ONCE(*p4dp);
367 pdshift = P4D_SHIFT;
369 if (p4d_none(p4d))
370 return NULL;
372 if (p4d_is_leaf(p4d)) {
373 ret_pte = (pte_t *)p4dp;
374 goto out;
377 if (is_hugepd(__hugepd(p4d_val(p4d)))) {
378 hpdp = (hugepd_t *)&p4d;
379 goto out_huge;
383 * Even if we end up with an unmap, the pgtable will not
384 * be freed, because we do an rcu free and here we are
385 * irq disabled
387 pdshift = PUD_SHIFT;
388 pudp = pud_offset(&p4d, ea);
389 pud = READ_ONCE(*pudp);
391 if (pud_none(pud))
392 return NULL;
394 if (pud_is_leaf(pud)) {
395 ret_pte = (pte_t *)pudp;
396 goto out;
399 if (is_hugepd(__hugepd(pud_val(pud)))) {
400 hpdp = (hugepd_t *)&pud;
401 goto out_huge;
404 pdshift = PMD_SHIFT;
405 pmdp = pmd_offset(&pud, ea);
406 pmd = READ_ONCE(*pmdp);
409 * A hugepage collapse is captured by this condition, see
410 * pmdp_collapse_flush.
412 if (pmd_none(pmd))
413 return NULL;
415 #ifdef CONFIG_PPC_BOOK3S_64
417 * A hugepage split is captured by this condition, see
418 * pmdp_invalidate.
420 * Huge page modification can be caught here too.
422 if (pmd_is_serializing(pmd))
423 return NULL;
424 #endif
426 if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
427 if (is_thp)
428 *is_thp = true;
429 ret_pte = (pte_t *)pmdp;
430 goto out;
433 if (pmd_is_leaf(pmd)) {
434 ret_pte = (pte_t *)pmdp;
435 goto out;
438 if (is_hugepd(__hugepd(pmd_val(pmd)))) {
439 hpdp = (hugepd_t *)&pmd;
440 goto out_huge;
443 return pte_offset_kernel(&pmd, ea);
445 out_huge:
446 if (!hpdp)
447 return NULL;
449 ret_pte = hugepte_offset(*hpdp, ea, pdshift);
450 pdshift = hugepd_shift(*hpdp);
451 out:
452 if (hpage_shift)
453 *hpage_shift = pdshift;
454 return ret_pte;
456 EXPORT_SYMBOL_GPL(__find_linux_pte);