arch/powerpc/perf/isa207-common.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2009 Paul Mackerras, IBM Corporation.
   4  * Copyright 2013 Michael Ellerman, IBM Corporation.
   5  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
   6  */
   7
   8 #ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_
   9 #define _LINUX_POWERPC_PERF_ISA207_COMMON_H_
  10
  11 #include <linux/kernel.h>
  12 #include <linux/perf_event.h>
  13 #include <asm/firmware.h>
  14 #include <asm/cputable.h>
  15
  16 #define EVENT_EBB_MASK          1ull
  17 #define EVENT_EBB_SHIFT         PERF_EVENT_CONFIG_EBB_SHIFT
  18 #define EVENT_BHRB_MASK         1ull
  19 #define EVENT_BHRB_SHIFT        62
  20 #define EVENT_WANTS_BHRB        (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
  21 #define EVENT_IFM_MASK          3ull
  22 #define EVENT_IFM_SHIFT         60
  23 #define EVENT_THR_CMP_SHIFT     40      /* Threshold CMP value */
  24 #define EVENT_THR_CMP_MASK      0x3ff
  25 #define EVENT_THR_CTL_SHIFT     32      /* Threshold control value (start/stop) */
  26 #define EVENT_THR_CTL_MASK      0xffull
  27 #define EVENT_THR_SEL_SHIFT     29      /* Threshold select value */
  28 #define EVENT_THR_SEL_MASK      0x7
  29 #define EVENT_THRESH_SHIFT      29      /* All threshold bits */
  30 #define EVENT_THRESH_MASK       0x1fffffull
  31 #define EVENT_SAMPLE_SHIFT      24      /* Sampling mode & eligibility */
  32 #define EVENT_SAMPLE_MASK       0x1f
  33 #define EVENT_CACHE_SEL_SHIFT   20      /* L2/L3 cache select */
  34 #define EVENT_CACHE_SEL_MASK    0xf
  35 #define EVENT_IS_L1             (4 << EVENT_CACHE_SEL_SHIFT)
  36 #define EVENT_PMC_SHIFT         16      /* PMC number (1-based) */
  37 #define EVENT_PMC_MASK          0xf
  38 #define EVENT_UNIT_SHIFT        12      /* Unit */
  39 #define EVENT_UNIT_MASK         0xf
  40 #define EVENT_COMBINE_SHIFT     11      /* Combine bit */
  41 #define EVENT_COMBINE_MASK      0x1
  42 #define EVENT_COMBINE(v)        (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)
  43 #define EVENT_MARKED_SHIFT      8       /* Marked bit */
  44 #define EVENT_MARKED_MASK       0x1
  45 #define EVENT_IS_MARKED         (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
  46 #define EVENT_PSEL_MASK         0xff    /* PMCxSEL value */
  47
  48 /* Bits defined by Linux */
  49 #define EVENT_LINUX_MASK        \
  50         ((EVENT_EBB_MASK  << EVENT_EBB_SHIFT)                   |       \
  51          (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)                  |       \
  52          (EVENT_IFM_MASK  << EVENT_IFM_SHIFT))
  53
  54 #define EVENT_VALID_MASK        \
  55         ((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)           |       \
  56          (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)           |       \
  57          (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)        |       \
  58          (EVENT_PMC_MASK       << EVENT_PMC_SHIFT)              |       \
  59          (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)             |       \
  60          (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)          |       \
  61          (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)           |       \
  62           EVENT_LINUX_MASK                                      |       \
  63           EVENT_PSEL_MASK)
  64
  65 #define ONLY_PLM \
  66         (PERF_SAMPLE_BRANCH_USER        |\
  67          PERF_SAMPLE_BRANCH_KERNEL      |\
  68          PERF_SAMPLE_BRANCH_HV)
  69
  70 /* Contants to support power9 raw encoding format */
  71 #define p9_EVENT_COMBINE_SHIFT  10      /* Combine bit */
  72 #define p9_EVENT_COMBINE_MASK   0x3ull
  73 #define p9_EVENT_COMBINE(v)     (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)
  74 #define p9_SDAR_MODE_SHIFT      50
  75 #define p9_SDAR_MODE_MASK       0x3ull
  76 #define p9_SDAR_MODE(v)         (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)
  77
  78 #define p9_EVENT_VALID_MASK             \
  79         ((p9_SDAR_MODE_MASK   << p9_SDAR_MODE_SHIFT             |       \
  80         (EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)            |       \
  81         (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)            |       \
  82         (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)         |       \
  83         (EVENT_PMC_MASK       << EVENT_PMC_SHIFT)               |       \
  84         (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)              |       \
  85         (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)       |       \
  86         (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)            |       \
  87          EVENT_LINUX_MASK                                       |       \
  88          EVENT_PSEL_MASK))
  89
  90 /* Contants to support power10 raw encoding format */
  91 #define p10_SDAR_MODE_SHIFT             22
  92 #define p10_SDAR_MODE_MASK              0x3ull
  93 #define p10_SDAR_MODE(v)                (((v) >> p10_SDAR_MODE_SHIFT) & \
  94                                         p10_SDAR_MODE_MASK)
  95 #define p10_EVENT_L2L3_SEL_MASK         0x1f
  96 #define p10_L2L3_SEL_SHIFT              3
  97 #define p10_L2L3_EVENT_SHIFT            40
  98 #define p10_EVENT_THRESH_MASK           0xffffull
  99 #define p10_EVENT_CACHE_SEL_MASK        0x3ull
 100 #define p10_EVENT_MMCR3_MASK            0x7fffull
 101 #define p10_EVENT_MMCR3_SHIFT           45
 102
 103 #define p10_EVENT_VALID_MASK            \
 104         ((p10_SDAR_MODE_MASK   << p10_SDAR_MODE_SHIFT           |       \
 105         (p10_EVENT_THRESH_MASK  << EVENT_THRESH_SHIFT)          |       \
 106         (EVENT_SAMPLE_MASK     << EVENT_SAMPLE_SHIFT)           |       \
 107         (p10_EVENT_CACHE_SEL_MASK  << EVENT_CACHE_SEL_SHIFT)    |       \
 108         (EVENT_PMC_MASK        << EVENT_PMC_SHIFT)              |       \
 109         (EVENT_UNIT_MASK       << EVENT_UNIT_SHIFT)             |       \
 110         (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)       |       \
 111         (p10_EVENT_MMCR3_MASK  << p10_EVENT_MMCR3_SHIFT)        |       \
 112         (EVENT_MARKED_MASK     << EVENT_MARKED_SHIFT)           |       \
 113          EVENT_LINUX_MASK                                       |       \
 114         EVENT_PSEL_MASK))
 115 /*
 116  * Layout of constraint bits:
 117  *
 118  *        60        56        52        48        44        40        36        32
 119  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 120  *   [   fab_match   ]         [       thresh_cmp      ] [   thresh_ctl    ] [   ]
 121  *                                                                             |
 122  *                                                                 thresh_sel -*
 123  *
 124  *        28        24        20        16        12         8         4         0
 125  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 126  *               [ ] |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
 127  *                |  |    |                     |
 128  *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
 129  *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
 130  *      L1 I/D qualifier -*                     |
 131  *                     nc - number of counters -*
 132  *
 133  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
 134  * we want the low bit of each field to be added to any existing value.
 135  *
 136  * Everything else is a value field.
 137  */
 138
 139 #define CNST_FAB_MATCH_VAL(v)   (((v) & EVENT_THR_CTL_MASK) << 56)
 140 #define CNST_FAB_MATCH_MASK     CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
 141
 142 /* We just throw all the threshold bits into the constraint */
 143 #define CNST_THRESH_VAL(v)      (((v) & EVENT_THRESH_MASK) << 32)
 144 #define CNST_THRESH_MASK        CNST_THRESH_VAL(EVENT_THRESH_MASK)
 145
 146 #define CNST_EBB_VAL(v)         (((v) & EVENT_EBB_MASK) << 24)
 147 #define CNST_EBB_MASK           CNST_EBB_VAL(EVENT_EBB_MASK)
 148
 149 #define CNST_IFM_VAL(v)         (((v) & EVENT_IFM_MASK) << 25)
 150 #define CNST_IFM_MASK           CNST_IFM_VAL(EVENT_IFM_MASK)
 151
 152 #define CNST_L1_QUAL_VAL(v)     (((v) & 3) << 22)
 153 #define CNST_L1_QUAL_MASK       CNST_L1_QUAL_VAL(3)
 154
 155 #define CNST_SAMPLE_VAL(v)      (((v) & EVENT_SAMPLE_MASK) << 16)
 156 #define CNST_SAMPLE_MASK        CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
 157
 158 #define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55)
 159 #define CNST_CACHE_GROUP_MASK   CNST_CACHE_GROUP_VAL(0xff)
 160 #define CNST_CACHE_PMC4_VAL     (1ull << 54)
 161 #define CNST_CACHE_PMC4_MASK    CNST_CACHE_PMC4_VAL
 162
 163 #define CNST_L2L3_GROUP_VAL(v)  (((v) & 0x1full) << 55)
 164 #define CNST_L2L3_GROUP_MASK    CNST_L2L3_GROUP_VAL(0x1f)
 165
 166 /*
 167  * For NC we are counting up to 4 events. This requires three bits, and we need
 168  * the fifth event to overflow and set the 4th bit. To achieve that we bias the
 169  * fields by 3 in test_adder.
 170  */
 171 #define CNST_NC_SHIFT           12
 172 #define CNST_NC_VAL             (1 << CNST_NC_SHIFT)
 173 #define CNST_NC_MASK            (8 << CNST_NC_SHIFT)
 174 #define ISA207_TEST_ADDER       (3 << CNST_NC_SHIFT)
 175
 176 /*
 177  * For the per-PMC fields we have two bits. The low bit is added, so if two
 178  * events ask for the same PMC the sum will overflow, setting the high bit,
 179  * indicating an error. So our mask sets the high bit.
 180  */
 181 #define CNST_PMC_SHIFT(pmc)     ((pmc - 1) * 2)
 182 #define CNST_PMC_VAL(pmc)       (1 << CNST_PMC_SHIFT(pmc))
 183 #define CNST_PMC_MASK(pmc)      (2 << CNST_PMC_SHIFT(pmc))
 184
 185 /* Our add_fields is defined as: */
 186 #define ISA207_ADD_FIELDS       \
 187         CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
 188         CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
 189
 190 /* Bits in MMCR1 for PowerISA v2.07 */
 191 #define MMCR1_UNIT_SHIFT(pmc)           (60 - (4 * ((pmc) - 1)))
 192 #define MMCR1_COMBINE_SHIFT(pmc)        (35 - ((pmc) - 1))
 193 #define MMCR1_PMCSEL_SHIFT(pmc)         (24 - (((pmc) - 1)) * 8)
 194 #define MMCR1_FAB_SHIFT                 36
 195 #define MMCR1_DC_IC_QUAL_MASK           0x3
 196 #define MMCR1_DC_IC_QUAL_SHIFT          46
 197
 198 /* MMCR1 Combine bits macro for power9 */
 199 #define p9_MMCR1_COMBINE_SHIFT(pmc)     (38 - ((pmc - 1) * 2))
 200
 201 /* Bits in MMCRA for PowerISA v2.07 */
 202 #define MMCRA_SAMP_MODE_SHIFT           1
 203 #define MMCRA_SAMP_ELIG_SHIFT           4
 204 #define MMCRA_THR_CTL_SHIFT             8
 205 #define MMCRA_THR_SEL_SHIFT             16
 206 #define MMCRA_THR_CMP_SHIFT             32
 207 #define MMCRA_SDAR_MODE_SHIFT           42
 208 #define MMCRA_SDAR_MODE_TLB             (1ull << MMCRA_SDAR_MODE_SHIFT)
 209 #define MMCRA_SDAR_MODE_NO_UPDATES      ~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
 210 #define MMCRA_SDAR_MODE_DCACHE          (2ull << MMCRA_SDAR_MODE_SHIFT)
 211 #define MMCRA_IFM_SHIFT                 30
 212 #define MMCRA_THR_CTR_MANT_SHIFT        19
 213 #define MMCRA_THR_CTR_MANT_MASK         0x7Ful
 214 #define MMCRA_THR_CTR_MANT(v)           (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
 215                                                 MMCRA_THR_CTR_MANT_MASK)
 216
 217 #define MMCRA_THR_CTR_EXP_SHIFT         27
 218 #define MMCRA_THR_CTR_EXP_MASK          0x7ul
 219 #define MMCRA_THR_CTR_EXP(v)            (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
 220                                                 MMCRA_THR_CTR_EXP_MASK)
 221
 222 /* MMCRA Threshold Compare bit constant for power9 */
 223 #define p9_MMCRA_THR_CMP_SHIFT  45
 224
 225 /* Bits in MMCR2 for PowerISA v2.07 */
 226 #define MMCR2_FCS(pmc)                  (1ull << (63 - (((pmc) - 1) * 9)))
 227 #define MMCR2_FCP(pmc)                  (1ull << (62 - (((pmc) - 1) * 9)))
 228 #define MMCR2_FCH(pmc)                  (1ull << (57 - (((pmc) - 1) * 9)))
 229
 230 #define MAX_ALT                         2
 231 #define MAX_PMU_COUNTERS                6
 232
 233 /* Bits in MMCR3 for PowerISA v3.10 */
 234 #define MMCR3_SHIFT(pmc)                (49 - (15 * ((pmc) - 1)))
 235
 236 #define ISA207_SIER_TYPE_SHIFT          15
 237 #define ISA207_SIER_TYPE_MASK           (0x7ull << ISA207_SIER_TYPE_SHIFT)
 238
 239 #define ISA207_SIER_LDST_SHIFT          1
 240 #define ISA207_SIER_LDST_MASK           (0x7ull << ISA207_SIER_LDST_SHIFT)
 241
 242 #define ISA207_SIER_DATA_SRC_SHIFT      53
 243 #define ISA207_SIER_DATA_SRC_MASK       (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
 244
 245 #define P(a, b)                         PERF_MEM_S(a, b)
 246 #define PH(a, b)                        (P(LVL, HIT) | P(a, b))
 247 #define PM(a, b)                        (P(LVL, MISS) | P(a, b))
 248
 249 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
 250 int isa207_compute_mmcr(u64 event[], int n_ev,
 251                                 unsigned int hwc[], struct mmcr_regs *mmcr,
 252                                 struct perf_event *pevents[]);
 253 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
 254 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
 255                                         const unsigned int ev_alt[][MAX_ALT]);
 256 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
 257                                                         struct pt_regs *regs);
 258 void isa207_get_mem_weight(u64 *weight);
 259
 260 #endif