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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / arch / mips / include / asm / kvm_host.h
blob6ded8d347af966da7693529050d7c95bf739b182
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
25
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
28
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
56
57
58 #define KVM_MAX_VCPUS 1
59 #define KVM_USER_MEM_SLOTS 8
60 /* memory slots that does not exposed to userspace */
61 #define KVM_PRIVATE_MEM_SLOTS 0
62
63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 #define KVM_HALT_POLL_NS_DEFAULT 500000
65
66
67
68 /* Special address that contains the comm page, used for reducing # of traps */
69 #define KVM_GUEST_COMMPAGE_ADDR 0x0
70
71 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
73
74 #define KVM_GUEST_KUSEG 0x00000000UL
75 #define KVM_GUEST_KSEG0 0x40000000UL
76 #define KVM_GUEST_KSEG23 0x60000000UL
77 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
78 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
79
80 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
81 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
82 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
83
84 /*
85 * Map an address to a certain kernel segment
86 */
87 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
88 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
89 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
90
91 #define KVM_INVALID_PAGE 0xdeadbeef
92 #define KVM_INVALID_INST 0xdeadbeef
93 #define KVM_INVALID_ADDR 0xdeadbeef
94
95 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
96
97 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
98 #define MS_TO_NS(x) (x * 1E6L)
99
100 #define CAUSEB_DC 27
101 #define CAUSEF_DC (_ULCAST_(1) << 27)
102
103 extern atomic_t kvm_mips_instance;
104 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
105 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
106 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
107
108 struct kvm_vm_stat {
109 u32 remote_tlb_flush;
110 };
111
112 struct kvm_vcpu_stat {
113 u32 wait_exits;
114 u32 cache_exits;
115 u32 signal_exits;
116 u32 int_exits;
117 u32 cop_unusable_exits;
118 u32 tlbmod_exits;
119 u32 tlbmiss_ld_exits;
120 u32 tlbmiss_st_exits;
121 u32 addrerr_st_exits;
122 u32 addrerr_ld_exits;
123 u32 syscall_exits;
124 u32 resvd_inst_exits;
125 u32 break_inst_exits;
126 u32 trap_inst_exits;
127 u32 msa_fpe_exits;
128 u32 fpe_exits;
129 u32 msa_disabled_exits;
130 u32 flush_dcache_exits;
131 u32 halt_successful_poll;
132 u32 halt_attempted_poll;
133 u32 halt_wakeup;
134 };
135
136 enum kvm_mips_exit_types {
137 WAIT_EXITS,
138 CACHE_EXITS,
139 SIGNAL_EXITS,
140 INT_EXITS,
141 COP_UNUSABLE_EXITS,
142 TLBMOD_EXITS,
143 TLBMISS_LD_EXITS,
144 TLBMISS_ST_EXITS,
145 ADDRERR_ST_EXITS,
146 ADDRERR_LD_EXITS,
147 SYSCALL_EXITS,
148 RESVD_INST_EXITS,
149 BREAK_INST_EXITS,
150 TRAP_INST_EXITS,
151 MSA_FPE_EXITS,
152 FPE_EXITS,
153 MSA_DISABLED_EXITS,
154 FLUSH_DCACHE_EXITS,
155 MAX_KVM_MIPS_EXIT_TYPES
156 };
157
158 struct kvm_arch_memory_slot {
159 };
160
161 struct kvm_arch {
162 /* Guest GVA->HPA page table */
163 unsigned long *guest_pmap;
164 unsigned long guest_pmap_npages;
165
166 /* Wired host TLB used for the commpage */
167 int commpage_tlb;
168 };
169
170 #define N_MIPS_COPROC_REGS 32
171 #define N_MIPS_COPROC_SEL 8
172
173 struct mips_coproc {
174 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
175 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
176 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
177 #endif
178 };
179
180 /*
181 * Coprocessor 0 register names
182 */
183 #define MIPS_CP0_TLB_INDEX 0
184 #define MIPS_CP0_TLB_RANDOM 1
185 #define MIPS_CP0_TLB_LOW 2
186 #define MIPS_CP0_TLB_LO0 2
187 #define MIPS_CP0_TLB_LO1 3
188 #define MIPS_CP0_TLB_CONTEXT 4
189 #define MIPS_CP0_TLB_PG_MASK 5
190 #define MIPS_CP0_TLB_WIRED 6
191 #define MIPS_CP0_HWRENA 7
192 #define MIPS_CP0_BAD_VADDR 8
193 #define MIPS_CP0_COUNT 9
194 #define MIPS_CP0_TLB_HI 10
195 #define MIPS_CP0_COMPARE 11
196 #define MIPS_CP0_STATUS 12
197 #define MIPS_CP0_CAUSE 13
198 #define MIPS_CP0_EXC_PC 14
199 #define MIPS_CP0_PRID 15
200 #define MIPS_CP0_CONFIG 16
201 #define MIPS_CP0_LLADDR 17
202 #define MIPS_CP0_WATCH_LO 18
203 #define MIPS_CP0_WATCH_HI 19
204 #define MIPS_CP0_TLB_XCONTEXT 20
205 #define MIPS_CP0_ECC 26
206 #define MIPS_CP0_CACHE_ERR 27
207 #define MIPS_CP0_TAG_LO 28
208 #define MIPS_CP0_TAG_HI 29
209 #define MIPS_CP0_ERROR_PC 30
210 #define MIPS_CP0_DEBUG 23
211 #define MIPS_CP0_DEPC 24
212 #define MIPS_CP0_PERFCNT 25
213 #define MIPS_CP0_ERRCTL 26
214 #define MIPS_CP0_DATA_LO 28
215 #define MIPS_CP0_DATA_HI 29
216 #define MIPS_CP0_DESAVE 31
217
218 #define MIPS_CP0_CONFIG_SEL 0
219 #define MIPS_CP0_CONFIG1_SEL 1
220 #define MIPS_CP0_CONFIG2_SEL 2
221 #define MIPS_CP0_CONFIG3_SEL 3
222 #define MIPS_CP0_CONFIG4_SEL 4
223 #define MIPS_CP0_CONFIG5_SEL 5
224
225 /* Config0 register bits */
226 #define CP0C0_M 31
227 #define CP0C0_K23 28
228 #define CP0C0_KU 25
229 #define CP0C0_MDU 20
230 #define CP0C0_MM 17
231 #define CP0C0_BM 16
232 #define CP0C0_BE 15
233 #define CP0C0_AT 13
234 #define CP0C0_AR 10
235 #define CP0C0_MT 7
236 #define CP0C0_VI 3
237 #define CP0C0_K0 0
238
239 /* Config1 register bits */
240 #define CP0C1_M 31
241 #define CP0C1_MMU 25
242 #define CP0C1_IS 22
243 #define CP0C1_IL 19
244 #define CP0C1_IA 16
245 #define CP0C1_DS 13
246 #define CP0C1_DL 10
247 #define CP0C1_DA 7
248 #define CP0C1_C2 6
249 #define CP0C1_MD 5
250 #define CP0C1_PC 4
251 #define CP0C1_WR 3
252 #define CP0C1_CA 2
253 #define CP0C1_EP 1
254 #define CP0C1_FP 0
255
256 /* Config2 Register bits */
257 #define CP0C2_M 31
258 #define CP0C2_TU 28
259 #define CP0C2_TS 24
260 #define CP0C2_TL 20
261 #define CP0C2_TA 16
262 #define CP0C2_SU 12
263 #define CP0C2_SS 8
264 #define CP0C2_SL 4
265 #define CP0C2_SA 0
266
267 /* Config3 Register bits */
268 #define CP0C3_M 31
269 #define CP0C3_ISA_ON_EXC 16
270 #define CP0C3_ULRI 13
271 #define CP0C3_DSPP 10
272 #define CP0C3_LPA 7
273 #define CP0C3_VEIC 6
274 #define CP0C3_VInt 5
275 #define CP0C3_SP 4
276 #define CP0C3_MT 2
277 #define CP0C3_SM 1
278 #define CP0C3_TL 0
279
280 /* MMU types, the first four entries have the same layout as the
281 CP0C0_MT field. */
282 enum mips_mmu_types {
283 MMU_TYPE_NONE,
284 MMU_TYPE_R4000,
285 MMU_TYPE_RESERVED,
286 MMU_TYPE_FMT,
287 MMU_TYPE_R3000,
288 MMU_TYPE_R6000,
289 MMU_TYPE_R8000
290 };
291
292 /*
293 * Trap codes
294 */
295 #define T_INT 0 /* Interrupt pending */
296 #define T_TLB_MOD 1 /* TLB modified fault */
297 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
298 #define T_TLB_ST_MISS 3 /* TLB miss on a store */
299 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
300 #define T_ADDR_ERR_ST 5 /* Address error on a store */
301 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
302 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
303 #define T_SYSCALL 8 /* System call */
304 #define T_BREAK 9 /* Breakpoint */
305 #define T_RES_INST 10 /* Reserved instruction exception */
306 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
307 #define T_OVFLOW 12 /* Arithmetic overflow */
308
309 /*
310 * Trap definitions added for r4000 port.
311 */
312 #define T_TRAP 13 /* Trap instruction */
313 #define T_VCEI 14 /* Virtual coherency exception */
314 #define T_MSAFPE 14 /* MSA floating point exception */
315 #define T_FPE 15 /* Floating point exception */
316 #define T_MSADIS 21 /* MSA disabled exception */
317 #define T_WATCH 23 /* Watch address reference */
318 #define T_VCED 31 /* Virtual coherency data */
319
320 /* Resume Flags */
321 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
322 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
323
324 #define RESUME_GUEST 0
325 #define RESUME_GUEST_DR RESUME_FLAG_DR
326 #define RESUME_HOST RESUME_FLAG_HOST
327
328 enum emulation_result {
329 EMULATE_DONE, /* no further processing */
330 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
331 EMULATE_FAIL, /* can't emulate this instruction */
332 EMULATE_WAIT, /* WAIT instruction */
333 EMULATE_PRIV_FAIL,
334 };
335
336 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
337 #define MIPS3_PG_V 0x00000002 /* Valid */
338 #define MIPS3_PG_NV 0x00000000
339 #define MIPS3_PG_D 0x00000004 /* Dirty */
340
341 #define mips3_paddr_to_tlbpfn(x) \
342 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
343 #define mips3_tlbpfn_to_paddr(x) \
344 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
345
346 #define MIPS3_PG_SHIFT 6
347 #define MIPS3_PG_FRAME 0x3fffffc0
348
349 #define VPN2_MASK 0xffffe000
350 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
351 ((x).tlb_lo1 & MIPS3_PG_G))
352 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
353 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
354 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
355 ? ((x).tlb_lo1 & MIPS3_PG_V) \
356 : ((x).tlb_lo0 & MIPS3_PG_V))
357 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
358 ((y) & VPN2_MASK & ~(x).tlb_mask))
359 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
360 TLB_ASID(x) == ((y) & ASID_MASK))
361
362 struct kvm_mips_tlb {
363 long tlb_mask;
364 long tlb_hi;
365 long tlb_lo0;
366 long tlb_lo1;
367 };
368
369 #define KVM_MIPS_FPU_FPU 0x1
370 #define KVM_MIPS_FPU_MSA 0x2
371
372 #define KVM_MIPS_GUEST_TLB_SIZE 64
373 struct kvm_vcpu_arch {
374 void *host_ebase, *guest_ebase;
375 unsigned long host_stack;
376 unsigned long host_gp;
377
378 /* Host CP0 registers used when handling exits from guest */
379 unsigned long host_cp0_badvaddr;
380 unsigned long host_cp0_cause;
381 unsigned long host_cp0_epc;
382 unsigned long host_cp0_entryhi;
383 uint32_t guest_inst;
384
385 /* GPRS */
386 unsigned long gprs[32];
387 unsigned long hi;
388 unsigned long lo;
389 unsigned long pc;
390
391 /* FPU State */
392 struct mips_fpu_struct fpu;
393 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
394 unsigned int fpu_inuse;
395
396 /* COP0 State */
397 struct mips_coproc *cop0;
398
399 /* Host KSEG0 address of the EI/DI offset */
400 void *kseg0_commpage;
401
402 u32 io_gpr; /* GPR used as IO source/target */
403
404 struct hrtimer comparecount_timer;
405 /* Count timer control KVM register */
406 uint32_t count_ctl;
407 /* Count bias from the raw time */
408 uint32_t count_bias;
409 /* Frequency of timer in Hz */
410 uint32_t count_hz;
411 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
412 s64 count_dyn_bias;
413 /* Resume time */
414 ktime_t count_resume;
415 /* Period of timer tick in ns */
416 u64 count_period;
417
418 /* Bitmask of exceptions that are pending */
419 unsigned long pending_exceptions;
420
421 /* Bitmask of pending exceptions to be cleared */
422 unsigned long pending_exceptions_clr;
423
424 unsigned long pending_load_cause;
425
426 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
427 unsigned long preempt_entryhi;
428
429 /* S/W Based TLB for guest */
430 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
431
432 /* Cached guest kernel/user ASIDs */
433 uint32_t guest_user_asid[NR_CPUS];
434 uint32_t guest_kernel_asid[NR_CPUS];
435 struct mm_struct guest_kernel_mm, guest_user_mm;
436
437 int last_sched_cpu;
438
439 /* WAIT executed */
440 int wait;
441
442 u8 fpu_enabled;
443 u8 msa_enabled;
444 };
445
446
447 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
448 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
449 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
450 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
451 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
452 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
453 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
454 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
455 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
456 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
457 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
458 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
459 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
460 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
461 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
462 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
463 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
464 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
465 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
466 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
467 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
468 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
469 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
470 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
471 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
472 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
473 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
474 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
475 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
476 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
477 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
478 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
479 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
480 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
481 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
482 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
483 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
484 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
485 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
486 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
487 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
488 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
489 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
490 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
491 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
492 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
493 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
494 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
495 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
496 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
497
498 /*
499 * Some of the guest registers may be modified asynchronously (e.g. from a
500 * hrtimer callback in hard irq context) and therefore need stronger atomicity
501 * guarantees than other registers.
502 */
503
504 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
505 unsigned long val)
506 {
507 unsigned long temp;
508 do {
509 __asm__ __volatile__(
510 " .set mips3 \n"
511 " " __LL "%0, %1 \n"
512 " or %0, %2 \n"
513 " " __SC "%0, %1 \n"
514 " .set mips0 \n"
515 : "=&r" (temp), "+m" (*reg)
516 : "r" (val));
517 } while (unlikely(!temp));
518 }
519
520 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
521 unsigned long val)
522 {
523 unsigned long temp;
524 do {
525 __asm__ __volatile__(
526 " .set mips3 \n"
527 " " __LL "%0, %1 \n"
528 " and %0, %2 \n"
529 " " __SC "%0, %1 \n"
530 " .set mips0 \n"
531 : "=&r" (temp), "+m" (*reg)
532 : "r" (~val));
533 } while (unlikely(!temp));
534 }
535
536 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
537 unsigned long change,
538 unsigned long val)
539 {
540 unsigned long temp;
541 do {
542 __asm__ __volatile__(
543 " .set mips3 \n"
544 " " __LL "%0, %1 \n"
545 " and %0, %2 \n"
546 " or %0, %3 \n"
547 " " __SC "%0, %1 \n"
548 " .set mips0 \n"
549 : "=&r" (temp), "+m" (*reg)
550 : "r" (~change), "r" (val & change));
551 } while (unlikely(!temp));
552 }
553
554 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
555 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
556
557 /* Cause can be modified asynchronously from hardirq hrtimer callback */
558 #define kvm_set_c0_guest_cause(cop0, val) \
559 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
560 #define kvm_clear_c0_guest_cause(cop0, val) \
561 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
562 #define kvm_change_c0_guest_cause(cop0, change, val) \
563 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
564 change, val)
565
566 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
567 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
568 #define kvm_change_c0_guest_ebase(cop0, change, val) \
569 { \
570 kvm_clear_c0_guest_ebase(cop0, change); \
571 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
572 }
573
574 /* Helpers */
575
576 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
577 {
578 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
579 vcpu->fpu_enabled;
580 }
581
582 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
583 {
584 return kvm_mips_guest_can_have_fpu(vcpu) &&
585 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
586 }
587
588 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
589 {
590 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
591 vcpu->msa_enabled;
592 }
593
594 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
595 {
596 return kvm_mips_guest_can_have_msa(vcpu) &&
597 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
598 }
599
600 struct kvm_mips_callbacks {
601 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
602 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
603 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
604 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
605 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
606 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
607 int (*handle_syscall)(struct kvm_vcpu *vcpu);
608 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
609 int (*handle_break)(struct kvm_vcpu *vcpu);
610 int (*handle_trap)(struct kvm_vcpu *vcpu);
611 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
612 int (*handle_fpe)(struct kvm_vcpu *vcpu);
613 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
614 int (*vm_init)(struct kvm *kvm);
615 int (*vcpu_init)(struct kvm_vcpu *vcpu);
616 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
617 gpa_t (*gva_to_gpa)(gva_t gva);
618 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
619 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
620 void (*queue_io_int)(struct kvm_vcpu *vcpu,
621 struct kvm_mips_interrupt *irq);
622 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
623 struct kvm_mips_interrupt *irq);
624 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
625 uint32_t cause);
626 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
627 uint32_t cause);
628 int (*get_one_reg)(struct kvm_vcpu *vcpu,
629 const struct kvm_one_reg *reg, s64 *v);
630 int (*set_one_reg)(struct kvm_vcpu *vcpu,
631 const struct kvm_one_reg *reg, s64 v);
632 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
633 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
634 };
635 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
636 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
637
638 /* Debug: dump vcpu state */
639 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
640
641 /* Trampoline ASM routine to start running in "Guest" context */
642 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
643
644 /* FPU/MSA context management */
645 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
646 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
647 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
648 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
649 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
650 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
651 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
652 void kvm_own_fpu(struct kvm_vcpu *vcpu);
653 void kvm_own_msa(struct kvm_vcpu *vcpu);
654 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
655 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
656
657 /* TLB handling */
658 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
659
660 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
661
662 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
663
664 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
665 struct kvm_vcpu *vcpu);
666
667 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
668 struct kvm_vcpu *vcpu);
669
670 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
671 struct kvm_mips_tlb *tlb,
672 unsigned long *hpa0,
673 unsigned long *hpa1);
674
675 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
676 uint32_t *opc,
677 struct kvm_run *run,
678 struct kvm_vcpu *vcpu);
679
680 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
681 uint32_t *opc,
682 struct kvm_run *run,
683 struct kvm_vcpu *vcpu);
684
685 extern void kvm_mips_dump_host_tlbs(void);
686 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
687 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
688 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
689 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
690
691 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
692 unsigned long entryhi);
693 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
694 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
695 unsigned long gva);
696 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
697 struct kvm_vcpu *vcpu);
698 extern void kvm_local_flush_tlb_all(void);
699 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
700 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
701 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
702
703 /* Emulation */
704 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
705 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
706
707 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
708 uint32_t *opc,
709 struct kvm_run *run,
710 struct kvm_vcpu *vcpu);
711
712 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
713 uint32_t *opc,
714 struct kvm_run *run,
715 struct kvm_vcpu *vcpu);
716
717 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
718 uint32_t *opc,
719 struct kvm_run *run,
720 struct kvm_vcpu *vcpu);
721
722 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
723 uint32_t *opc,
724 struct kvm_run *run,
725 struct kvm_vcpu *vcpu);
726
727 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
728 uint32_t *opc,
729 struct kvm_run *run,
730 struct kvm_vcpu *vcpu);
731
732 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
733 uint32_t *opc,
734 struct kvm_run *run,
735 struct kvm_vcpu *vcpu);
736
737 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
738 uint32_t *opc,
739 struct kvm_run *run,
740 struct kvm_vcpu *vcpu);
741
742 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
743 uint32_t *opc,
744 struct kvm_run *run,
745 struct kvm_vcpu *vcpu);
746
747 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
748 uint32_t *opc,
749 struct kvm_run *run,
750 struct kvm_vcpu *vcpu);
751
752 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
753 uint32_t *opc,
754 struct kvm_run *run,
755 struct kvm_vcpu *vcpu);
756
757 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
758 uint32_t *opc,
759 struct kvm_run *run,
760 struct kvm_vcpu *vcpu);
761
762 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
763 uint32_t *opc,
764 struct kvm_run *run,
765 struct kvm_vcpu *vcpu);
766
767 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
768 uint32_t *opc,
769 struct kvm_run *run,
770 struct kvm_vcpu *vcpu);
771
772 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
773 uint32_t *opc,
774 struct kvm_run *run,
775 struct kvm_vcpu *vcpu);
776
777 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
778 uint32_t *opc,
779 struct kvm_run *run,
780 struct kvm_vcpu *vcpu);
781
782 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
783 struct kvm_run *run);
784
785 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
786 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
787 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
788 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
789 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
790 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
791 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
792 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
793 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
794 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
795
796 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
797 uint32_t *opc,
798 struct kvm_run *run,
799 struct kvm_vcpu *vcpu);
800
801 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
802 uint32_t *opc,
803 uint32_t cause,
804 struct kvm_run *run,
805 struct kvm_vcpu *vcpu);
806 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
807 uint32_t *opc,
808 uint32_t cause,
809 struct kvm_run *run,
810 struct kvm_vcpu *vcpu);
811 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
812 uint32_t cause,
813 struct kvm_run *run,
814 struct kvm_vcpu *vcpu);
815 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
816 uint32_t cause,
817 struct kvm_run *run,
818 struct kvm_vcpu *vcpu);
819
820 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
821 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
822 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
823 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
824
825 /* Dynamic binary translation */
826 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
827 struct kvm_vcpu *vcpu);
828 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
829 struct kvm_vcpu *vcpu);
830 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
831 struct kvm_vcpu *vcpu);
832 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
833 struct kvm_vcpu *vcpu);
834
835 /* Misc */
836 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
837 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
838
839 static inline void kvm_arch_hardware_disable(void) {}
840 static inline void kvm_arch_hardware_unsetup(void) {}
841 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
842 static inline void kvm_arch_free_memslot(struct kvm *kvm,
843 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
844 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
845 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
846 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
847 struct kvm_memory_slot *slot) {}
848 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
849 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
850 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
851 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
852
853 #endif /* __MIPS_KVM_HOST_H__ */
Linux with added FPC-III support