2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is in this distribution in the file
21 * Documentation: ARM DDI 0196G == PL080
22 * Documentation: ARM DDI 0218E == PL081
23 * Documentation: S3C6410 User's Manual == PL080S
25 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
28 * The PL080 has 8 channels available for simultaneous use, and the PL081
29 * has only two channels. So on these DMA controllers the number of channels
30 * and the number of incoming DMA signals are two totally different things.
31 * It is usually not possible to theoretically handle all physical signals,
32 * so a multiplexing scheme with possible denial of use is necessary.
34 * The PL080 has a dual bus master, PL081 has a single master.
36 * PL080S is a version modified by Samsung and used in S3C64xx SoCs.
37 * It differs in following aspects:
38 * - CH_CONFIG register at different offset,
39 * - separate CH_CONTROL2 register for transfer size,
40 * - bigger maximum transfer size,
41 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
42 * - no support for peripheral flow control.
44 * Memory to peripheral transfer may be visualized as
45 * Get data from memory to DMAC
47 * On burst request from peripheral
48 * Destination burst from DMAC to peripheral
50 * Raise terminal count interrupt
52 * For peripherals with a FIFO:
53 * Source burst size == half the depth of the peripheral FIFO
54 * Destination burst size == the depth of the peripheral FIFO
56 * (Bursts are irrelevant for mem to mem transfers - there are no burst
57 * signals, the DMA controller will simply facilitate its AHB master.)
59 * ASSUMES default (little) endianness for DMA transfers
61 * The PL08x has two flow control settings:
62 * - DMAC flow control: the transfer size defines the number of transfers
63 * which occur for the current LLI entry, and the DMAC raises TC at the
64 * end of every LLI entry. Observed behaviour shows the DMAC listening
65 * to both the BREQ and SREQ signals (contrary to documented),
66 * transferring data if either is active. The LBREQ and LSREQ signals
69 * - Peripheral flow control: the transfer size is ignored (and should be
70 * zero). The data is transferred from the current LLI entry, until
71 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
72 * will then move to the next LLI entry. Unsupported by PL080S.
74 #include <linux/amba/bus.h>
75 #include <linux/amba/pl08x.h>
76 #include <linux/debugfs.h>
77 #include <linux/delay.h>
78 #include <linux/device.h>
79 #include <linux/dmaengine.h>
80 #include <linux/dmapool.h>
81 #include <linux/dma-mapping.h>
82 #include <linux/export.h>
83 #include <linux/init.h>
84 #include <linux/interrupt.h>
85 #include <linux/module.h>
87 #include <linux/of_dma.h>
88 #include <linux/pm_runtime.h>
89 #include <linux/seq_file.h>
90 #include <linux/slab.h>
91 #include <linux/amba/pl080.h>
93 #include "dmaengine.h"
96 #define DRIVER_NAME "pl08xdmac"
98 #define PL80X_DMA_BUSWIDTHS \
99 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
100 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
101 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
102 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
104 static struct amba_driver pl08x_amba_driver
;
105 struct pl08x_driver_data
;
108 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
109 * @channels: the number of channels available in this variant
110 * @dualmaster: whether this version supports dual AHB masters or not.
111 * @nomadik: whether the channels have Nomadik security extension bits
112 * that need to be checked for permission before use and some registers are
114 * @pl080s: whether this version is a PL080S, which has separate register and
115 * LLI word for transfer size.
123 u32 max_transfer_size
;
127 * struct pl08x_bus_data - information of source or destination
128 * busses for a transfer
129 * @addr: current address
130 * @maxwidth: the maximum width of a transfer on this bus
131 * @buswidth: the width of this bus in bytes: 1, 2 or 4
133 struct pl08x_bus_data
{
139 #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
142 * struct pl08x_phy_chan - holder for the physical channels
143 * @id: physical index to this channel
144 * @lock: a lock to use when altering an instance of this struct
145 * @serving: the virtual channel currently being served by this physical
147 * @locked: channel unavailable for the system, e.g. dedicated to secure
150 struct pl08x_phy_chan
{
153 void __iomem
*reg_config
;
155 struct pl08x_dma_chan
*serving
;
160 * struct pl08x_sg - structure containing data per sg
161 * @src_addr: src address of sg
162 * @dst_addr: dst address of sg
163 * @len: transfer len in bytes
164 * @node: node for txd's dsg_list
170 struct list_head node
;
174 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
175 * @vd: virtual DMA descriptor
176 * @dsg_list: list of children sg's
177 * @llis_bus: DMA memory address (physical) start for the LLIs
178 * @llis_va: virtual memory address start for the LLIs
179 * @cctl: control reg values for current txd
180 * @ccfg: config reg values for current txd
181 * @done: this marks completed descriptors, which should not have their
183 * @cyclic: indicate cyclic transfers
186 struct virt_dma_desc vd
;
187 struct list_head dsg_list
;
190 /* Default cctl value for LLIs */
193 * Settings to be put into the physical channel when we
194 * trigger this txd. Other registers are in llis_va[0].
202 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
204 * @PL08X_CHAN_IDLE: the channel is idle
205 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
206 * channel and is running a transfer on it
207 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
208 * channel, but the transfer is currently paused
209 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
210 * channel to become available (only pertains to memcpy channels)
212 enum pl08x_dma_chan_state
{
220 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
221 * @vc: wrappped virtual channel
222 * @phychan: the physical channel utilized by this channel, if there is one
223 * @name: name of channel
224 * @cd: channel platform data
225 * @runtime_addr: address for RX/TX according to the runtime config
226 * @at: active transaction on this channel
227 * @lock: a lock for this channel data
228 * @host: a pointer to the host (internal use)
229 * @state: whether the channel is idle, paused, running etc
230 * @slave: whether this channel is a device (slave) or for memcpy
231 * @signal: the physical DMA request signal which this channel is using
232 * @mux_use: count of descriptors using this DMA request signal setting
234 struct pl08x_dma_chan
{
235 struct virt_dma_chan vc
;
236 struct pl08x_phy_chan
*phychan
;
238 const struct pl08x_channel_data
*cd
;
239 struct dma_slave_config cfg
;
240 struct pl08x_txd
*at
;
241 struct pl08x_driver_data
*host
;
242 enum pl08x_dma_chan_state state
;
249 * struct pl08x_driver_data - the local state holder for the PL08x
250 * @slave: slave engine for this instance
251 * @memcpy: memcpy engine for this instance
252 * @base: virtual memory base (remapped) for the PL08x
253 * @adev: the corresponding AMBA (PrimeCell) bus entry
254 * @vd: vendor data for this PL08x variant
255 * @pd: platform data passed in from the platform/machine
256 * @phy_chans: array of data for the physical channels
257 * @pool: a pool for the LLI descriptors
258 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
260 * @mem_buses: set to indicate memory transfers on AHB2.
261 * @lock: a spinlock for this struct
263 struct pl08x_driver_data
{
264 struct dma_device slave
;
265 struct dma_device memcpy
;
267 struct amba_device
*adev
;
268 const struct vendor_data
*vd
;
269 struct pl08x_platform_data
*pd
;
270 struct pl08x_phy_chan
*phy_chans
;
271 struct dma_pool
*pool
;
278 * PL08X specific defines
281 /* The order of words in an LLI. */
282 #define PL080_LLI_SRC 0
283 #define PL080_LLI_DST 1
284 #define PL080_LLI_LLI 2
285 #define PL080_LLI_CCTL 3
286 #define PL080S_LLI_CCTL2 4
288 /* Total words in an LLI. */
289 #define PL080_LLI_WORDS 4
290 #define PL080S_LLI_WORDS 8
293 * Number of LLIs in each LLI buffer allocated for one transfer
294 * (maximum times we call dma_pool_alloc on this pool without freeing)
296 #define MAX_NUM_TSFR_LLIS 512
297 #define PL08X_ALIGN 8
299 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
301 return container_of(chan
, struct pl08x_dma_chan
, vc
.chan
);
304 static inline struct pl08x_txd
*to_pl08x_txd(struct dma_async_tx_descriptor
*tx
)
306 return container_of(tx
, struct pl08x_txd
, vd
.tx
);
312 * This gives us the DMA request input to the PL08x primecell which the
313 * peripheral described by the channel data will be routed to, possibly
314 * via a board/SoC specific external MUX. One important point to note
315 * here is that this does not depend on the physical channel.
317 static int pl08x_request_mux(struct pl08x_dma_chan
*plchan
)
319 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
322 if (plchan
->mux_use
++ == 0 && pd
->get_xfer_signal
) {
323 ret
= pd
->get_xfer_signal(plchan
->cd
);
329 plchan
->signal
= ret
;
334 static void pl08x_release_mux(struct pl08x_dma_chan
*plchan
)
336 const struct pl08x_platform_data
*pd
= plchan
->host
->pd
;
338 if (plchan
->signal
>= 0) {
339 WARN_ON(plchan
->mux_use
== 0);
341 if (--plchan
->mux_use
== 0 && pd
->put_xfer_signal
) {
342 pd
->put_xfer_signal(plchan
->cd
, plchan
->signal
);
349 * Physical channel handling
352 /* Whether a certain channel is busy or not */
353 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
357 val
= readl(ch
->reg_config
);
358 return val
& PL080_CONFIG_ACTIVE
;
361 static void pl08x_write_lli(struct pl08x_driver_data
*pl08x
,
362 struct pl08x_phy_chan
*phychan
, const u32
*lli
, u32 ccfg
)
364 if (pl08x
->vd
->pl080s
)
365 dev_vdbg(&pl08x
->adev
->dev
,
366 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
367 "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",
368 phychan
->id
, lli
[PL080_LLI_SRC
], lli
[PL080_LLI_DST
],
369 lli
[PL080_LLI_LLI
], lli
[PL080_LLI_CCTL
],
370 lli
[PL080S_LLI_CCTL2
], ccfg
);
372 dev_vdbg(&pl08x
->adev
->dev
,
373 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
374 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
375 phychan
->id
, lli
[PL080_LLI_SRC
], lli
[PL080_LLI_DST
],
376 lli
[PL080_LLI_LLI
], lli
[PL080_LLI_CCTL
], ccfg
);
378 writel_relaxed(lli
[PL080_LLI_SRC
], phychan
->base
+ PL080_CH_SRC_ADDR
);
379 writel_relaxed(lli
[PL080_LLI_DST
], phychan
->base
+ PL080_CH_DST_ADDR
);
380 writel_relaxed(lli
[PL080_LLI_LLI
], phychan
->base
+ PL080_CH_LLI
);
381 writel_relaxed(lli
[PL080_LLI_CCTL
], phychan
->base
+ PL080_CH_CONTROL
);
383 if (pl08x
->vd
->pl080s
)
384 writel_relaxed(lli
[PL080S_LLI_CCTL2
],
385 phychan
->base
+ PL080S_CH_CONTROL2
);
387 writel(ccfg
, phychan
->reg_config
);
391 * Set the initial DMA register values i.e. those for the first LLI
392 * The next LLI pointer and the configuration interrupt bit have
393 * been set when the LLIs were constructed. Poke them into the hardware
394 * and start the transfer.
396 static void pl08x_start_next_txd(struct pl08x_dma_chan
*plchan
)
398 struct pl08x_driver_data
*pl08x
= plchan
->host
;
399 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
400 struct virt_dma_desc
*vd
= vchan_next_desc(&plchan
->vc
);
401 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
404 list_del(&txd
->vd
.node
);
408 /* Wait for channel inactive */
409 while (pl08x_phy_channel_busy(phychan
))
412 pl08x_write_lli(pl08x
, phychan
, &txd
->llis_va
[0], txd
->ccfg
);
414 /* Enable the DMA channel */
415 /* Do not access config register until channel shows as disabled */
416 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << phychan
->id
))
419 /* Do not access config register until channel shows as inactive */
420 val
= readl(phychan
->reg_config
);
421 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
422 val
= readl(phychan
->reg_config
);
424 writel(val
| PL080_CONFIG_ENABLE
, phychan
->reg_config
);
428 * Pause the channel by setting the HALT bit.
430 * For M->P transfers, pause the DMAC first and then stop the peripheral -
431 * the FIFO can only drain if the peripheral is still requesting data.
432 * (note: this can still timeout if the DMAC FIFO never drains of data.)
434 * For P->M transfers, disable the peripheral first to stop it filling
435 * the DMAC FIFO, and then pause the DMAC.
437 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
442 /* Set the HALT bit and wait for the FIFO to drain */
443 val
= readl(ch
->reg_config
);
444 val
|= PL080_CONFIG_HALT
;
445 writel(val
, ch
->reg_config
);
447 /* Wait for channel inactive */
448 for (timeout
= 1000; timeout
; timeout
--) {
449 if (!pl08x_phy_channel_busy(ch
))
453 if (pl08x_phy_channel_busy(ch
))
454 pr_err("pl08x: channel%u timeout waiting for pause\n", ch
->id
);
457 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
461 /* Clear the HALT bit */
462 val
= readl(ch
->reg_config
);
463 val
&= ~PL080_CONFIG_HALT
;
464 writel(val
, ch
->reg_config
);
468 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
469 * clears any pending interrupt status. This should not be used for
470 * an on-going transfer, but as a method of shutting down a channel
471 * (eg, when it's no longer used) or terminating a transfer.
473 static void pl08x_terminate_phy_chan(struct pl08x_driver_data
*pl08x
,
474 struct pl08x_phy_chan
*ch
)
476 u32 val
= readl(ch
->reg_config
);
478 val
&= ~(PL080_CONFIG_ENABLE
| PL080_CONFIG_ERR_IRQ_MASK
|
479 PL080_CONFIG_TC_IRQ_MASK
);
481 writel(val
, ch
->reg_config
);
483 writel(1 << ch
->id
, pl08x
->base
+ PL080_ERR_CLEAR
);
484 writel(1 << ch
->id
, pl08x
->base
+ PL080_TC_CLEAR
);
487 static inline u32
get_bytes_in_cctl(u32 cctl
)
489 /* The source width defines the number of bytes */
490 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
492 cctl
&= PL080_CONTROL_SWIDTH_MASK
;
494 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
495 case PL080_WIDTH_8BIT
:
497 case PL080_WIDTH_16BIT
:
500 case PL080_WIDTH_32BIT
:
507 static inline u32
get_bytes_in_cctl_pl080s(u32 cctl
, u32 cctl1
)
509 /* The source width defines the number of bytes */
510 u32 bytes
= cctl1
& PL080S_CONTROL_TRANSFER_SIZE_MASK
;
512 cctl
&= PL080_CONTROL_SWIDTH_MASK
;
514 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
515 case PL080_WIDTH_8BIT
:
517 case PL080_WIDTH_16BIT
:
520 case PL080_WIDTH_32BIT
:
527 /* The channel should be paused when calling this */
528 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
530 struct pl08x_driver_data
*pl08x
= plchan
->host
;
531 const u32
*llis_va
, *llis_va_limit
;
532 struct pl08x_phy_chan
*ch
;
534 struct pl08x_txd
*txd
;
539 ch
= plchan
->phychan
;
546 * Follow the LLIs to get the number of remaining
547 * bytes in the currently active transaction.
549 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
551 /* First get the remaining bytes in the active transfer */
552 if (pl08x
->vd
->pl080s
)
553 bytes
= get_bytes_in_cctl_pl080s(
554 readl(ch
->base
+ PL080_CH_CONTROL
),
555 readl(ch
->base
+ PL080S_CH_CONTROL2
));
557 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
562 llis_va
= txd
->llis_va
;
563 llis_bus
= txd
->llis_bus
;
565 llis_max_words
= pl08x
->lli_words
* MAX_NUM_TSFR_LLIS
;
566 BUG_ON(clli
< llis_bus
|| clli
>= llis_bus
+
567 sizeof(u32
) * llis_max_words
);
570 * Locate the next LLI - as this is an array,
571 * it's simple maths to find.
573 llis_va
+= (clli
- llis_bus
) / sizeof(u32
);
575 llis_va_limit
= llis_va
+ llis_max_words
;
577 for (; llis_va
< llis_va_limit
; llis_va
+= pl08x
->lli_words
) {
578 if (pl08x
->vd
->pl080s
)
579 bytes
+= get_bytes_in_cctl_pl080s(
580 llis_va
[PL080_LLI_CCTL
],
581 llis_va
[PL080S_LLI_CCTL2
]);
583 bytes
+= get_bytes_in_cctl(llis_va
[PL080_LLI_CCTL
]);
586 * A LLI pointer going backward terminates the LLI list
588 if (llis_va
[PL080_LLI_LLI
] <= clli
)
596 * Allocate a physical channel for a virtual channel
598 * Try to locate a physical channel to be used for this transfer. If all
599 * are taken return NULL and the requester will have to cope by using
600 * some fallback PIO mode or retrying later.
602 static struct pl08x_phy_chan
*
603 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
604 struct pl08x_dma_chan
*virt_chan
)
606 struct pl08x_phy_chan
*ch
= NULL
;
610 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
611 ch
= &pl08x
->phy_chans
[i
];
613 spin_lock_irqsave(&ch
->lock
, flags
);
615 if (!ch
->locked
&& !ch
->serving
) {
616 ch
->serving
= virt_chan
;
617 spin_unlock_irqrestore(&ch
->lock
, flags
);
621 spin_unlock_irqrestore(&ch
->lock
, flags
);
624 if (i
== pl08x
->vd
->channels
) {
625 /* No physical channel available, cope with it */
632 /* Mark the physical channel as free. Note, this write is atomic. */
633 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
634 struct pl08x_phy_chan
*ch
)
640 * Try to allocate a physical channel. When successful, assign it to
641 * this virtual channel, and initiate the next descriptor. The
642 * virtual channel lock must be held at this point.
644 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan
*plchan
)
646 struct pl08x_driver_data
*pl08x
= plchan
->host
;
647 struct pl08x_phy_chan
*ch
;
649 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
651 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
652 plchan
->state
= PL08X_CHAN_WAITING
;
656 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d for xfer on %s\n",
657 ch
->id
, plchan
->name
);
659 plchan
->phychan
= ch
;
660 plchan
->state
= PL08X_CHAN_RUNNING
;
661 pl08x_start_next_txd(plchan
);
664 static void pl08x_phy_reassign_start(struct pl08x_phy_chan
*ch
,
665 struct pl08x_dma_chan
*plchan
)
667 struct pl08x_driver_data
*pl08x
= plchan
->host
;
669 dev_dbg(&pl08x
->adev
->dev
, "reassigned physical channel %d for xfer on %s\n",
670 ch
->id
, plchan
->name
);
673 * We do this without taking the lock; we're really only concerned
674 * about whether this pointer is NULL or not, and we're guaranteed
675 * that this will only be called when it _already_ is non-NULL.
677 ch
->serving
= plchan
;
678 plchan
->phychan
= ch
;
679 plchan
->state
= PL08X_CHAN_RUNNING
;
680 pl08x_start_next_txd(plchan
);
684 * Free a physical DMA channel, potentially reallocating it to another
685 * virtual channel if we have any pending.
687 static void pl08x_phy_free(struct pl08x_dma_chan
*plchan
)
689 struct pl08x_driver_data
*pl08x
= plchan
->host
;
690 struct pl08x_dma_chan
*p
, *next
;
695 /* Find a waiting virtual channel for the next transfer. */
696 list_for_each_entry(p
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
)
697 if (p
->state
== PL08X_CHAN_WAITING
) {
703 list_for_each_entry(p
, &pl08x
->slave
.channels
, vc
.chan
.device_node
)
704 if (p
->state
== PL08X_CHAN_WAITING
) {
710 /* Ensure that the physical channel is stopped */
711 pl08x_terminate_phy_chan(pl08x
, plchan
->phychan
);
717 * Eww. We know this isn't going to deadlock
718 * but lockdep probably doesn't.
720 spin_lock(&next
->vc
.lock
);
721 /* Re-check the state now that we have the lock */
722 success
= next
->state
== PL08X_CHAN_WAITING
;
724 pl08x_phy_reassign_start(plchan
->phychan
, next
);
725 spin_unlock(&next
->vc
.lock
);
727 /* If the state changed, try to find another channel */
731 /* No more jobs, so free up the physical channel */
732 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
735 plchan
->phychan
= NULL
;
736 plchan
->state
= PL08X_CHAN_IDLE
;
743 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
746 case PL080_WIDTH_8BIT
:
748 case PL080_WIDTH_16BIT
:
750 case PL080_WIDTH_32BIT
:
759 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
764 /* Remove all src, dst and transfer size bits */
765 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
766 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
767 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
769 /* Then set the bits according to the parameters */
772 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
775 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
778 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
787 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
790 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
793 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
800 tsize
&= PL080_CONTROL_TRANSFER_SIZE_MASK
;
801 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
805 struct pl08x_lli_build_data
{
806 struct pl08x_txd
*txd
;
807 struct pl08x_bus_data srcbus
;
808 struct pl08x_bus_data dstbus
;
814 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
815 * victim in case src & dest are not similarly aligned. i.e. If after aligning
816 * masters address with width requirements of transfer (by sending few byte by
817 * byte data), slave is still not aligned, then its width will be reduced to
819 * - prefers the destination bus if both available
820 * - prefers bus with fixed address (i.e. peripheral)
822 static void pl08x_choose_master_bus(struct pl08x_lli_build_data
*bd
,
823 struct pl08x_bus_data
**mbus
, struct pl08x_bus_data
**sbus
, u32 cctl
)
825 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
828 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
832 if (bd
->dstbus
.buswidth
>= bd
->srcbus
.buswidth
) {
843 * Fills in one LLI for a certain transfer descriptor and advance the counter
845 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data
*pl08x
,
846 struct pl08x_lli_build_data
*bd
,
847 int num_llis
, int len
, u32 cctl
, u32 cctl2
)
849 u32 offset
= num_llis
* pl08x
->lli_words
;
850 u32
*llis_va
= bd
->txd
->llis_va
+ offset
;
851 dma_addr_t llis_bus
= bd
->txd
->llis_bus
;
853 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
855 /* Advance the offset to next LLI. */
856 offset
+= pl08x
->lli_words
;
858 llis_va
[PL080_LLI_SRC
] = bd
->srcbus
.addr
;
859 llis_va
[PL080_LLI_DST
] = bd
->dstbus
.addr
;
860 llis_va
[PL080_LLI_LLI
] = (llis_bus
+ sizeof(u32
) * offset
);
861 llis_va
[PL080_LLI_LLI
] |= bd
->lli_bus
;
862 llis_va
[PL080_LLI_CCTL
] = cctl
;
863 if (pl08x
->vd
->pl080s
)
864 llis_va
[PL080S_LLI_CCTL2
] = cctl2
;
866 if (cctl
& PL080_CONTROL_SRC_INCR
)
867 bd
->srcbus
.addr
+= len
;
868 if (cctl
& PL080_CONTROL_DST_INCR
)
869 bd
->dstbus
.addr
+= len
;
871 BUG_ON(bd
->remainder
< len
);
873 bd
->remainder
-= len
;
876 static inline void prep_byte_width_lli(struct pl08x_driver_data
*pl08x
,
877 struct pl08x_lli_build_data
*bd
, u32
*cctl
, u32 len
,
878 int num_llis
, size_t *total_bytes
)
880 *cctl
= pl08x_cctl_bits(*cctl
, 1, 1, len
);
881 pl08x_fill_lli_for_desc(pl08x
, bd
, num_llis
, len
, *cctl
, len
);
882 (*total_bytes
) += len
;
886 static void pl08x_dump_lli(struct pl08x_driver_data
*pl08x
,
887 const u32
*llis_va
, int num_llis
)
891 if (pl08x
->vd
->pl080s
) {
892 dev_vdbg(&pl08x
->adev
->dev
,
893 "%-3s %-9s %-10s %-10s %-10s %-10s %s\n",
894 "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
895 for (i
= 0; i
< num_llis
; i
++) {
896 dev_vdbg(&pl08x
->adev
->dev
,
897 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
898 i
, llis_va
, llis_va
[PL080_LLI_SRC
],
899 llis_va
[PL080_LLI_DST
], llis_va
[PL080_LLI_LLI
],
900 llis_va
[PL080_LLI_CCTL
],
901 llis_va
[PL080S_LLI_CCTL2
]);
902 llis_va
+= pl08x
->lli_words
;
905 dev_vdbg(&pl08x
->adev
->dev
,
906 "%-3s %-9s %-10s %-10s %-10s %s\n",
907 "lli", "", "csrc", "cdst", "clli", "cctl");
908 for (i
= 0; i
< num_llis
; i
++) {
909 dev_vdbg(&pl08x
->adev
->dev
,
910 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
911 i
, llis_va
, llis_va
[PL080_LLI_SRC
],
912 llis_va
[PL080_LLI_DST
], llis_va
[PL080_LLI_LLI
],
913 llis_va
[PL080_LLI_CCTL
]);
914 llis_va
+= pl08x
->lli_words
;
919 static inline void pl08x_dump_lli(struct pl08x_driver_data
*pl08x
,
920 const u32
*llis_va
, int num_llis
) {}
924 * This fills in the table of LLIs for the transfer descriptor
925 * Note that we assume we never have to change the burst sizes
928 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
929 struct pl08x_txd
*txd
)
931 struct pl08x_bus_data
*mbus
, *sbus
;
932 struct pl08x_lli_build_data bd
;
934 u32 cctl
, early_bytes
= 0;
935 size_t max_bytes_per_lli
, total_bytes
;
936 u32
*llis_va
, *last_lli
;
937 struct pl08x_sg
*dsg
;
939 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
, &txd
->llis_bus
);
941 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
946 bd
.lli_bus
= (pl08x
->lli_buses
& PL08X_AHB2
) ? PL080_LLI_LM_AHB2
: 0;
949 /* Find maximum width of the source bus */
951 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
952 PL080_CONTROL_SWIDTH_SHIFT
);
954 /* Find maximum width of the destination bus */
956 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
957 PL080_CONTROL_DWIDTH_SHIFT
);
959 list_for_each_entry(dsg
, &txd
->dsg_list
, node
) {
963 bd
.srcbus
.addr
= dsg
->src_addr
;
964 bd
.dstbus
.addr
= dsg
->dst_addr
;
965 bd
.remainder
= dsg
->len
;
966 bd
.srcbus
.buswidth
= bd
.srcbus
.maxwidth
;
967 bd
.dstbus
.buswidth
= bd
.dstbus
.maxwidth
;
969 pl08x_choose_master_bus(&bd
, &mbus
, &sbus
, cctl
);
971 dev_vdbg(&pl08x
->adev
->dev
,
972 "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
974 cctl
& PL080_CONTROL_SRC_INCR
? "+" : "",
977 cctl
& PL080_CONTROL_DST_INCR
? "+" : "",
980 dev_vdbg(&pl08x
->adev
->dev
, "mbus=%s sbus=%s\n",
981 mbus
== &bd
.srcbus
? "src" : "dst",
982 sbus
== &bd
.srcbus
? "src" : "dst");
985 * Zero length is only allowed if all these requirements are
987 * - flow controller is peripheral.
988 * - src.addr is aligned to src.width
989 * - dst.addr is aligned to dst.width
991 * sg_len == 1 should be true, as there can be two cases here:
993 * - Memory addresses are contiguous and are not scattered.
994 * Here, Only one sg will be passed by user driver, with
995 * memory address and zero length. We pass this to controller
996 * and after the transfer it will receive the last burst
997 * request from peripheral and so transfer finishes.
999 * - Memory addresses are scattered and are not contiguous.
1000 * Here, Obviously as DMA controller doesn't know when a lli's
1001 * transfer gets over, it can't load next lli. So in this
1002 * case, there has to be an assumption that only one lli is
1003 * supported. Thus, we can't have scattered addresses.
1005 if (!bd
.remainder
) {
1006 u32 fc
= (txd
->ccfg
& PL080_CONFIG_FLOW_CONTROL_MASK
) >>
1007 PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1008 if (!((fc
>= PL080_FLOW_SRC2DST_DST
) &&
1009 (fc
<= PL080_FLOW_SRC2DST_SRC
))) {
1010 dev_err(&pl08x
->adev
->dev
, "%s sg len can't be zero",
1015 if (!IS_BUS_ALIGNED(&bd
.srcbus
) ||
1016 !IS_BUS_ALIGNED(&bd
.dstbus
)) {
1017 dev_err(&pl08x
->adev
->dev
,
1018 "%s src & dst address must be aligned to src"
1019 " & dst width if peripheral is flow controller",
1024 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
1025 bd
.dstbus
.buswidth
, 0);
1026 pl08x_fill_lli_for_desc(pl08x
, &bd
, num_llis
++,
1032 * Send byte by byte for following cases
1033 * - Less than a bus width available
1034 * - until master bus is aligned
1036 if (bd
.remainder
< mbus
->buswidth
)
1037 early_bytes
= bd
.remainder
;
1038 else if (!IS_BUS_ALIGNED(mbus
)) {
1039 early_bytes
= mbus
->buswidth
-
1040 (mbus
->addr
& (mbus
->buswidth
- 1));
1041 if ((bd
.remainder
- early_bytes
) < mbus
->buswidth
)
1042 early_bytes
= bd
.remainder
;
1046 dev_vdbg(&pl08x
->adev
->dev
,
1047 "%s byte width LLIs (remain 0x%08zx)\n",
1048 __func__
, bd
.remainder
);
1049 prep_byte_width_lli(pl08x
, &bd
, &cctl
, early_bytes
,
1050 num_llis
++, &total_bytes
);
1055 * Master now aligned
1056 * - if slave is not then we must set its width down
1058 if (!IS_BUS_ALIGNED(sbus
)) {
1059 dev_dbg(&pl08x
->adev
->dev
,
1060 "%s set down bus width to one byte\n",
1067 * Bytes transferred = tsize * src width, not
1070 max_bytes_per_lli
= bd
.srcbus
.buswidth
*
1071 pl08x
->vd
->max_transfer_size
;
1072 dev_vdbg(&pl08x
->adev
->dev
,
1073 "%s max bytes per lli = %zu\n",
1074 __func__
, max_bytes_per_lli
);
1077 * Make largest possible LLIs until less than one bus
1080 while (bd
.remainder
> (mbus
->buswidth
- 1)) {
1081 size_t lli_len
, tsize
, width
;
1084 * If enough left try to send max possible,
1085 * otherwise try to send the remainder
1087 lli_len
= min(bd
.remainder
, max_bytes_per_lli
);
1090 * Check against maximum bus alignment:
1091 * Calculate actual transfer size in relation to
1092 * bus width an get a maximum remainder of the
1093 * highest bus width - 1
1095 width
= max(mbus
->buswidth
, sbus
->buswidth
);
1096 lli_len
= (lli_len
/ width
) * width
;
1097 tsize
= lli_len
/ bd
.srcbus
.buswidth
;
1099 dev_vdbg(&pl08x
->adev
->dev
,
1100 "%s fill lli with single lli chunk of "
1101 "size 0x%08zx (remainder 0x%08zx)\n",
1102 __func__
, lli_len
, bd
.remainder
);
1104 cctl
= pl08x_cctl_bits(cctl
, bd
.srcbus
.buswidth
,
1105 bd
.dstbus
.buswidth
, tsize
);
1106 pl08x_fill_lli_for_desc(pl08x
, &bd
, num_llis
++,
1107 lli_len
, cctl
, tsize
);
1108 total_bytes
+= lli_len
;
1112 * Send any odd bytes
1115 dev_vdbg(&pl08x
->adev
->dev
,
1116 "%s align with boundary, send odd bytes (remain %zu)\n",
1117 __func__
, bd
.remainder
);
1118 prep_byte_width_lli(pl08x
, &bd
, &cctl
,
1119 bd
.remainder
, num_llis
++, &total_bytes
);
1123 if (total_bytes
!= dsg
->len
) {
1124 dev_err(&pl08x
->adev
->dev
,
1125 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1126 __func__
, total_bytes
, dsg
->len
);
1130 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
1131 dev_err(&pl08x
->adev
->dev
,
1132 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1133 __func__
, MAX_NUM_TSFR_LLIS
);
1138 llis_va
= txd
->llis_va
;
1139 last_lli
= llis_va
+ (num_llis
- 1) * pl08x
->lli_words
;
1142 /* Link back to the first LLI. */
1143 last_lli
[PL080_LLI_LLI
] = txd
->llis_bus
| bd
.lli_bus
;
1145 /* The final LLI terminates the LLI. */
1146 last_lli
[PL080_LLI_LLI
] = 0;
1147 /* The final LLI element shall also fire an interrupt. */
1148 last_lli
[PL080_LLI_CCTL
] |= PL080_CONTROL_TC_IRQ_EN
;
1151 pl08x_dump_lli(pl08x
, llis_va
, num_llis
);
1156 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
1157 struct pl08x_txd
*txd
)
1159 struct pl08x_sg
*dsg
, *_dsg
;
1162 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
1164 list_for_each_entry_safe(dsg
, _dsg
, &txd
->dsg_list
, node
) {
1165 list_del(&dsg
->node
);
1172 static void pl08x_desc_free(struct virt_dma_desc
*vd
)
1174 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
1175 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(vd
->tx
.chan
);
1177 dma_descriptor_unmap(&vd
->tx
);
1179 pl08x_release_mux(plchan
);
1181 pl08x_free_txd(plchan
->host
, txd
);
1184 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
1185 struct pl08x_dma_chan
*plchan
)
1189 vchan_get_all_descriptors(&plchan
->vc
, &head
);
1190 vchan_dma_desc_free_list(&plchan
->vc
, &head
);
1194 * The DMA ENGINE API
1196 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1198 /* Ensure all queued descriptors are freed */
1199 vchan_free_chan_resources(to_virt_chan(chan
));
1202 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1203 struct dma_chan
*chan
, unsigned long flags
)
1205 struct dma_async_tx_descriptor
*retval
= NULL
;
1211 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1212 * If slaves are relying on interrupts to signal completion this function
1213 * must not be called with interrupts disabled.
1215 static enum dma_status
pl08x_dma_tx_status(struct dma_chan
*chan
,
1216 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
1218 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1219 struct virt_dma_desc
*vd
;
1220 unsigned long flags
;
1221 enum dma_status ret
;
1224 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1225 if (ret
== DMA_COMPLETE
)
1229 * There's no point calculating the residue if there's
1230 * no txstate to store the value.
1233 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1238 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1239 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1240 if (ret
!= DMA_COMPLETE
) {
1241 vd
= vchan_find_desc(&plchan
->vc
, cookie
);
1243 /* On the issued list, so hasn't been processed yet */
1244 struct pl08x_txd
*txd
= to_pl08x_txd(&vd
->tx
);
1245 struct pl08x_sg
*dsg
;
1247 list_for_each_entry(dsg
, &txd
->dsg_list
, node
)
1250 bytes
= pl08x_getbytes_chan(plchan
);
1253 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1256 * This cookie not complete yet
1257 * Get number of bytes left in the active transactions and queue
1259 dma_set_residue(txstate
, bytes
);
1261 if (plchan
->state
== PL08X_CHAN_PAUSED
&& ret
== DMA_IN_PROGRESS
)
1264 /* Whether waiting or running, we're in progress */
1268 /* PrimeCell DMA extension */
1269 struct burst_table
{
1274 static const struct burst_table burst_sizes
[] = {
1277 .reg
= PL080_BSIZE_256
,
1281 .reg
= PL080_BSIZE_128
,
1285 .reg
= PL080_BSIZE_64
,
1289 .reg
= PL080_BSIZE_32
,
1293 .reg
= PL080_BSIZE_16
,
1297 .reg
= PL080_BSIZE_8
,
1301 .reg
= PL080_BSIZE_4
,
1305 .reg
= PL080_BSIZE_1
,
1310 * Given the source and destination available bus masks, select which
1311 * will be routed to each port. We try to have source and destination
1312 * on separate ports, but always respect the allowable settings.
1314 static u32
pl08x_select_bus(u8 src
, u8 dst
)
1318 if (!(dst
& PL08X_AHB1
) || ((dst
& PL08X_AHB2
) && (src
& PL08X_AHB1
)))
1319 cctl
|= PL080_CONTROL_DST_AHB2
;
1320 if (!(src
& PL08X_AHB1
) || ((src
& PL08X_AHB2
) && !(dst
& PL08X_AHB2
)))
1321 cctl
|= PL080_CONTROL_SRC_AHB2
;
1326 static u32
pl08x_cctl(u32 cctl
)
1328 cctl
&= ~(PL080_CONTROL_SRC_AHB2
| PL080_CONTROL_DST_AHB2
|
1329 PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
|
1330 PL080_CONTROL_PROT_MASK
);
1332 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1333 return cctl
| PL080_CONTROL_PROT_SYS
;
1336 static u32
pl08x_width(enum dma_slave_buswidth width
)
1339 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1340 return PL080_WIDTH_8BIT
;
1341 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1342 return PL080_WIDTH_16BIT
;
1343 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1344 return PL080_WIDTH_32BIT
;
1350 static u32
pl08x_burst(u32 maxburst
)
1354 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1355 if (burst_sizes
[i
].burstwords
<= maxburst
)
1358 return burst_sizes
[i
].reg
;
1361 static u32
pl08x_get_cctl(struct pl08x_dma_chan
*plchan
,
1362 enum dma_slave_buswidth addr_width
, u32 maxburst
)
1364 u32 width
, burst
, cctl
= 0;
1366 width
= pl08x_width(addr_width
);
1370 cctl
|= width
<< PL080_CONTROL_SWIDTH_SHIFT
;
1371 cctl
|= width
<< PL080_CONTROL_DWIDTH_SHIFT
;
1374 * If this channel will only request single transfers, set this
1375 * down to ONE element. Also select one element if no maxburst
1378 if (plchan
->cd
->single
)
1381 burst
= pl08x_burst(maxburst
);
1382 cctl
|= burst
<< PL080_CONTROL_SB_SIZE_SHIFT
;
1383 cctl
|= burst
<< PL080_CONTROL_DB_SIZE_SHIFT
;
1385 return pl08x_cctl(cctl
);
1389 * Slave transactions callback to the slave device to allow
1390 * synchronization of slave DMA signals with the DMAC enable
1392 static void pl08x_issue_pending(struct dma_chan
*chan
)
1394 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1395 unsigned long flags
;
1397 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1398 if (vchan_issue_pending(&plchan
->vc
)) {
1399 if (!plchan
->phychan
&& plchan
->state
!= PL08X_CHAN_WAITING
)
1400 pl08x_phy_alloc_and_start(plchan
);
1402 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1405 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
)
1407 struct pl08x_txd
*txd
= kzalloc(sizeof(*txd
), GFP_NOWAIT
);
1410 INIT_LIST_HEAD(&txd
->dsg_list
);
1412 /* Always enable error and terminal interrupts */
1413 txd
->ccfg
= PL080_CONFIG_ERR_IRQ_MASK
|
1414 PL080_CONFIG_TC_IRQ_MASK
;
1420 * Initialize a descriptor to be used by memcpy submit
1422 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1423 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1424 size_t len
, unsigned long flags
)
1426 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1427 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1428 struct pl08x_txd
*txd
;
1429 struct pl08x_sg
*dsg
;
1432 txd
= pl08x_get_txd(plchan
);
1434 dev_err(&pl08x
->adev
->dev
,
1435 "%s no memory for descriptor\n", __func__
);
1439 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1441 pl08x_free_txd(pl08x
, txd
);
1442 dev_err(&pl08x
->adev
->dev
, "%s no memory for pl080 sg\n",
1446 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1448 dsg
->src_addr
= src
;
1449 dsg
->dst_addr
= dest
;
1452 /* Set platform data for m2m */
1453 txd
->ccfg
|= PL080_FLOW_MEM2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1454 txd
->cctl
= pl08x
->pd
->memcpy_channel
.cctl_memcpy
&
1455 ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
1457 /* Both to be incremented or the code will break */
1458 txd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1460 if (pl08x
->vd
->dualmaster
)
1461 txd
->cctl
|= pl08x_select_bus(pl08x
->mem_buses
,
1464 ret
= pl08x_fill_llis_for_desc(plchan
->host
, txd
);
1466 pl08x_free_txd(pl08x
, txd
);
1470 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1473 static struct pl08x_txd
*pl08x_init_txd(
1474 struct dma_chan
*chan
,
1475 enum dma_transfer_direction direction
,
1476 dma_addr_t
*slave_addr
)
1478 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1479 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1480 struct pl08x_txd
*txd
;
1481 enum dma_slave_buswidth addr_width
;
1483 u8 src_buses
, dst_buses
;
1486 txd
= pl08x_get_txd(plchan
);
1488 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1493 * Set up addresses, the PrimeCell configured address
1494 * will take precedence since this may configure the
1495 * channel target address dynamically at runtime.
1497 if (direction
== DMA_MEM_TO_DEV
) {
1498 cctl
= PL080_CONTROL_SRC_INCR
;
1499 *slave_addr
= plchan
->cfg
.dst_addr
;
1500 addr_width
= plchan
->cfg
.dst_addr_width
;
1501 maxburst
= plchan
->cfg
.dst_maxburst
;
1502 src_buses
= pl08x
->mem_buses
;
1503 dst_buses
= plchan
->cd
->periph_buses
;
1504 } else if (direction
== DMA_DEV_TO_MEM
) {
1505 cctl
= PL080_CONTROL_DST_INCR
;
1506 *slave_addr
= plchan
->cfg
.src_addr
;
1507 addr_width
= plchan
->cfg
.src_addr_width
;
1508 maxburst
= plchan
->cfg
.src_maxburst
;
1509 src_buses
= plchan
->cd
->periph_buses
;
1510 dst_buses
= pl08x
->mem_buses
;
1512 pl08x_free_txd(pl08x
, txd
);
1513 dev_err(&pl08x
->adev
->dev
,
1514 "%s direction unsupported\n", __func__
);
1518 cctl
|= pl08x_get_cctl(plchan
, addr_width
, maxburst
);
1520 pl08x_free_txd(pl08x
, txd
);
1521 dev_err(&pl08x
->adev
->dev
,
1522 "DMA slave configuration botched?\n");
1526 txd
->cctl
= cctl
| pl08x_select_bus(src_buses
, dst_buses
);
1528 if (plchan
->cfg
.device_fc
)
1529 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER_PER
:
1530 PL080_FLOW_PER2MEM_PER
;
1532 tmp
= (direction
== DMA_MEM_TO_DEV
) ? PL080_FLOW_MEM2PER
:
1535 txd
->ccfg
|= tmp
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1537 ret
= pl08x_request_mux(plchan
);
1539 pl08x_free_txd(pl08x
, txd
);
1540 dev_dbg(&pl08x
->adev
->dev
,
1541 "unable to mux for transfer on %s due to platform restrictions\n",
1546 dev_dbg(&pl08x
->adev
->dev
, "allocated DMA request signal %d for xfer on %s\n",
1547 plchan
->signal
, plchan
->name
);
1549 /* Assign the flow control signal to this channel */
1550 if (direction
== DMA_MEM_TO_DEV
)
1551 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
;
1553 txd
->ccfg
|= plchan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
;
1558 static int pl08x_tx_add_sg(struct pl08x_txd
*txd
,
1559 enum dma_transfer_direction direction
,
1560 dma_addr_t slave_addr
,
1561 dma_addr_t buf_addr
,
1564 struct pl08x_sg
*dsg
;
1566 dsg
= kzalloc(sizeof(struct pl08x_sg
), GFP_NOWAIT
);
1570 list_add_tail(&dsg
->node
, &txd
->dsg_list
);
1573 if (direction
== DMA_MEM_TO_DEV
) {
1574 dsg
->src_addr
= buf_addr
;
1575 dsg
->dst_addr
= slave_addr
;
1577 dsg
->src_addr
= slave_addr
;
1578 dsg
->dst_addr
= buf_addr
;
1584 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1585 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1586 unsigned int sg_len
, enum dma_transfer_direction direction
,
1587 unsigned long flags
, void *context
)
1589 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1590 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1591 struct pl08x_txd
*txd
;
1592 struct scatterlist
*sg
;
1594 dma_addr_t slave_addr
;
1596 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1597 __func__
, sg_dma_len(sgl
), plchan
->name
);
1599 txd
= pl08x_init_txd(chan
, direction
, &slave_addr
);
1603 for_each_sg(sgl
, sg
, sg_len
, tmp
) {
1604 ret
= pl08x_tx_add_sg(txd
, direction
, slave_addr
,
1608 pl08x_release_mux(plchan
);
1609 pl08x_free_txd(pl08x
, txd
);
1610 dev_err(&pl08x
->adev
->dev
, "%s no mem for pl080 sg\n",
1616 ret
= pl08x_fill_llis_for_desc(plchan
->host
, txd
);
1618 pl08x_release_mux(plchan
);
1619 pl08x_free_txd(pl08x
, txd
);
1623 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1626 static struct dma_async_tx_descriptor
*pl08x_prep_dma_cyclic(
1627 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
1628 size_t period_len
, enum dma_transfer_direction direction
,
1629 unsigned long flags
)
1631 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1632 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1633 struct pl08x_txd
*txd
;
1635 dma_addr_t slave_addr
;
1637 dev_dbg(&pl08x
->adev
->dev
,
1638 "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n",
1639 __func__
, period_len
, buf_len
,
1640 direction
== DMA_MEM_TO_DEV
? "to" : "from",
1643 txd
= pl08x_init_txd(chan
, direction
, &slave_addr
);
1648 txd
->cctl
|= PL080_CONTROL_TC_IRQ_EN
;
1649 for (tmp
= 0; tmp
< buf_len
; tmp
+= period_len
) {
1650 ret
= pl08x_tx_add_sg(txd
, direction
, slave_addr
,
1651 buf_addr
+ tmp
, period_len
);
1653 pl08x_release_mux(plchan
);
1654 pl08x_free_txd(pl08x
, txd
);
1659 ret
= pl08x_fill_llis_for_desc(plchan
->host
, txd
);
1661 pl08x_release_mux(plchan
);
1662 pl08x_free_txd(pl08x
, txd
);
1666 return vchan_tx_prep(&plchan
->vc
, &txd
->vd
, flags
);
1669 static int pl08x_config(struct dma_chan
*chan
,
1670 struct dma_slave_config
*config
)
1672 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1673 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1678 /* Reject definitely invalid configurations */
1679 if (config
->src_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
||
1680 config
->dst_addr_width
== DMA_SLAVE_BUSWIDTH_8_BYTES
)
1683 if (config
->device_fc
&& pl08x
->vd
->pl080s
) {
1684 dev_err(&pl08x
->adev
->dev
,
1685 "%s: PL080S does not support peripheral flow control\n",
1690 plchan
->cfg
= *config
;
1695 static int pl08x_terminate_all(struct dma_chan
*chan
)
1697 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1698 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1699 unsigned long flags
;
1701 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1702 if (!plchan
->phychan
&& !plchan
->at
) {
1703 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1707 plchan
->state
= PL08X_CHAN_IDLE
;
1709 if (plchan
->phychan
) {
1711 * Mark physical channel as free and free any slave
1714 pl08x_phy_free(plchan
);
1716 /* Dequeue jobs and free LLIs */
1718 pl08x_desc_free(&plchan
->at
->vd
);
1721 /* Dequeue jobs not yet fired as well */
1722 pl08x_free_txd_list(pl08x
, plchan
);
1724 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1729 static int pl08x_pause(struct dma_chan
*chan
)
1731 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1732 unsigned long flags
;
1735 * Anything succeeds on channels with no physical allocation and
1736 * no queued transfers.
1738 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1739 if (!plchan
->phychan
&& !plchan
->at
) {
1740 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1744 pl08x_pause_phy_chan(plchan
->phychan
);
1745 plchan
->state
= PL08X_CHAN_PAUSED
;
1747 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1752 static int pl08x_resume(struct dma_chan
*chan
)
1754 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1755 unsigned long flags
;
1758 * Anything succeeds on channels with no physical allocation and
1759 * no queued transfers.
1761 spin_lock_irqsave(&plchan
->vc
.lock
, flags
);
1762 if (!plchan
->phychan
&& !plchan
->at
) {
1763 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1767 pl08x_resume_phy_chan(plchan
->phychan
);
1768 plchan
->state
= PL08X_CHAN_RUNNING
;
1770 spin_unlock_irqrestore(&plchan
->vc
.lock
, flags
);
1775 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1777 struct pl08x_dma_chan
*plchan
;
1778 char *name
= chan_id
;
1780 /* Reject channels for devices not bound to this driver */
1781 if (chan
->device
->dev
->driver
!= &pl08x_amba_driver
.drv
)
1784 plchan
= to_pl08x_chan(chan
);
1786 /* Check that the channel is not taken! */
1787 if (!strcmp(plchan
->name
, name
))
1792 EXPORT_SYMBOL_GPL(pl08x_filter_id
);
1795 * Just check that the device is there and active
1796 * TODO: turn this bit on/off depending on the number of physical channels
1797 * actually used, if it is zero... well shut it off. That will save some
1798 * power. Cut the clock at the same time.
1800 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1802 /* The Nomadik variant does not have the config register */
1803 if (pl08x
->vd
->nomadik
)
1805 writel(PL080_CONFIG_ENABLE
, pl08x
->base
+ PL080_CONFIG
);
1808 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1810 struct pl08x_driver_data
*pl08x
= dev
;
1811 u32 mask
= 0, err
, tc
, i
;
1813 /* check & clear - ERR & TC interrupts */
1814 err
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1816 dev_err(&pl08x
->adev
->dev
, "%s error interrupt, register value 0x%08x\n",
1818 writel(err
, pl08x
->base
+ PL080_ERR_CLEAR
);
1820 tc
= readl(pl08x
->base
+ PL080_TC_STATUS
);
1822 writel(tc
, pl08x
->base
+ PL080_TC_CLEAR
);
1827 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1828 if (((1 << i
) & err
) || ((1 << i
) & tc
)) {
1829 /* Locate physical channel */
1830 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1831 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1832 struct pl08x_txd
*tx
;
1835 dev_err(&pl08x
->adev
->dev
,
1836 "%s Error TC interrupt on unused channel: 0x%08x\n",
1841 spin_lock(&plchan
->vc
.lock
);
1843 if (tx
&& tx
->cyclic
) {
1844 vchan_cyclic_callback(&tx
->vd
);
1848 * This descriptor is done, release its mux
1851 pl08x_release_mux(plchan
);
1853 vchan_cookie_complete(&tx
->vd
);
1856 * And start the next descriptor (if any),
1857 * otherwise free this channel.
1859 if (vchan_next_desc(&plchan
->vc
))
1860 pl08x_start_next_txd(plchan
);
1862 pl08x_phy_free(plchan
);
1864 spin_unlock(&plchan
->vc
.lock
);
1870 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1873 static void pl08x_dma_slave_init(struct pl08x_dma_chan
*chan
)
1876 chan
->name
= chan
->cd
->bus_id
;
1877 chan
->cfg
.src_addr
= chan
->cd
->addr
;
1878 chan
->cfg
.dst_addr
= chan
->cd
->addr
;
1882 * Initialise the DMAC memcpy/slave channels.
1883 * Make a local wrapper to hold required data
1885 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1886 struct dma_device
*dmadev
, unsigned int channels
, bool slave
)
1888 struct pl08x_dma_chan
*chan
;
1891 INIT_LIST_HEAD(&dmadev
->channels
);
1894 * Register as many many memcpy as we have physical channels,
1895 * we won't always be able to use all but the code will have
1896 * to cope with that situation.
1898 for (i
= 0; i
< channels
; i
++) {
1899 chan
= kzalloc(sizeof(*chan
), GFP_KERNEL
);
1901 dev_err(&pl08x
->adev
->dev
,
1902 "%s no memory for channel\n", __func__
);
1907 chan
->state
= PL08X_CHAN_IDLE
;
1911 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1912 pl08x_dma_slave_init(chan
);
1914 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1915 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1921 dev_dbg(&pl08x
->adev
->dev
,
1922 "initialize virtual channel \"%s\"\n",
1925 chan
->vc
.desc_free
= pl08x_desc_free
;
1926 vchan_init(&chan
->vc
, dmadev
);
1928 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1929 i
, slave
? "slave" : "memcpy");
1933 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1935 struct pl08x_dma_chan
*chan
= NULL
;
1936 struct pl08x_dma_chan
*next
;
1938 list_for_each_entry_safe(chan
,
1939 next
, &dmadev
->channels
, vc
.chan
.device_node
) {
1940 list_del(&chan
->vc
.chan
.device_node
);
1945 #ifdef CONFIG_DEBUG_FS
1946 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1949 case PL08X_CHAN_IDLE
:
1951 case PL08X_CHAN_RUNNING
:
1953 case PL08X_CHAN_PAUSED
:
1955 case PL08X_CHAN_WAITING
:
1960 return "UNKNOWN STATE";
1963 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1965 struct pl08x_driver_data
*pl08x
= s
->private;
1966 struct pl08x_dma_chan
*chan
;
1967 struct pl08x_phy_chan
*ch
;
1968 unsigned long flags
;
1971 seq_printf(s
, "PL08x physical channels:\n");
1972 seq_printf(s
, "CHANNEL:\tUSER:\n");
1973 seq_printf(s
, "--------\t-----\n");
1974 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1975 struct pl08x_dma_chan
*virt_chan
;
1977 ch
= &pl08x
->phy_chans
[i
];
1979 spin_lock_irqsave(&ch
->lock
, flags
);
1980 virt_chan
= ch
->serving
;
1982 seq_printf(s
, "%d\t\t%s%s\n",
1984 virt_chan
? virt_chan
->name
: "(none)",
1985 ch
->locked
? " LOCKED" : "");
1987 spin_unlock_irqrestore(&ch
->lock
, flags
);
1990 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1991 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1992 seq_printf(s
, "--------\t------\n");
1993 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, vc
.chan
.device_node
) {
1994 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1995 pl08x_state_str(chan
->state
));
1998 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1999 seq_printf(s
, "CHANNEL:\tSTATE:\n");
2000 seq_printf(s
, "--------\t------\n");
2001 list_for_each_entry(chan
, &pl08x
->slave
.channels
, vc
.chan
.device_node
) {
2002 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
2003 pl08x_state_str(chan
->state
));
2009 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
2011 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
2014 static const struct file_operations pl08x_debugfs_operations
= {
2015 .open
= pl08x_debugfs_open
,
2017 .llseek
= seq_lseek
,
2018 .release
= single_release
,
2021 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
2023 /* Expose a simple debugfs interface to view all clocks */
2024 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
),
2025 S_IFREG
| S_IRUGO
, NULL
, pl08x
,
2026 &pl08x_debugfs_operations
);
2030 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
2036 static struct dma_chan
*pl08x_find_chan_id(struct pl08x_driver_data
*pl08x
,
2039 struct pl08x_dma_chan
*chan
;
2041 list_for_each_entry(chan
, &pl08x
->slave
.channels
, vc
.chan
.device_node
) {
2042 if (chan
->signal
== id
)
2043 return &chan
->vc
.chan
;
2049 static struct dma_chan
*pl08x_of_xlate(struct of_phandle_args
*dma_spec
,
2050 struct of_dma
*ofdma
)
2052 struct pl08x_driver_data
*pl08x
= ofdma
->of_dma_data
;
2053 struct pl08x_channel_data
*data
;
2054 struct pl08x_dma_chan
*chan
;
2055 struct dma_chan
*dma_chan
;
2060 if (dma_spec
->args_count
!= 2)
2063 dma_chan
= pl08x_find_chan_id(pl08x
, dma_spec
->args
[0]);
2065 return dma_get_slave_channel(dma_chan
);
2067 chan
= devm_kzalloc(pl08x
->slave
.dev
, sizeof(*chan
) + sizeof(*data
),
2072 data
= (void *)&chan
[1];
2073 data
->bus_id
= "(none)";
2074 data
->periph_buses
= dma_spec
->args
[1];
2079 chan
->name
= data
->bus_id
;
2080 chan
->state
= PL08X_CHAN_IDLE
;
2081 chan
->signal
= dma_spec
->args
[0];
2082 chan
->vc
.desc_free
= pl08x_desc_free
;
2084 vchan_init(&chan
->vc
, &pl08x
->slave
);
2086 return dma_get_slave_channel(&chan
->vc
.chan
);
2089 static int pl08x_of_probe(struct amba_device
*adev
,
2090 struct pl08x_driver_data
*pl08x
,
2091 struct device_node
*np
)
2093 struct pl08x_platform_data
*pd
;
2094 u32 cctl_memcpy
= 0;
2098 pd
= devm_kzalloc(&adev
->dev
, sizeof(*pd
), GFP_KERNEL
);
2102 /* Eligible bus masters for fetching LLIs */
2103 if (of_property_read_bool(np
, "lli-bus-interface-ahb1"))
2104 pd
->lli_buses
|= PL08X_AHB1
;
2105 if (of_property_read_bool(np
, "lli-bus-interface-ahb2"))
2106 pd
->lli_buses
|= PL08X_AHB2
;
2107 if (!pd
->lli_buses
) {
2108 dev_info(&adev
->dev
, "no bus masters for LLIs stated, assume all\n");
2109 pd
->lli_buses
|= PL08X_AHB1
| PL08X_AHB2
;
2112 /* Eligible bus masters for memory access */
2113 if (of_property_read_bool(np
, "mem-bus-interface-ahb1"))
2114 pd
->mem_buses
|= PL08X_AHB1
;
2115 if (of_property_read_bool(np
, "mem-bus-interface-ahb2"))
2116 pd
->mem_buses
|= PL08X_AHB2
;
2117 if (!pd
->mem_buses
) {
2118 dev_info(&adev
->dev
, "no bus masters for memory stated, assume all\n");
2119 pd
->mem_buses
|= PL08X_AHB1
| PL08X_AHB2
;
2122 /* Parse the memcpy channel properties */
2123 ret
= of_property_read_u32(np
, "memcpy-burst-size", &val
);
2125 dev_info(&adev
->dev
, "no memcpy burst size specified, using 1 byte\n");
2130 dev_err(&adev
->dev
, "illegal burst size for memcpy, set to 1\n");
2133 cctl_memcpy
|= PL080_BSIZE_1
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2134 PL080_BSIZE_1
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2137 cctl_memcpy
|= PL080_BSIZE_4
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2138 PL080_BSIZE_4
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2141 cctl_memcpy
|= PL080_BSIZE_8
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2142 PL080_BSIZE_8
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2145 cctl_memcpy
|= PL080_BSIZE_16
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2146 PL080_BSIZE_16
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2149 cctl_memcpy
|= PL080_BSIZE_32
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2150 PL080_BSIZE_32
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2153 cctl_memcpy
|= PL080_BSIZE_64
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2154 PL080_BSIZE_64
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2157 cctl_memcpy
|= PL080_BSIZE_128
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2158 PL080_BSIZE_128
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2161 cctl_memcpy
|= PL080_BSIZE_256
<< PL080_CONTROL_SB_SIZE_SHIFT
|
2162 PL080_BSIZE_256
<< PL080_CONTROL_DB_SIZE_SHIFT
;
2166 ret
= of_property_read_u32(np
, "memcpy-bus-width", &val
);
2168 dev_info(&adev
->dev
, "no memcpy bus width specified, using 8 bits\n");
2173 dev_err(&adev
->dev
, "illegal bus width for memcpy, set to 8 bits\n");
2176 cctl_memcpy
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
|
2177 PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
2180 cctl_memcpy
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
|
2181 PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
2184 cctl_memcpy
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
|
2185 PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
2189 /* This is currently the only thing making sense */
2190 cctl_memcpy
|= PL080_CONTROL_PROT_SYS
;
2192 /* Set up memcpy channel */
2193 pd
->memcpy_channel
.bus_id
= "memcpy";
2194 pd
->memcpy_channel
.cctl_memcpy
= cctl_memcpy
;
2195 /* Use the buses that can access memory, obviously */
2196 pd
->memcpy_channel
.periph_buses
= pd
->mem_buses
;
2200 return of_dma_controller_register(adev
->dev
.of_node
, pl08x_of_xlate
,
2204 static inline int pl08x_of_probe(struct amba_device
*adev
,
2205 struct pl08x_driver_data
*pl08x
,
2206 struct device_node
*np
)
2212 static int pl08x_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2214 struct pl08x_driver_data
*pl08x
;
2215 const struct vendor_data
*vd
= id
->data
;
2216 struct device_node
*np
= adev
->dev
.of_node
;
2221 ret
= amba_request_regions(adev
, NULL
);
2225 /* Ensure that we can do DMA */
2226 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2230 /* Create the driver state holder */
2231 pl08x
= kzalloc(sizeof(*pl08x
), GFP_KERNEL
);
2237 /* Initialize memcpy engine */
2238 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
2239 pl08x
->memcpy
.dev
= &adev
->dev
;
2240 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
2241 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
2242 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
2243 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
2244 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
2245 pl08x
->memcpy
.device_config
= pl08x_config
;
2246 pl08x
->memcpy
.device_pause
= pl08x_pause
;
2247 pl08x
->memcpy
.device_resume
= pl08x_resume
;
2248 pl08x
->memcpy
.device_terminate_all
= pl08x_terminate_all
;
2249 pl08x
->memcpy
.src_addr_widths
= PL80X_DMA_BUSWIDTHS
;
2250 pl08x
->memcpy
.dst_addr_widths
= PL80X_DMA_BUSWIDTHS
;
2251 pl08x
->memcpy
.directions
= BIT(DMA_MEM_TO_MEM
);
2252 pl08x
->memcpy
.residue_granularity
= DMA_RESIDUE_GRANULARITY_SEGMENT
;
2254 /* Initialize slave engine */
2255 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
2256 dma_cap_set(DMA_CYCLIC
, pl08x
->slave
.cap_mask
);
2257 pl08x
->slave
.dev
= &adev
->dev
;
2258 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
2259 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
2260 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
2261 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
2262 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
2263 pl08x
->slave
.device_prep_dma_cyclic
= pl08x_prep_dma_cyclic
;
2264 pl08x
->slave
.device_config
= pl08x_config
;
2265 pl08x
->slave
.device_pause
= pl08x_pause
;
2266 pl08x
->slave
.device_resume
= pl08x_resume
;
2267 pl08x
->slave
.device_terminate_all
= pl08x_terminate_all
;
2268 pl08x
->slave
.src_addr_widths
= PL80X_DMA_BUSWIDTHS
;
2269 pl08x
->slave
.dst_addr_widths
= PL80X_DMA_BUSWIDTHS
;
2270 pl08x
->slave
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2271 pl08x
->slave
.residue_granularity
= DMA_RESIDUE_GRANULARITY_SEGMENT
;
2273 /* Get the platform data */
2274 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
2277 ret
= pl08x_of_probe(adev
, pl08x
, np
);
2279 goto out_no_platdata
;
2281 dev_err(&adev
->dev
, "no platform data supplied\n");
2283 goto out_no_platdata
;
2287 /* Assign useful pointers to the driver state */
2291 /* By default, AHB1 only. If dualmaster, from platform */
2292 pl08x
->lli_buses
= PL08X_AHB1
;
2293 pl08x
->mem_buses
= PL08X_AHB1
;
2294 if (pl08x
->vd
->dualmaster
) {
2295 pl08x
->lli_buses
= pl08x
->pd
->lli_buses
;
2296 pl08x
->mem_buses
= pl08x
->pd
->mem_buses
;
2300 pl08x
->lli_words
= PL080S_LLI_WORDS
;
2302 pl08x
->lli_words
= PL080_LLI_WORDS
;
2303 tsfr_size
= MAX_NUM_TSFR_LLIS
* pl08x
->lli_words
* sizeof(u32
);
2305 /* A DMA memory pool for LLIs, align on 1-byte boundary */
2306 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
2307 tsfr_size
, PL08X_ALIGN
, 0);
2310 goto out_no_lli_pool
;
2313 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2316 goto out_no_ioremap
;
2319 /* Turn on the PL08x */
2320 pl08x_ensure_on(pl08x
);
2322 /* Attach the interrupt handler */
2323 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
2324 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
2326 ret
= request_irq(adev
->irq
[0], pl08x_irq
, 0, DRIVER_NAME
, pl08x
);
2328 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
2329 __func__
, adev
->irq
[0]);
2333 /* Initialize physical channels */
2334 pl08x
->phy_chans
= kzalloc((vd
->channels
* sizeof(*pl08x
->phy_chans
)),
2336 if (!pl08x
->phy_chans
) {
2337 dev_err(&adev
->dev
, "%s failed to allocate "
2338 "physical channel holders\n",
2341 goto out_no_phychans
;
2344 for (i
= 0; i
< vd
->channels
; i
++) {
2345 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
2348 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
2349 ch
->reg_config
= ch
->base
+ vd
->config_offset
;
2350 spin_lock_init(&ch
->lock
);
2353 * Nomadik variants can have channels that are locked
2354 * down for the secure world only. Lock up these channels
2355 * by perpetually serving a dummy virtual channel.
2360 val
= readl(ch
->reg_config
);
2361 if (val
& (PL080N_CONFIG_ITPROT
| PL080N_CONFIG_SECPROT
)) {
2362 dev_info(&adev
->dev
, "physical channel %d reserved for secure access only\n", i
);
2367 dev_dbg(&adev
->dev
, "physical channel %d is %s\n",
2368 i
, pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
2371 /* Register as many memcpy channels as there are physical channels */
2372 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
2373 pl08x
->vd
->channels
, false);
2375 dev_warn(&pl08x
->adev
->dev
,
2376 "%s failed to enumerate memcpy channels - %d\n",
2381 /* Register slave channels */
2382 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2383 pl08x
->pd
->num_slave_channels
, true);
2385 dev_warn(&pl08x
->adev
->dev
,
2386 "%s failed to enumerate slave channels - %d\n",
2391 ret
= dma_async_device_register(&pl08x
->memcpy
);
2393 dev_warn(&pl08x
->adev
->dev
,
2394 "%s failed to register memcpy as an async device - %d\n",
2396 goto out_no_memcpy_reg
;
2399 ret
= dma_async_device_register(&pl08x
->slave
);
2401 dev_warn(&pl08x
->adev
->dev
,
2402 "%s failed to register slave as an async device - %d\n",
2404 goto out_no_slave_reg
;
2407 amba_set_drvdata(adev
, pl08x
);
2408 init_pl08x_debugfs(pl08x
);
2409 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n",
2410 amba_part(adev
), pl08x
->vd
->pl080s
? "s" : "", amba_rev(adev
),
2411 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2416 dma_async_device_unregister(&pl08x
->memcpy
);
2418 pl08x_free_virtual_channels(&pl08x
->slave
);
2420 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2422 kfree(pl08x
->phy_chans
);
2424 free_irq(adev
->irq
[0], pl08x
);
2426 iounmap(pl08x
->base
);
2428 dma_pool_destroy(pl08x
->pool
);
2433 amba_release_regions(adev
);
2437 /* PL080 has 8 channels and the PL080 have just 2 */
2438 static struct vendor_data vendor_pl080
= {
2439 .config_offset
= PL080_CH_CONFIG
,
2442 .max_transfer_size
= PL080_CONTROL_TRANSFER_SIZE_MASK
,
2445 static struct vendor_data vendor_nomadik
= {
2446 .config_offset
= PL080_CH_CONFIG
,
2450 .max_transfer_size
= PL080_CONTROL_TRANSFER_SIZE_MASK
,
2453 static struct vendor_data vendor_pl080s
= {
2454 .config_offset
= PL080S_CH_CONFIG
,
2457 .max_transfer_size
= PL080S_CONTROL_TRANSFER_SIZE_MASK
,
2460 static struct vendor_data vendor_pl081
= {
2461 .config_offset
= PL080_CH_CONFIG
,
2463 .dualmaster
= false,
2464 .max_transfer_size
= PL080_CONTROL_TRANSFER_SIZE_MASK
,
2467 static struct amba_id pl08x_ids
[] = {
2468 /* Samsung PL080S variant */
2472 .data
= &vendor_pl080s
,
2478 .data
= &vendor_pl080
,
2484 .data
= &vendor_pl081
,
2486 /* Nomadik 8815 PL080 variant */
2490 .data
= &vendor_nomadik
,
2495 MODULE_DEVICE_TABLE(amba
, pl08x_ids
);
2497 static struct amba_driver pl08x_amba_driver
= {
2498 .drv
.name
= DRIVER_NAME
,
2499 .id_table
= pl08x_ids
,
2500 .probe
= pl08x_probe
,
2503 static int __init
pl08x_init(void)
2506 retval
= amba_driver_register(&pl08x_amba_driver
);
2508 printk(KERN_WARNING DRIVER_NAME
2509 "failed to register as an AMBA device (%d)\n",
2513 subsys_initcall(pl08x_init
);