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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / edac / i5100_edac.c
blob40917775dca1c84fa2f84acbea9a988ec94060e3
1 /*
2 * Intel 5100 Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * This module is based on the following document:
8 *
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
11 *
12 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
14 * rows for each respective channel are laid out one after another,
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
17 *
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
19 * several ranks. However, instead of showing memories as ranks, it outputs
20 * them as DIMM's. An internal table creates the association between ranks
21 * and DIMM's.
22 */
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/edac.h>
28 #include <linux/delay.h>
29 #include <linux/mmzone.h>
30 #include <linux/debugfs.h>
31
32 #include "edac_core.h"
33 #include "edac_module.h"
34
35 /* register addresses */
36
37 /* device 16, func 1 */
38 #define I5100_MC 0x40 /* Memory Control Register */
39 #define I5100_MC_SCRBEN_MASK (1 << 7)
40 #define I5100_MC_SCRBDONE_MASK (1 << 4)
41 #define I5100_MS 0x44 /* Memory Status Register */
42 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
43 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
44 #define I5100_TOLM 0x6c /* Top of Low Memory */
45 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
46 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
47 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
48 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
49 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
50 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
51 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
52 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
53 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
54 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
55 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
56 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
57 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
58 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
59 #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
60 #define I5100_FERR_NF_MEM_ANY_MASK \
61 (I5100_FERR_NF_MEM_M16ERR_MASK | \
62 I5100_FERR_NF_MEM_M15ERR_MASK | \
63 I5100_FERR_NF_MEM_M14ERR_MASK | \
64 I5100_FERR_NF_MEM_M12ERR_MASK | \
65 I5100_FERR_NF_MEM_M11ERR_MASK | \
66 I5100_FERR_NF_MEM_M10ERR_MASK | \
67 I5100_FERR_NF_MEM_M6ERR_MASK | \
68 I5100_FERR_NF_MEM_M5ERR_MASK | \
69 I5100_FERR_NF_MEM_M4ERR_MASK | \
70 I5100_FERR_NF_MEM_M1ERR_MASK)
71 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
72 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
73 #define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */
74 #define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */
75 #define I5100_MEMXEINJMSK0_EINJEN (1 << 27)
76 #define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */
77 #define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */
78
79 /* Device 19, Function 0 */
80 #define I5100_DINJ0 0x9a
81
82 /* device 21 and 22, func 0 */
83 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
84 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
85 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */
86 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
87 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
88 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
89 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
90 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
91 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
92 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
93
94 /* bit field accessors */
95
96 static inline u32 i5100_mc_scrben(u32 mc)
97 {
98 return mc >> 7 & 1;
99 }
100
101 static inline u32 i5100_mc_errdeten(u32 mc)
102 {
103 return mc >> 5 & 1;
104 }
105
106 static inline u32 i5100_mc_scrbdone(u32 mc)
107 {
108 return mc >> 4 & 1;
109 }
110
111 static inline u16 i5100_spddata_rdo(u16 a)
112 {
113 return a >> 15 & 1;
114 }
115
116 static inline u16 i5100_spddata_sbe(u16 a)
117 {
118 return a >> 13 & 1;
119 }
120
121 static inline u16 i5100_spddata_busy(u16 a)
122 {
123 return a >> 12 & 1;
124 }
125
126 static inline u16 i5100_spddata_data(u16 a)
127 {
128 return a & ((1 << 8) - 1);
129 }
130
131 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
132 u32 data, u32 cmd)
133 {
134 return ((dti & ((1 << 4) - 1)) << 28) |
135 ((ckovrd & 1) << 27) |
136 ((sa & ((1 << 3) - 1)) << 24) |
137 ((ba & ((1 << 8) - 1)) << 16) |
138 ((data & ((1 << 8) - 1)) << 8) |
139 (cmd & 1);
140 }
141
142 static inline u16 i5100_tolm_tolm(u16 a)
143 {
144 return a >> 12 & ((1 << 4) - 1);
145 }
146
147 static inline u16 i5100_mir_limit(u16 a)
148 {
149 return a >> 4 & ((1 << 12) - 1);
150 }
151
152 static inline u16 i5100_mir_way1(u16 a)
153 {
154 return a >> 1 & 1;
155 }
156
157 static inline u16 i5100_mir_way0(u16 a)
158 {
159 return a & 1;
160 }
161
162 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
163 {
164 return a >> 28 & 1;
165 }
166
167 static inline u32 i5100_ferr_nf_mem_any(u32 a)
168 {
169 return a & I5100_FERR_NF_MEM_ANY_MASK;
170 }
171
172 static inline u32 i5100_nerr_nf_mem_any(u32 a)
173 {
174 return i5100_ferr_nf_mem_any(a);
175 }
176
177 static inline u32 i5100_dmir_limit(u32 a)
178 {
179 return a >> 16 & ((1 << 11) - 1);
180 }
181
182 static inline u32 i5100_dmir_rank(u32 a, u32 i)
183 {
184 return a >> (4 * i) & ((1 << 2) - 1);
185 }
186
187 static inline u16 i5100_mtr_present(u16 a)
188 {
189 return a >> 10 & 1;
190 }
191
192 static inline u16 i5100_mtr_ethrottle(u16 a)
193 {
194 return a >> 9 & 1;
195 }
196
197 static inline u16 i5100_mtr_width(u16 a)
198 {
199 return a >> 8 & 1;
200 }
201
202 static inline u16 i5100_mtr_numbank(u16 a)
203 {
204 return a >> 6 & 1;
205 }
206
207 static inline u16 i5100_mtr_numrow(u16 a)
208 {
209 return a >> 2 & ((1 << 2) - 1);
210 }
211
212 static inline u16 i5100_mtr_numcol(u16 a)
213 {
214 return a & ((1 << 2) - 1);
215 }
216
217
218 static inline u32 i5100_validlog_redmemvalid(u32 a)
219 {
220 return a >> 2 & 1;
221 }
222
223 static inline u32 i5100_validlog_recmemvalid(u32 a)
224 {
225 return a >> 1 & 1;
226 }
227
228 static inline u32 i5100_validlog_nrecmemvalid(u32 a)
229 {
230 return a & 1;
231 }
232
233 static inline u32 i5100_nrecmema_merr(u32 a)
234 {
235 return a >> 15 & ((1 << 5) - 1);
236 }
237
238 static inline u32 i5100_nrecmema_bank(u32 a)
239 {
240 return a >> 12 & ((1 << 3) - 1);
241 }
242
243 static inline u32 i5100_nrecmema_rank(u32 a)
244 {
245 return a >> 8 & ((1 << 3) - 1);
246 }
247
248 static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
249 {
250 return a & ((1 << 8) - 1);
251 }
252
253 static inline u32 i5100_nrecmemb_cas(u32 a)
254 {
255 return a >> 16 & ((1 << 13) - 1);
256 }
257
258 static inline u32 i5100_nrecmemb_ras(u32 a)
259 {
260 return a & ((1 << 16) - 1);
261 }
262
263 static inline u32 i5100_redmemb_ecc_locator(u32 a)
264 {
265 return a & ((1 << 18) - 1);
266 }
267
268 static inline u32 i5100_recmema_merr(u32 a)
269 {
270 return i5100_nrecmema_merr(a);
271 }
272
273 static inline u32 i5100_recmema_bank(u32 a)
274 {
275 return i5100_nrecmema_bank(a);
276 }
277
278 static inline u32 i5100_recmema_rank(u32 a)
279 {
280 return i5100_nrecmema_rank(a);
281 }
282
283 static inline u32 i5100_recmemb_cas(u32 a)
284 {
285 return i5100_nrecmemb_cas(a);
286 }
287
288 static inline u32 i5100_recmemb_ras(u32 a)
289 {
290 return i5100_nrecmemb_ras(a);
291 }
292
293 /* some generic limits */
294 #define I5100_MAX_RANKS_PER_CHAN 6
295 #define I5100_CHANNELS 2
296 #define I5100_MAX_RANKS_PER_DIMM 4
297 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
298 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
299 #define I5100_MAX_RANK_INTERLEAVE 4
300 #define I5100_MAX_DMIRS 5
301 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
302
303 struct i5100_priv {
304 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
305 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
306
307 /*
308 * mainboard chip select map -- maps i5100 chip selects to
309 * DIMM slot chip selects. In the case of only 4 ranks per
310 * channel, the mapping is fairly obvious but not unique.
311 * we map -1 -> NC and assume both channels use the same
312 * map...
313 *
314 */
315 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
316
317 /* memory interleave range */
318 struct {
319 u64 limit;
320 unsigned way[2];
321 } mir[I5100_CHANNELS];
322
323 /* adjusted memory interleave range register */
324 unsigned amir[I5100_CHANNELS];
325
326 /* dimm interleave range */
327 struct {
328 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
329 u64 limit;
330 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
331
332 /* memory technology registers... */
333 struct {
334 unsigned present; /* 0 or 1 */
335 unsigned ethrottle; /* 0 or 1 */
336 unsigned width; /* 4 or 8 bits */
337 unsigned numbank; /* 2 or 3 lines */
338 unsigned numrow; /* 13 .. 16 lines */
339 unsigned numcol; /* 11 .. 12 lines */
340 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
341
342 u64 tolm; /* top of low memory in bytes */
343 unsigned ranksperchan; /* number of ranks per channel */
344
345 struct pci_dev *mc; /* device 16 func 1 */
346 struct pci_dev *einj; /* device 19 func 0 */
347 struct pci_dev *ch0mm; /* device 21 func 0 */
348 struct pci_dev *ch1mm; /* device 22 func 0 */
349
350 struct delayed_work i5100_scrubbing;
351 int scrub_enable;
352
353 /* Error injection */
354 u8 inject_channel;
355 u8 inject_hlinesel;
356 u8 inject_deviceptr1;
357 u8 inject_deviceptr2;
358 u16 inject_eccmask1;
359 u16 inject_eccmask2;
360
361 struct dentry *debugfs;
362 };
363
364 static struct dentry *i5100_debugfs;
365
366 /* map a rank/chan to a slot number on the mainboard */
367 static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
368 int chan, int rank)
369 {
370 const struct i5100_priv *priv = mci->pvt_info;
371 int i;
372
373 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
374 int j;
375 const int numrank = priv->dimm_numrank[chan][i];
376
377 for (j = 0; j < numrank; j++)
378 if (priv->dimm_csmap[i][j] == rank)
379 return i * 2 + chan;
380 }
381
382 return -1;
383 }
384
385 static const char *i5100_err_msg(unsigned err)
386 {
387 static const char *merrs[] = {
388 "unknown", /* 0 */
389 "uncorrectable data ECC on replay", /* 1 */
390 "unknown", /* 2 */
391 "unknown", /* 3 */
392 "aliased uncorrectable demand data ECC", /* 4 */
393 "aliased uncorrectable spare-copy data ECC", /* 5 */
394 "aliased uncorrectable patrol data ECC", /* 6 */
395 "unknown", /* 7 */
396 "unknown", /* 8 */
397 "unknown", /* 9 */
398 "non-aliased uncorrectable demand data ECC", /* 10 */
399 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
400 "non-aliased uncorrectable patrol data ECC", /* 12 */
401 "unknown", /* 13 */
402 "correctable demand data ECC", /* 14 */
403 "correctable spare-copy data ECC", /* 15 */
404 "correctable patrol data ECC", /* 16 */
405 "unknown", /* 17 */
406 "SPD protocol error", /* 18 */
407 "unknown", /* 19 */
408 "spare copy initiated", /* 20 */
409 "spare copy completed", /* 21 */
410 };
411 unsigned i;
412
413 for (i = 0; i < ARRAY_SIZE(merrs); i++)
414 if (1 << i & err)
415 return merrs[i];
416
417 return "none";
418 }
419
420 /* convert csrow index into a rank (per channel -- 0..5) */
421 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
422 {
423 const struct i5100_priv *priv = mci->pvt_info;
424
425 return csrow % priv->ranksperchan;
426 }
427
428 /* convert csrow index into a channel (0..1) */
429 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
430 {
431 const struct i5100_priv *priv = mci->pvt_info;
432
433 return csrow / priv->ranksperchan;
434 }
435
436 static void i5100_handle_ce(struct mem_ctl_info *mci,
437 int chan,
438 unsigned bank,
439 unsigned rank,
440 unsigned long syndrome,
441 unsigned cas,
442 unsigned ras,
443 const char *msg)
444 {
445 char detail[80];
446
447 /* Form out message */
448 snprintf(detail, sizeof(detail),
449 "bank %u, cas %u, ras %u\n",
450 bank, cas, ras);
451
452 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
453 0, 0, syndrome,
454 chan, rank, -1,
455 msg, detail);
456 }
457
458 static void i5100_handle_ue(struct mem_ctl_info *mci,
459 int chan,
460 unsigned bank,
461 unsigned rank,
462 unsigned long syndrome,
463 unsigned cas,
464 unsigned ras,
465 const char *msg)
466 {
467 char detail[80];
468
469 /* Form out message */
470 snprintf(detail, sizeof(detail),
471 "bank %u, cas %u, ras %u\n",
472 bank, cas, ras);
473
474 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
475 0, 0, syndrome,
476 chan, rank, -1,
477 msg, detail);
478 }
479
480 static void i5100_read_log(struct mem_ctl_info *mci, int chan,
481 u32 ferr, u32 nerr)
482 {
483 struct i5100_priv *priv = mci->pvt_info;
484 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
485 u32 dw;
486 u32 dw2;
487 unsigned syndrome = 0;
488 unsigned ecc_loc = 0;
489 unsigned merr;
490 unsigned bank;
491 unsigned rank;
492 unsigned cas;
493 unsigned ras;
494
495 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
496
497 if (i5100_validlog_redmemvalid(dw)) {
498 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
499 syndrome = dw2;
500 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
501 ecc_loc = i5100_redmemb_ecc_locator(dw2);
502 }
503
504 if (i5100_validlog_recmemvalid(dw)) {
505 const char *msg;
506
507 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
508 merr = i5100_recmema_merr(dw2);
509 bank = i5100_recmema_bank(dw2);
510 rank = i5100_recmema_rank(dw2);
511
512 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
513 cas = i5100_recmemb_cas(dw2);
514 ras = i5100_recmemb_ras(dw2);
515
516 /* FIXME: not really sure if this is what merr is...
517 */
518 if (!merr)
519 msg = i5100_err_msg(ferr);
520 else
521 msg = i5100_err_msg(nerr);
522
523 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
524 }
525
526 if (i5100_validlog_nrecmemvalid(dw)) {
527 const char *msg;
528
529 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
530 merr = i5100_nrecmema_merr(dw2);
531 bank = i5100_nrecmema_bank(dw2);
532 rank = i5100_nrecmema_rank(dw2);
533
534 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
535 cas = i5100_nrecmemb_cas(dw2);
536 ras = i5100_nrecmemb_ras(dw2);
537
538 /* FIXME: not really sure if this is what merr is...
539 */
540 if (!merr)
541 msg = i5100_err_msg(ferr);
542 else
543 msg = i5100_err_msg(nerr);
544
545 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
546 }
547
548 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
549 }
550
551 static void i5100_check_error(struct mem_ctl_info *mci)
552 {
553 struct i5100_priv *priv = mci->pvt_info;
554 u32 dw, dw2;
555
556 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
557 if (i5100_ferr_nf_mem_any(dw)) {
558
559 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
560
561 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
562 i5100_ferr_nf_mem_any(dw),
563 i5100_nerr_nf_mem_any(dw2));
564
565 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
566 }
567 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
568 }
569
570 /* The i5100 chipset will scrub the entire memory once, then
571 * set a done bit. Continuous scrubbing is achieved by enqueing
572 * delayed work to a workqueue, checking every few minutes if
573 * the scrubbing has completed and if so reinitiating it.
574 */
575
576 static void i5100_refresh_scrubbing(struct work_struct *work)
577 {
578 struct delayed_work *i5100_scrubbing = container_of(work,
579 struct delayed_work,
580 work);
581 struct i5100_priv *priv = container_of(i5100_scrubbing,
582 struct i5100_priv,
583 i5100_scrubbing);
584 u32 dw;
585
586 pci_read_config_dword(priv->mc, I5100_MC, &dw);
587
588 if (priv->scrub_enable) {
589
590 pci_read_config_dword(priv->mc, I5100_MC, &dw);
591
592 if (i5100_mc_scrbdone(dw)) {
593 dw |= I5100_MC_SCRBEN_MASK;
594 pci_write_config_dword(priv->mc, I5100_MC, dw);
595 pci_read_config_dword(priv->mc, I5100_MC, &dw);
596 }
597
598 schedule_delayed_work(&(priv->i5100_scrubbing),
599 I5100_SCRUB_REFRESH_RATE);
600 }
601 }
602 /*
603 * The bandwidth is based on experimentation, feel free to refine it.
604 */
605 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
606 {
607 struct i5100_priv *priv = mci->pvt_info;
608 u32 dw;
609
610 pci_read_config_dword(priv->mc, I5100_MC, &dw);
611 if (bandwidth) {
612 priv->scrub_enable = 1;
613 dw |= I5100_MC_SCRBEN_MASK;
614 schedule_delayed_work(&(priv->i5100_scrubbing),
615 I5100_SCRUB_REFRESH_RATE);
616 } else {
617 priv->scrub_enable = 0;
618 dw &= ~I5100_MC_SCRBEN_MASK;
619 cancel_delayed_work(&(priv->i5100_scrubbing));
620 }
621 pci_write_config_dword(priv->mc, I5100_MC, dw);
622
623 pci_read_config_dword(priv->mc, I5100_MC, &dw);
624
625 bandwidth = 5900000 * i5100_mc_scrben(dw);
626
627 return bandwidth;
628 }
629
630 static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
631 {
632 struct i5100_priv *priv = mci->pvt_info;
633 u32 dw;
634
635 pci_read_config_dword(priv->mc, I5100_MC, &dw);
636
637 return 5900000 * i5100_mc_scrben(dw);
638 }
639
640 static struct pci_dev *pci_get_device_func(unsigned vendor,
641 unsigned device,
642 unsigned func)
643 {
644 struct pci_dev *ret = NULL;
645
646 while (1) {
647 ret = pci_get_device(vendor, device, ret);
648
649 if (!ret)
650 break;
651
652 if (PCI_FUNC(ret->devfn) == func)
653 break;
654 }
655
656 return ret;
657 }
658
659 static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
660 {
661 struct i5100_priv *priv = mci->pvt_info;
662 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
663 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
664 unsigned addr_lines;
665
666 /* dimm present? */
667 if (!priv->mtr[chan][chan_rank].present)
668 return 0ULL;
669
670 addr_lines =
671 I5100_DIMM_ADDR_LINES +
672 priv->mtr[chan][chan_rank].numcol +
673 priv->mtr[chan][chan_rank].numrow +
674 priv->mtr[chan][chan_rank].numbank;
675
676 return (unsigned long)
677 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
678 }
679
680 static void i5100_init_mtr(struct mem_ctl_info *mci)
681 {
682 struct i5100_priv *priv = mci->pvt_info;
683 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
684 int i;
685
686 for (i = 0; i < I5100_CHANNELS; i++) {
687 int j;
688 struct pci_dev *pdev = mms[i];
689
690 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
691 const unsigned addr =
692 (j < 4) ? I5100_MTR_0 + j * 2 :
693 I5100_MTR_4 + (j - 4) * 2;
694 u16 w;
695
696 pci_read_config_word(pdev, addr, &w);
697
698 priv->mtr[i][j].present = i5100_mtr_present(w);
699 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
700 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
701 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
702 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
703 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
704 }
705 }
706 }
707
708 /*
709 * FIXME: make this into a real i2c adapter (so that dimm-decode
710 * will work)?
711 */
712 static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
713 u8 ch, u8 slot, u8 addr, u8 *byte)
714 {
715 struct i5100_priv *priv = mci->pvt_info;
716 u16 w;
717 unsigned long et;
718
719 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
720 if (i5100_spddata_busy(w))
721 return -1;
722
723 pci_write_config_dword(priv->mc, I5100_SPDCMD,
724 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
725 0, 0));
726
727 /* wait up to 100ms */
728 et = jiffies + HZ / 10;
729 udelay(100);
730 while (1) {
731 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
732 if (!i5100_spddata_busy(w))
733 break;
734 udelay(100);
735 }
736
737 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
738 return -1;
739
740 *byte = i5100_spddata_data(w);
741
742 return 0;
743 }
744
745 /*
746 * fill dimm chip select map
747 *
748 * FIXME:
749 * o not the only way to may chip selects to dimm slots
750 * o investigate if there is some way to obtain this map from the bios
751 */
752 static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
753 {
754 struct i5100_priv *priv = mci->pvt_info;
755 int i;
756
757 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
758 int j;
759
760 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
761 priv->dimm_csmap[i][j] = -1; /* default NC */
762 }
763
764 /* only 2 chip selects per slot... */
765 if (priv->ranksperchan == 4) {
766 priv->dimm_csmap[0][0] = 0;
767 priv->dimm_csmap[0][1] = 3;
768 priv->dimm_csmap[1][0] = 1;
769 priv->dimm_csmap[1][1] = 2;
770 priv->dimm_csmap[2][0] = 2;
771 priv->dimm_csmap[3][0] = 3;
772 } else {
773 priv->dimm_csmap[0][0] = 0;
774 priv->dimm_csmap[0][1] = 1;
775 priv->dimm_csmap[1][0] = 2;
776 priv->dimm_csmap[1][1] = 3;
777 priv->dimm_csmap[2][0] = 4;
778 priv->dimm_csmap[2][1] = 5;
779 }
780 }
781
782 static void i5100_init_dimm_layout(struct pci_dev *pdev,
783 struct mem_ctl_info *mci)
784 {
785 struct i5100_priv *priv = mci->pvt_info;
786 int i;
787
788 for (i = 0; i < I5100_CHANNELS; i++) {
789 int j;
790
791 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
792 u8 rank;
793
794 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
795 priv->dimm_numrank[i][j] = 0;
796 else
797 priv->dimm_numrank[i][j] = (rank & 3) + 1;
798 }
799 }
800
801 i5100_init_dimm_csmap(mci);
802 }
803
804 static void i5100_init_interleaving(struct pci_dev *pdev,
805 struct mem_ctl_info *mci)
806 {
807 u16 w;
808 u32 dw;
809 struct i5100_priv *priv = mci->pvt_info;
810 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
811 int i;
812
813 pci_read_config_word(pdev, I5100_TOLM, &w);
814 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
815
816 pci_read_config_word(pdev, I5100_MIR0, &w);
817 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
818 priv->mir[0].way[1] = i5100_mir_way1(w);
819 priv->mir[0].way[0] = i5100_mir_way0(w);
820
821 pci_read_config_word(pdev, I5100_MIR1, &w);
822 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
823 priv->mir[1].way[1] = i5100_mir_way1(w);
824 priv->mir[1].way[0] = i5100_mir_way0(w);
825
826 pci_read_config_word(pdev, I5100_AMIR_0, &w);
827 priv->amir[0] = w;
828 pci_read_config_word(pdev, I5100_AMIR_1, &w);
829 priv->amir[1] = w;
830
831 for (i = 0; i < I5100_CHANNELS; i++) {
832 int j;
833
834 for (j = 0; j < 5; j++) {
835 int k;
836
837 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
838
839 priv->dmir[i][j].limit =
840 (u64) i5100_dmir_limit(dw) << 28;
841 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
842 priv->dmir[i][j].rank[k] =
843 i5100_dmir_rank(dw, k);
844 }
845 }
846
847 i5100_init_mtr(mci);
848 }
849
850 static void i5100_init_csrows(struct mem_ctl_info *mci)
851 {
852 int i;
853 struct i5100_priv *priv = mci->pvt_info;
854
855 for (i = 0; i < mci->tot_dimms; i++) {
856 struct dimm_info *dimm;
857 const unsigned long npages = i5100_npages(mci, i);
858 const unsigned chan = i5100_csrow_to_chan(mci, i);
859 const unsigned rank = i5100_csrow_to_rank(mci, i);
860
861 if (!npages)
862 continue;
863
864 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
865 chan, rank, 0);
866
867 dimm->nr_pages = npages;
868 dimm->grain = 32;
869 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
870 DEV_X4 : DEV_X8;
871 dimm->mtype = MEM_RDDR2;
872 dimm->edac_mode = EDAC_SECDED;
873 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",
874 i5100_rank_to_slot(mci, chan, rank));
875
876 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
877 chan, rank, (long)PAGES_TO_MiB(npages));
878 }
879 }
880
881 /****************************************************************************
882 * Error injection routines
883 ****************************************************************************/
884
885 static void i5100_do_inject(struct mem_ctl_info *mci)
886 {
887 struct i5100_priv *priv = mci->pvt_info;
888 u32 mask0;
889 u16 mask1;
890
891 /* MEM[1:0]EINJMSK0
892 * 31 - ADDRMATCHEN
893 * 29:28 - HLINESEL
894 * 00 Reserved
895 * 01 Lower half of cache line
896 * 10 Upper half of cache line
897 * 11 Both upper and lower parts of cache line
898 * 27 - EINJEN
899 * 25:19 - XORMASK1 for deviceptr1
900 * 9:5 - SEC2RAM for deviceptr2
901 * 4:0 - FIR2RAM for deviceptr1
902 */
903 mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
904 I5100_MEMXEINJMSK0_EINJEN |
905 ((priv->inject_eccmask1 & 0xffff) << 10) |
906 ((priv->inject_deviceptr2 & 0x1f) << 5) |
907 (priv->inject_deviceptr1 & 0x1f);
908
909 /* MEM[1:0]EINJMSK1
910 * 15:0 - XORMASK2 for deviceptr2
911 */
912 mask1 = priv->inject_eccmask2;
913
914 if (priv->inject_channel == 0) {
915 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
916 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
917 } else {
918 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
919 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
920 }
921
922 /* Error Injection Response Function
923 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet
924 * hints about this register but carry no data about them. All
925 * data regarding device 19 is based on experimentation and the
926 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet
927 * which appears to be accurate for the i5100 in this area.
928 *
929 * The injection code don't work without setting this register.
930 * The register needs to be flipped off then on else the hardware
931 * will only preform the first injection.
932 *
933 * Stop condition bits 7:4
934 * 1010 - Stop after one injection
935 * 1011 - Never stop injecting faults
936 *
937 * Start condition bits 3:0
938 * 1010 - Never start
939 * 1011 - Start immediately
940 */
941 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
942 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
943 }
944
945 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
946 static ssize_t inject_enable_write(struct file *file, const char __user *data,
947 size_t count, loff_t *ppos)
948 {
949 struct device *dev = file->private_data;
950 struct mem_ctl_info *mci = to_mci(dev);
951
952 i5100_do_inject(mci);
953
954 return count;
955 }
956
957 static const struct file_operations i5100_inject_enable_fops = {
958 .open = simple_open,
959 .write = inject_enable_write,
960 .llseek = generic_file_llseek,
961 };
962
963 static int i5100_setup_debugfs(struct mem_ctl_info *mci)
964 {
965 struct i5100_priv *priv = mci->pvt_info;
966
967 if (!i5100_debugfs)
968 return -ENODEV;
969
970 priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs);
971
972 if (!priv->debugfs)
973 return -ENOMEM;
974
975 edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
976 &priv->inject_channel);
977 edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
978 &priv->inject_hlinesel);
979 edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
980 &priv->inject_deviceptr1);
981 edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
982 &priv->inject_deviceptr2);
983 edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
984 &priv->inject_eccmask1);
985 edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
986 &priv->inject_eccmask2);
987 edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
988 &mci->dev, &i5100_inject_enable_fops);
989
990 return 0;
991
992 }
993
994 static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
995 {
996 int rc;
997 struct mem_ctl_info *mci;
998 struct edac_mc_layer layers[2];
999 struct i5100_priv *priv;
1000 struct pci_dev *ch0mm, *ch1mm, *einj;
1001 int ret = 0;
1002 u32 dw;
1003 int ranksperch;
1004
1005 if (PCI_FUNC(pdev->devfn) != 1)
1006 return -ENODEV;
1007
1008 rc = pci_enable_device(pdev);
1009 if (rc < 0) {
1010 ret = rc;
1011 goto bail;
1012 }
1013
1014 /* ECC enabled? */
1015 pci_read_config_dword(pdev, I5100_MC, &dw);
1016 if (!i5100_mc_errdeten(dw)) {
1017 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
1018 ret = -ENODEV;
1019 goto bail_pdev;
1020 }
1021
1022 /* figure out how many ranks, from strapped state of 48GB_Mode input */
1023 pci_read_config_dword(pdev, I5100_MS, &dw);
1024 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
1025
1026 /* enable error reporting... */
1027 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
1028 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
1029 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
1030
1031 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
1032 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1033 PCI_DEVICE_ID_INTEL_5100_21, 0);
1034 if (!ch0mm) {
1035 ret = -ENODEV;
1036 goto bail_pdev;
1037 }
1038
1039 rc = pci_enable_device(ch0mm);
1040 if (rc < 0) {
1041 ret = rc;
1042 goto bail_ch0;
1043 }
1044
1045 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
1046 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1047 PCI_DEVICE_ID_INTEL_5100_22, 0);
1048 if (!ch1mm) {
1049 ret = -ENODEV;
1050 goto bail_disable_ch0;
1051 }
1052
1053 rc = pci_enable_device(ch1mm);
1054 if (rc < 0) {
1055 ret = rc;
1056 goto bail_ch1;
1057 }
1058
1059 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1060 layers[0].size = 2;
1061 layers[0].is_virt_csrow = false;
1062 layers[1].type = EDAC_MC_LAYER_SLOT;
1063 layers[1].size = ranksperch;
1064 layers[1].is_virt_csrow = true;
1065 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1066 sizeof(*priv));
1067 if (!mci) {
1068 ret = -ENOMEM;
1069 goto bail_disable_ch1;
1070 }
1071
1072
1073 /* device 19, func 0, Error injection */
1074 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1075 PCI_DEVICE_ID_INTEL_5100_19, 0);
1076 if (!einj) {
1077 ret = -ENODEV;
1078 goto bail_einj;
1079 }
1080
1081 rc = pci_enable_device(einj);
1082 if (rc < 0) {
1083 ret = rc;
1084 goto bail_disable_einj;
1085 }
1086
1087
1088 mci->pdev = &pdev->dev;
1089
1090 priv = mci->pvt_info;
1091 priv->ranksperchan = ranksperch;
1092 priv->mc = pdev;
1093 priv->ch0mm = ch0mm;
1094 priv->ch1mm = ch1mm;
1095 priv->einj = einj;
1096
1097 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
1098
1099 /* If scrubbing was already enabled by the bios, start maintaining it */
1100 pci_read_config_dword(pdev, I5100_MC, &dw);
1101 if (i5100_mc_scrben(dw)) {
1102 priv->scrub_enable = 1;
1103 schedule_delayed_work(&(priv->i5100_scrubbing),
1104 I5100_SCRUB_REFRESH_RATE);
1105 }
1106
1107 i5100_init_dimm_layout(pdev, mci);
1108 i5100_init_interleaving(pdev, mci);
1109
1110 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1111 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1112 mci->edac_cap = EDAC_FLAG_SECDED;
1113 mci->mod_name = "i5100_edac.c";
1114 mci->mod_ver = "not versioned";
1115 mci->ctl_name = "i5100";
1116 mci->dev_name = pci_name(pdev);
1117 mci->ctl_page_to_phys = NULL;
1118
1119 mci->edac_check = i5100_check_error;
1120 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
1121 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
1122
1123 priv->inject_channel = 0;
1124 priv->inject_hlinesel = 0;
1125 priv->inject_deviceptr1 = 0;
1126 priv->inject_deviceptr2 = 0;
1127 priv->inject_eccmask1 = 0;
1128 priv->inject_eccmask2 = 0;
1129
1130 i5100_init_csrows(mci);
1131
1132 /* this strange construction seems to be in every driver, dunno why */
1133 switch (edac_op_state) {
1134 case EDAC_OPSTATE_POLL:
1135 case EDAC_OPSTATE_NMI:
1136 break;
1137 default:
1138 edac_op_state = EDAC_OPSTATE_POLL;
1139 break;
1140 }
1141
1142 if (edac_mc_add_mc(mci)) {
1143 ret = -ENODEV;
1144 goto bail_scrub;
1145 }
1146
1147 i5100_setup_debugfs(mci);
1148
1149 return ret;
1150
1151 bail_scrub:
1152 priv->scrub_enable = 0;
1153 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1154 edac_mc_free(mci);
1155
1156 bail_disable_einj:
1157 pci_disable_device(einj);
1158
1159 bail_einj:
1160 pci_dev_put(einj);
1161
1162 bail_disable_ch1:
1163 pci_disable_device(ch1mm);
1164
1165 bail_ch1:
1166 pci_dev_put(ch1mm);
1167
1168 bail_disable_ch0:
1169 pci_disable_device(ch0mm);
1170
1171 bail_ch0:
1172 pci_dev_put(ch0mm);
1173
1174 bail_pdev:
1175 pci_disable_device(pdev);
1176
1177 bail:
1178 return ret;
1179 }
1180
1181 static void i5100_remove_one(struct pci_dev *pdev)
1182 {
1183 struct mem_ctl_info *mci;
1184 struct i5100_priv *priv;
1185
1186 mci = edac_mc_del_mc(&pdev->dev);
1187
1188 if (!mci)
1189 return;
1190
1191 priv = mci->pvt_info;
1192
1193 edac_debugfs_remove_recursive(priv->debugfs);
1194
1195 priv->scrub_enable = 0;
1196 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1197
1198 pci_disable_device(pdev);
1199 pci_disable_device(priv->ch0mm);
1200 pci_disable_device(priv->ch1mm);
1201 pci_disable_device(priv->einj);
1202 pci_dev_put(priv->ch0mm);
1203 pci_dev_put(priv->ch1mm);
1204 pci_dev_put(priv->einj);
1205
1206 edac_mc_free(mci);
1207 }
1208
1209 static const struct pci_device_id i5100_pci_tbl[] = {
1210 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1211 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1212 { 0, }
1213 };
1214 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1215
1216 static struct pci_driver i5100_driver = {
1217 .name = KBUILD_BASENAME,
1218 .probe = i5100_init_one,
1219 .remove = i5100_remove_one,
1220 .id_table = i5100_pci_tbl,
1221 };
1222
1223 static int __init i5100_init(void)
1224 {
1225 int pci_rc;
1226
1227 i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL);
1228
1229 pci_rc = pci_register_driver(&i5100_driver);
1230 return (pci_rc < 0) ? pci_rc : 0;
1231 }
1232
1233 static void __exit i5100_exit(void)
1234 {
1235 edac_debugfs_remove(i5100_debugfs);
1236
1237 pci_unregister_driver(&i5100_driver);
1238 }
1239
1240 module_init(i5100_init);
1241 module_exit(i5100_exit);
1242
1243 MODULE_LICENSE("GPL");
1244 MODULE_AUTHOR
1245 ("Arthur Jones <ajones@riverbed.com>");
1246 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
Linux with added FPC-III support