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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / gpio / gpio-mvebu.c
blobd428b97876c52e933ee37b42540313b777c39c73
1 /*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36 #include <linux/err.h>
37 #include <linux/module.h>
38 #include <linux/gpio.h>
39 #include <linux/irq.h>
40 #include <linux/slab.h>
41 #include <linux/irqdomain.h>
42 #include <linux/io.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_device.h>
45 #include <linux/clk.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/irqchip/chained_irq.h>
48
49 /*
50 * GPIO unit register offsets.
51 */
52 #define GPIO_OUT_OFF 0x0000
53 #define GPIO_IO_CONF_OFF 0x0004
54 #define GPIO_BLINK_EN_OFF 0x0008
55 #define GPIO_IN_POL_OFF 0x000c
56 #define GPIO_DATA_IN_OFF 0x0010
57 #define GPIO_EDGE_CAUSE_OFF 0x0014
58 #define GPIO_EDGE_MASK_OFF 0x0018
59 #define GPIO_LEVEL_MASK_OFF 0x001c
60
61 /* The MV78200 has per-CPU registers for edge mask and level mask */
62 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
63 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
64
65 /* The Armada XP has per-CPU registers for interrupt cause, interrupt
66 * mask and interrupt level mask. Those are relative to the
67 * percpu_membase. */
68 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
69 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
70 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
71
72 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
73 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
74 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
75
76 #define MVEBU_MAX_GPIO_PER_BANK 32
77
78 struct mvebu_gpio_chip {
79 struct gpio_chip chip;
80 spinlock_t lock;
81 void __iomem *membase;
82 void __iomem *percpu_membase;
83 int irqbase;
84 struct irq_domain *domain;
85 int soc_variant;
86
87 /* Used to preserve GPIO registers across suspend/resume */
88 u32 out_reg;
89 u32 io_conf_reg;
90 u32 blink_en_reg;
91 u32 in_pol_reg;
92 u32 edge_mask_regs[4];
93 u32 level_mask_regs[4];
94 };
95
96 /*
97 * Functions returning addresses of individual registers for a given
98 * GPIO controller.
99 */
100 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
101 {
102 return mvchip->membase + GPIO_OUT_OFF;
103 }
104
105 static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
106 {
107 return mvchip->membase + GPIO_BLINK_EN_OFF;
108 }
109
110 static inline void __iomem *
111 mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
112 {
113 return mvchip->membase + GPIO_IO_CONF_OFF;
114 }
115
116 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
117 {
118 return mvchip->membase + GPIO_IN_POL_OFF;
119 }
120
121 static inline void __iomem *
122 mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
123 {
124 return mvchip->membase + GPIO_DATA_IN_OFF;
125 }
126
127 static inline void __iomem *
128 mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
129 {
130 int cpu;
131
132 switch (mvchip->soc_variant) {
133 case MVEBU_GPIO_SOC_VARIANT_ORION:
134 case MVEBU_GPIO_SOC_VARIANT_MV78200:
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
137 cpu = smp_processor_id();
138 return mvchip->percpu_membase +
139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
140 default:
141 BUG();
142 }
143 }
144
145 static inline void __iomem *
146 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
147 {
148 int cpu;
149
150 switch (mvchip->soc_variant) {
151 case MVEBU_GPIO_SOC_VARIANT_ORION:
152 return mvchip->membase + GPIO_EDGE_MASK_OFF;
153 case MVEBU_GPIO_SOC_VARIANT_MV78200:
154 cpu = smp_processor_id();
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
157 cpu = smp_processor_id();
158 return mvchip->percpu_membase +
159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
160 default:
161 BUG();
162 }
163 }
164
165 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
166 {
167 int cpu;
168
169 switch (mvchip->soc_variant) {
170 case MVEBU_GPIO_SOC_VARIANT_ORION:
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
173 cpu = smp_processor_id();
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
176 cpu = smp_processor_id();
177 return mvchip->percpu_membase +
178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
179 default:
180 BUG();
181 }
182 }
183
184 /*
185 * Functions implementing the gpio_chip methods
186 */
187
188 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
189 {
190 struct mvebu_gpio_chip *mvchip =
191 container_of(chip, struct mvebu_gpio_chip, chip);
192 unsigned long flags;
193 u32 u;
194
195 spin_lock_irqsave(&mvchip->lock, flags);
196 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
197 if (value)
198 u |= 1 << pin;
199 else
200 u &= ~(1 << pin);
201 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
202 spin_unlock_irqrestore(&mvchip->lock, flags);
203 }
204
205 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
206 {
207 struct mvebu_gpio_chip *mvchip =
208 container_of(chip, struct mvebu_gpio_chip, chip);
209 u32 u;
210
211 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
212 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
213 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
214 } else {
215 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
216 }
217
218 return (u >> pin) & 1;
219 }
220
221 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
222 {
223 struct mvebu_gpio_chip *mvchip =
224 container_of(chip, struct mvebu_gpio_chip, chip);
225 unsigned long flags;
226 u32 u;
227
228 spin_lock_irqsave(&mvchip->lock, flags);
229 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
230 if (value)
231 u |= 1 << pin;
232 else
233 u &= ~(1 << pin);
234 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
235 spin_unlock_irqrestore(&mvchip->lock, flags);
236 }
237
238 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
239 {
240 struct mvebu_gpio_chip *mvchip =
241 container_of(chip, struct mvebu_gpio_chip, chip);
242 unsigned long flags;
243 int ret;
244 u32 u;
245
246 /* Check with the pinctrl driver whether this pin is usable as
247 * an input GPIO */
248 ret = pinctrl_gpio_direction_input(chip->base + pin);
249 if (ret)
250 return ret;
251
252 spin_lock_irqsave(&mvchip->lock, flags);
253 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
254 u |= 1 << pin;
255 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
256 spin_unlock_irqrestore(&mvchip->lock, flags);
257
258 return 0;
259 }
260
261 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
262 int value)
263 {
264 struct mvebu_gpio_chip *mvchip =
265 container_of(chip, struct mvebu_gpio_chip, chip);
266 unsigned long flags;
267 int ret;
268 u32 u;
269
270 /* Check with the pinctrl driver whether this pin is usable as
271 * an output GPIO */
272 ret = pinctrl_gpio_direction_output(chip->base + pin);
273 if (ret)
274 return ret;
275
276 mvebu_gpio_blink(chip, pin, 0);
277 mvebu_gpio_set(chip, pin, value);
278
279 spin_lock_irqsave(&mvchip->lock, flags);
280 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
281 u &= ~(1 << pin);
282 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
283 spin_unlock_irqrestore(&mvchip->lock, flags);
284
285 return 0;
286 }
287
288 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
289 {
290 struct mvebu_gpio_chip *mvchip =
291 container_of(chip, struct mvebu_gpio_chip, chip);
292 return irq_create_mapping(mvchip->domain, pin);
293 }
294
295 /*
296 * Functions implementing the irq_chip methods
297 */
298 static void mvebu_gpio_irq_ack(struct irq_data *d)
299 {
300 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
301 struct mvebu_gpio_chip *mvchip = gc->private;
302 u32 mask = ~(1 << (d->irq - gc->irq_base));
303
304 irq_gc_lock(gc);
305 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
306 irq_gc_unlock(gc);
307 }
308
309 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
310 {
311 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312 struct mvebu_gpio_chip *mvchip = gc->private;
313 struct irq_chip_type *ct = irq_data_get_chip_type(d);
314 u32 mask = 1 << (d->irq - gc->irq_base);
315
316 irq_gc_lock(gc);
317 ct->mask_cache_priv &= ~mask;
318
319 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
320 irq_gc_unlock(gc);
321 }
322
323 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
324 {
325 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
326 struct mvebu_gpio_chip *mvchip = gc->private;
327 struct irq_chip_type *ct = irq_data_get_chip_type(d);
328
329 u32 mask = 1 << (d->irq - gc->irq_base);
330
331 irq_gc_lock(gc);
332 ct->mask_cache_priv |= mask;
333 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
334 irq_gc_unlock(gc);
335 }
336
337 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
338 {
339 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
340 struct mvebu_gpio_chip *mvchip = gc->private;
341 struct irq_chip_type *ct = irq_data_get_chip_type(d);
342
343 u32 mask = 1 << (d->irq - gc->irq_base);
344
345 irq_gc_lock(gc);
346 ct->mask_cache_priv &= ~mask;
347 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
348 irq_gc_unlock(gc);
349 }
350
351 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
352 {
353 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
354 struct mvebu_gpio_chip *mvchip = gc->private;
355 struct irq_chip_type *ct = irq_data_get_chip_type(d);
356
357 u32 mask = 1 << (d->irq - gc->irq_base);
358
359 irq_gc_lock(gc);
360 ct->mask_cache_priv |= mask;
361 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
362 irq_gc_unlock(gc);
363 }
364
365 /*****************************************************************************
366 * MVEBU GPIO IRQ
367 *
368 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
369 * value of the line or the opposite value.
370 *
371 * Level IRQ handlers: DATA_IN is used directly as cause register.
372 * Interrupt are masked by LEVEL_MASK registers.
373 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
374 * Interrupt are masked by EDGE_MASK registers.
375 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
376 * the polarity to catch the next line transaction.
377 * This is a race condition that might not perfectly
378 * work on some use cases.
379 *
380 * Every eight GPIO lines are grouped (OR'ed) before going up to main
381 * cause register.
382 *
383 * EDGE cause mask
384 * data-in /--------| |-----| |----\
385 * -----| |----- ---- to main cause reg
386 * X \----------------| |----/
387 * polarity LEVEL mask
388 *
389 ****************************************************************************/
390
391 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
392 {
393 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
394 struct irq_chip_type *ct = irq_data_get_chip_type(d);
395 struct mvebu_gpio_chip *mvchip = gc->private;
396 int pin;
397 u32 u;
398
399 pin = d->hwirq;
400
401 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
402 if (!u)
403 return -EINVAL;
404
405 type &= IRQ_TYPE_SENSE_MASK;
406 if (type == IRQ_TYPE_NONE)
407 return -EINVAL;
408
409 /* Check if we need to change chip and handler */
410 if (!(ct->type & type))
411 if (irq_setup_alt_chip(d, type))
412 return -EINVAL;
413
414 /*
415 * Configure interrupt polarity.
416 */
417 switch (type) {
418 case IRQ_TYPE_EDGE_RISING:
419 case IRQ_TYPE_LEVEL_HIGH:
420 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
421 u &= ~(1 << pin);
422 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
423 break;
424 case IRQ_TYPE_EDGE_FALLING:
425 case IRQ_TYPE_LEVEL_LOW:
426 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
427 u |= 1 << pin;
428 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
429 break;
430 case IRQ_TYPE_EDGE_BOTH: {
431 u32 v;
432
433 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
434 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
435
436 /*
437 * set initial polarity based on current input level
438 */
439 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
440 if (v & (1 << pin))
441 u |= 1 << pin; /* falling */
442 else
443 u &= ~(1 << pin); /* rising */
444 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
445 break;
446 }
447 }
448 return 0;
449 }
450
451 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
452 {
453 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
454 struct irq_chip *chip = irq_desc_get_chip(desc);
455 u32 cause, type;
456 int i;
457
458 if (mvchip == NULL)
459 return;
460
461 chained_irq_enter(chip, desc);
462
463 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
464 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
465 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
466 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
467
468 for (i = 0; i < mvchip->chip.ngpio; i++) {
469 int irq;
470
471 irq = mvchip->irqbase + i;
472
473 if (!(cause & (1 << i)))
474 continue;
475
476 type = irq_get_trigger_type(irq);
477 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
478 /* Swap polarity (race with GPIO line) */
479 u32 polarity;
480
481 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
482 polarity ^= 1 << i;
483 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
484 }
485
486 generic_handle_irq(irq);
487 }
488
489 chained_irq_exit(chip, desc);
490 }
491
492 #ifdef CONFIG_DEBUG_FS
493 #include <linux/seq_file.h>
494
495 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
496 {
497 struct mvebu_gpio_chip *mvchip =
498 container_of(chip, struct mvebu_gpio_chip, chip);
499 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
500 int i;
501
502 out = readl_relaxed(mvebu_gpioreg_out(mvchip));
503 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
504 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
505 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
506 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
507 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
508 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
509 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
510
511 for (i = 0; i < chip->ngpio; i++) {
512 const char *label;
513 u32 msk;
514 bool is_out;
515
516 label = gpiochip_is_requested(chip, i);
517 if (!label)
518 continue;
519
520 msk = 1 << i;
521 is_out = !(io_conf & msk);
522
523 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
524
525 if (is_out) {
526 seq_printf(s, " out %s %s\n",
527 out & msk ? "hi" : "lo",
528 blink & msk ? "(blink )" : "");
529 continue;
530 }
531
532 seq_printf(s, " in %s (act %s) - IRQ",
533 (data_in ^ in_pol) & msk ? "hi" : "lo",
534 in_pol & msk ? "lo" : "hi");
535 if (!((edg_msk | lvl_msk) & msk)) {
536 seq_puts(s, " disabled\n");
537 continue;
538 }
539 if (edg_msk & msk)
540 seq_puts(s, " edge ");
541 if (lvl_msk & msk)
542 seq_puts(s, " level");
543 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
544 }
545 }
546 #else
547 #define mvebu_gpio_dbg_show NULL
548 #endif
549
550 static const struct of_device_id mvebu_gpio_of_match[] = {
551 {
552 .compatible = "marvell,orion-gpio",
553 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
554 },
555 {
556 .compatible = "marvell,mv78200-gpio",
557 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
558 },
559 {
560 .compatible = "marvell,armadaxp-gpio",
561 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
562 },
563 {
564 /* sentinel */
565 },
566 };
567 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
568
569 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
570 {
571 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
572 int i;
573
574 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
575 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
576 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
577 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
578
579 switch (mvchip->soc_variant) {
580 case MVEBU_GPIO_SOC_VARIANT_ORION:
581 mvchip->edge_mask_regs[0] =
582 readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
583 mvchip->level_mask_regs[0] =
584 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
585 break;
586 case MVEBU_GPIO_SOC_VARIANT_MV78200:
587 for (i = 0; i < 2; i++) {
588 mvchip->edge_mask_regs[i] =
589 readl(mvchip->membase +
590 GPIO_EDGE_MASK_MV78200_OFF(i));
591 mvchip->level_mask_regs[i] =
592 readl(mvchip->membase +
593 GPIO_LEVEL_MASK_MV78200_OFF(i));
594 }
595 break;
596 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
597 for (i = 0; i < 4; i++) {
598 mvchip->edge_mask_regs[i] =
599 readl(mvchip->membase +
600 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
601 mvchip->level_mask_regs[i] =
602 readl(mvchip->membase +
603 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
604 }
605 break;
606 default:
607 BUG();
608 }
609
610 return 0;
611 }
612
613 static int mvebu_gpio_resume(struct platform_device *pdev)
614 {
615 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
616 int i;
617
618 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
619 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
620 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
621 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
622
623 switch (mvchip->soc_variant) {
624 case MVEBU_GPIO_SOC_VARIANT_ORION:
625 writel(mvchip->edge_mask_regs[0],
626 mvchip->membase + GPIO_EDGE_MASK_OFF);
627 writel(mvchip->level_mask_regs[0],
628 mvchip->membase + GPIO_LEVEL_MASK_OFF);
629 break;
630 case MVEBU_GPIO_SOC_VARIANT_MV78200:
631 for (i = 0; i < 2; i++) {
632 writel(mvchip->edge_mask_regs[i],
633 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
634 writel(mvchip->level_mask_regs[i],
635 mvchip->membase +
636 GPIO_LEVEL_MASK_MV78200_OFF(i));
637 }
638 break;
639 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
640 for (i = 0; i < 4; i++) {
641 writel(mvchip->edge_mask_regs[i],
642 mvchip->membase +
643 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
644 writel(mvchip->level_mask_regs[i],
645 mvchip->membase +
646 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
647 }
648 break;
649 default:
650 BUG();
651 }
652
653 return 0;
654 }
655
656 static int mvebu_gpio_probe(struct platform_device *pdev)
657 {
658 struct mvebu_gpio_chip *mvchip;
659 const struct of_device_id *match;
660 struct device_node *np = pdev->dev.of_node;
661 struct resource *res;
662 struct irq_chip_generic *gc;
663 struct irq_chip_type *ct;
664 struct clk *clk;
665 unsigned int ngpios;
666 int soc_variant;
667 int i, cpu, id;
668 int err;
669
670 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
671 if (match)
672 soc_variant = (int) match->data;
673 else
674 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
675
676 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
677 GFP_KERNEL);
678 if (!mvchip)
679 return -ENOMEM;
680
681 platform_set_drvdata(pdev, mvchip);
682
683 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
684 dev_err(&pdev->dev, "Missing ngpios OF property\n");
685 return -ENODEV;
686 }
687
688 id = of_alias_get_id(pdev->dev.of_node, "gpio");
689 if (id < 0) {
690 dev_err(&pdev->dev, "Couldn't get OF id\n");
691 return id;
692 }
693
694 clk = devm_clk_get(&pdev->dev, NULL);
695 /* Not all SoCs require a clock.*/
696 if (!IS_ERR(clk))
697 clk_prepare_enable(clk);
698
699 mvchip->soc_variant = soc_variant;
700 mvchip->chip.label = dev_name(&pdev->dev);
701 mvchip->chip.dev = &pdev->dev;
702 mvchip->chip.request = gpiochip_generic_request;
703 mvchip->chip.free = gpiochip_generic_free;
704 mvchip->chip.direction_input = mvebu_gpio_direction_input;
705 mvchip->chip.get = mvebu_gpio_get;
706 mvchip->chip.direction_output = mvebu_gpio_direction_output;
707 mvchip->chip.set = mvebu_gpio_set;
708 mvchip->chip.to_irq = mvebu_gpio_to_irq;
709 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
710 mvchip->chip.ngpio = ngpios;
711 mvchip->chip.can_sleep = false;
712 mvchip->chip.of_node = np;
713 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
714
715 spin_lock_init(&mvchip->lock);
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
718 if (IS_ERR(mvchip->membase))
719 return PTR_ERR(mvchip->membase);
720
721 /* The Armada XP has a second range of registers for the
722 * per-CPU registers */
723 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
724 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
725 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
726 res);
727 if (IS_ERR(mvchip->percpu_membase))
728 return PTR_ERR(mvchip->percpu_membase);
729 }
730
731 /*
732 * Mask and clear GPIO interrupts.
733 */
734 switch (soc_variant) {
735 case MVEBU_GPIO_SOC_VARIANT_ORION:
736 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
737 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
738 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
739 break;
740 case MVEBU_GPIO_SOC_VARIANT_MV78200:
741 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
742 for (cpu = 0; cpu < 2; cpu++) {
743 writel_relaxed(0, mvchip->membase +
744 GPIO_EDGE_MASK_MV78200_OFF(cpu));
745 writel_relaxed(0, mvchip->membase +
746 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
747 }
748 break;
749 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
750 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
751 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
752 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
753 for (cpu = 0; cpu < 4; cpu++) {
754 writel_relaxed(0, mvchip->percpu_membase +
755 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
756 writel_relaxed(0, mvchip->percpu_membase +
757 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
758 writel_relaxed(0, mvchip->percpu_membase +
759 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
760 }
761 break;
762 default:
763 BUG();
764 }
765
766 gpiochip_add(&mvchip->chip);
767
768 /* Some gpio controllers do not provide irq support */
769 if (!of_irq_count(np))
770 return 0;
771
772 /* Setup the interrupt handlers. Each chip can have up to 4
773 * interrupt handlers, with each handler dealing with 8 GPIO
774 * pins. */
775 for (i = 0; i < 4; i++) {
776 int irq = platform_get_irq(pdev, i);
777
778 if (irq < 0)
779 continue;
780 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
781 mvchip);
782 }
783
784 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
785 if (mvchip->irqbase < 0) {
786 dev_err(&pdev->dev, "no irqs\n");
787 err = mvchip->irqbase;
788 goto err_gpiochip_add;
789 }
790
791 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
792 mvchip->membase, handle_level_irq);
793 if (!gc) {
794 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
795 err = -ENOMEM;
796 goto err_gpiochip_add;
797 }
798
799 gc->private = mvchip;
800 ct = &gc->chip_types[0];
801 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
802 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
803 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
804 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
805 ct->chip.name = mvchip->chip.label;
806
807 ct = &gc->chip_types[1];
808 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
809 ct->chip.irq_ack = mvebu_gpio_irq_ack;
810 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
811 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
812 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
813 ct->handler = handle_edge_irq;
814 ct->chip.name = mvchip->chip.label;
815
816 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
817 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
818
819 /* Setup irq domain on top of the generic chip. */
820 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
821 mvchip->irqbase,
822 &irq_domain_simple_ops,
823 mvchip);
824 if (!mvchip->domain) {
825 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
826 mvchip->chip.label);
827 err = -ENODEV;
828 goto err_generic_chip;
829 }
830
831 return 0;
832
833 err_generic_chip:
834 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
835 IRQ_LEVEL | IRQ_NOPROBE);
836 kfree(gc);
837
838 err_gpiochip_add:
839 gpiochip_remove(&mvchip->chip);
840
841 return err;
842 }
843
844 static struct platform_driver mvebu_gpio_driver = {
845 .driver = {
846 .name = "mvebu-gpio",
847 .of_match_table = mvebu_gpio_of_match,
848 },
849 .probe = mvebu_gpio_probe,
850 .suspend = mvebu_gpio_suspend,
851 .resume = mvebu_gpio_resume,
852 };
853 module_platform_driver(mvebu_gpio_driver);
Linux with added FPC-III support