drivers/pci/host/pci-rcar-gen2.c

   1 /*
   2  *  pci-rcar-gen2: internal PCI bus support
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/of_pci.h>
  19 #include <linux/pci.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/sizes.h>
  23 #include <linux/slab.h>
  24
  25 /* AHB-PCI Bridge PCI communication registers */
  26 #define RCAR_AHBPCI_PCICOM_OFFSET       0x800
  27
  28 #define RCAR_PCIAHB_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  29 #define RCAR_PCIAHB_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  30 #define RCAR_PCIAHB_PREFETCH0           0x0
  31 #define RCAR_PCIAHB_PREFETCH4           0x1
  32 #define RCAR_PCIAHB_PREFETCH8           0x2
  33 #define RCAR_PCIAHB_PREFETCH16          0x3
  34
  35 #define RCAR_AHBPCI_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  36 #define RCAR_AHBPCI_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  37 #define RCAR_AHBPCI_WIN_CTR_MEM         (3 << 1)
  38 #define RCAR_AHBPCI_WIN_CTR_CFG         (5 << 1)
  39 #define RCAR_AHBPCI_WIN1_HOST           (1 << 30)
  40 #define RCAR_AHBPCI_WIN1_DEVICE         (1 << 31)
  41
  42 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  43 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  44 #define RCAR_PCI_INT_SIGTABORT          (1 << 0)
  45 #define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
  46 #define RCAR_PCI_INT_REMABORT           (1 << 2)
  47 #define RCAR_PCI_INT_PERR               (1 << 3)
  48 #define RCAR_PCI_INT_SIGSERR            (1 << 4)
  49 #define RCAR_PCI_INT_RESERR             (1 << 5)
  50 #define RCAR_PCI_INT_WIN1ERR            (1 << 12)
  51 #define RCAR_PCI_INT_WIN2ERR            (1 << 13)
  52 #define RCAR_PCI_INT_A                  (1 << 16)
  53 #define RCAR_PCI_INT_B                  (1 << 17)
  54 #define RCAR_PCI_INT_PME                (1 << 19)
  55 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
  56                                 RCAR_PCI_INT_SIGRETABORT        | \
  57                                 RCAR_PCI_INT_SIGRETABORT        | \
  58                                 RCAR_PCI_INT_REMABORT           | \
  59                                 RCAR_PCI_INT_PERR               | \
  60                                 RCAR_PCI_INT_SIGSERR            | \
  61                                 RCAR_PCI_INT_RESERR             | \
  62                                 RCAR_PCI_INT_WIN1ERR            | \
  63                                 RCAR_PCI_INT_WIN2ERR)
  64
  65 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  66 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
  67 #define RCAR_AHB_BUS_MMODE_BYTE_BURST   (1 << 1)
  68 #define RCAR_AHB_BUS_MMODE_WR_INCR      (1 << 2)
  69 #define RCAR_AHB_BUS_MMODE_HBUS_REQ     (1 << 7)
  70 #define RCAR_AHB_BUS_SMODE_READYCTR     (1 << 17)
  71 #define RCAR_AHB_BUS_MODE               (RCAR_AHB_BUS_MMODE_HTRANS |    \
  72                                         RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  73                                         RCAR_AHB_BUS_MMODE_WR_INCR |    \
  74                                         RCAR_AHB_BUS_MMODE_HBUS_REQ |   \
  75                                         RCAR_AHB_BUS_SMODE_READYCTR)
  76
  77 #define RCAR_USBCTR_REG                 (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  78 #define RCAR_USBCTR_USBH_RST            (1 << 0)
  79 #define RCAR_USBCTR_PCICLK_MASK         (1 << 1)
  80 #define RCAR_USBCTR_PLL_RST             (1 << 2)
  81 #define RCAR_USBCTR_DIRPD               (1 << 8)
  82 #define RCAR_USBCTR_PCIAHB_WIN2_EN      (1 << 9)
  83 #define RCAR_USBCTR_PCIAHB_WIN1_256M    (0 << 10)
  84 #define RCAR_USBCTR_PCIAHB_WIN1_512M    (1 << 10)
  85 #define RCAR_USBCTR_PCIAHB_WIN1_1G      (2 << 10)
  86 #define RCAR_USBCTR_PCIAHB_WIN1_2G      (3 << 10)
  87 #define RCAR_USBCTR_PCIAHB_WIN1_MASK    (3 << 10)
  88
  89 #define RCAR_PCI_ARBITER_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  90 #define RCAR_PCI_ARBITER_PCIREQ0        (1 << 0)
  91 #define RCAR_PCI_ARBITER_PCIREQ1        (1 << 1)
  92 #define RCAR_PCI_ARBITER_PCIBP_MODE     (1 << 12)
  93
  94 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  95
  96 struct rcar_pci_priv {
  97         struct device *dev;
  98         void __iomem *reg;
  99         struct resource io_res;
 100         struct resource mem_res;
 101         struct resource *cfg_res;
 102         unsigned busnr;
 103         int irq;
 104         unsigned long window_size;
 105 };
 106
 107 /* PCI configuration space operations */
 108 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
 109                                        int where)
 110 {
 111         struct pci_sys_data *sys = bus->sysdata;
 112         struct rcar_pci_priv *priv = sys->private_data;
 113         int slot, val;
 114
 115         if (sys->busnr != bus->number || PCI_FUNC(devfn))
 116                 return NULL;
 117
 118         /* Only one EHCI/OHCI device built-in */
 119         slot = PCI_SLOT(devfn);
 120         if (slot > 2)
 121                 return NULL;
 122
 123         /* bridge logic only has registers to 0x40 */
 124         if (slot == 0x0 && where >= 0x40)
 125                 return NULL;
 126
 127         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
 128                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 129
 130         iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
 131         return priv->reg + (slot >> 1) * 0x100 + where;
 132 }
 133
 134 /* PCI interrupt mapping */
 135 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 136 {
 137         struct pci_sys_data *sys = dev->bus->sysdata;
 138         struct rcar_pci_priv *priv = sys->private_data;
 139         int irq;
 140
 141         irq = of_irq_parse_and_map_pci(dev, slot, pin);
 142         if (!irq)
 143                 irq = priv->irq;
 144
 145         return irq;
 146 }
 147
 148 #ifdef CONFIG_PCI_DEBUG
 149 /* if debug enabled, then attach an error handler irq to the bridge */
 150
 151 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
 152 {
 153         struct rcar_pci_priv *priv = pw;
 154         u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
 155
 156         if (status & RCAR_PCI_INT_ALLERRORS) {
 157                 dev_err(priv->dev, "error irq: status %08x\n", status);
 158
 159                 /* clear the error(s) */
 160                 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
 161                           priv->reg + RCAR_PCI_INT_STATUS_REG);
 162                 return IRQ_HANDLED;
 163         }
 164
 165         return IRQ_NONE;
 166 }
 167
 168 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
 169 {
 170         int ret;
 171         u32 val;
 172
 173         ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
 174                                IRQF_SHARED, "error irq", priv);
 175         if (ret) {
 176                 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
 177                 return;
 178         }
 179
 180         val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
 181         val |= RCAR_PCI_INT_ALLERRORS;
 182         iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
 183 }
 184 #else
 185 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
 186 #endif
 187
 188 /* PCI host controller setup */
 189 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 190 {
 191         struct rcar_pci_priv *priv = sys->private_data;
 192         void __iomem *reg = priv->reg;
 193         u32 val;
 194
 195         pm_runtime_enable(priv->dev);
 196         pm_runtime_get_sync(priv->dev);
 197
 198         val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
 199         dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 200
 201         /* Disable Direct Power Down State and assert reset */
 202         val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 203         val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
 204         iowrite32(val, reg + RCAR_USBCTR_REG);
 205         udelay(4);
 206
 207         /* De-assert reset and reset PCIAHB window1 size */
 208         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
 209                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
 210
 211         /* Setup PCIAHB window1 size */
 212         switch (priv->window_size) {
 213         case SZ_2G:
 214                 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
 215                 break;
 216         case SZ_1G:
 217                 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
 218                 break;
 219         case SZ_512M:
 220                 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
 221                 break;
 222         default:
 223                 pr_warn("unknown window size %ld - defaulting to 256M\n",
 224                         priv->window_size);
 225                 priv->window_size = SZ_256M;
 226                 /* fall-through */
 227         case SZ_256M:
 228                 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
 229                 break;
 230         }
 231         iowrite32(val, reg + RCAR_USBCTR_REG);
 232
 233         /* Configure AHB master and slave modes */
 234         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
 235
 236         /* Configure PCI arbiter */
 237         val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
 238         val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
 239                RCAR_PCI_ARBITER_PCIBP_MODE;
 240         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 241
 242         /* PCI-AHB mapping: 0x40000000 base */
 243         iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
 244                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 245
 246         /* AHB-PCI mapping: OHCI/EHCI registers */
 247         val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
 248         iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
 249
 250         /* Enable AHB-PCI bridge PCI configuration access */
 251         iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
 252                   reg + RCAR_AHBPCI_WIN1_CTR_REG);
 253         /* Set PCI-AHB Window1 address */
 254         iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
 255                   reg + PCI_BASE_ADDRESS_1);
 256         /* Set AHB-PCI bridge PCI communication area address */
 257         val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
 258         iowrite32(val, reg + PCI_BASE_ADDRESS_0);
 259
 260         val = ioread32(reg + PCI_COMMAND);
 261         val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 262                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 263         iowrite32(val, reg + PCI_COMMAND);
 264
 265         /* Enable PCI interrupts */
 266         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
 267                   reg + RCAR_PCI_INT_ENABLE_REG);
 268
 269         if (priv->irq > 0)
 270                 rcar_pci_setup_errirq(priv);
 271
 272         /* Add PCI resources */
 273         pci_add_resource(&sys->resources, &priv->io_res);
 274         pci_add_resource(&sys->resources, &priv->mem_res);
 275
 276         /* Setup bus number based on platform device id / of bus-range */
 277         sys->busnr = priv->busnr;
 278         return 1;
 279 }
 280
 281 static struct pci_ops rcar_pci_ops = {
 282         .map_bus = rcar_pci_cfg_base,
 283         .read   = pci_generic_config_read,
 284         .write  = pci_generic_config_write,
 285 };
 286
 287 static int rcar_pci_probe(struct platform_device *pdev)
 288 {
 289         struct resource *cfg_res, *mem_res;
 290         struct rcar_pci_priv *priv;
 291         void __iomem *reg;
 292         struct hw_pci hw;
 293         void *hw_private[1];
 294
 295         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 296         reg = devm_ioremap_resource(&pdev->dev, cfg_res);
 297         if (IS_ERR(reg))
 298                 return PTR_ERR(reg);
 299
 300         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 301         if (!mem_res || !mem_res->start)
 302                 return -ENODEV;
 303
 304         if (mem_res->start & 0xFFFF)
 305                 return -EINVAL;
 306
 307         priv = devm_kzalloc(&pdev->dev,
 308                             sizeof(struct rcar_pci_priv), GFP_KERNEL);
 309         if (!priv)
 310                 return -ENOMEM;
 311
 312         priv->mem_res = *mem_res;
 313         /*
 314          * The controller does not support/use port I/O,
 315          * so setup a dummy port I/O region here.
 316          */
 317         priv->io_res.start = priv->mem_res.start;
 318         priv->io_res.end = priv->mem_res.end;
 319         priv->io_res.flags = IORESOURCE_IO;
 320
 321         priv->cfg_res = cfg_res;
 322
 323         priv->irq = platform_get_irq(pdev, 0);
 324         priv->reg = reg;
 325         priv->dev = &pdev->dev;
 326
 327         if (priv->irq < 0) {
 328                 dev_err(&pdev->dev, "no valid irq found\n");
 329                 return priv->irq;
 330         }
 331
 332         priv->window_size = SZ_1G;
 333
 334         if (pdev->dev.of_node) {
 335                 struct resource busnr;
 336                 int ret;
 337
 338                 ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
 339                 if (ret < 0) {
 340                         dev_err(&pdev->dev, "failed to parse bus-range\n");
 341                         return ret;
 342                 }
 343
 344                 priv->busnr = busnr.start;
 345                 if (busnr.end != busnr.start)
 346                         dev_warn(&pdev->dev, "only one bus number supported\n");
 347         } else {
 348                 priv->busnr = pdev->id;
 349         }
 350
 351         hw_private[0] = priv;
 352         memset(&hw, 0, sizeof(hw));
 353         hw.nr_controllers = ARRAY_SIZE(hw_private);
 354         hw.private_data = hw_private;
 355         hw.map_irq = rcar_pci_map_irq;
 356         hw.ops = &rcar_pci_ops;
 357         hw.setup = rcar_pci_setup;
 358         pci_common_init_dev(&pdev->dev, &hw);
 359         return 0;
 360 }
 361
 362 static struct of_device_id rcar_pci_of_match[] = {
 363         { .compatible = "renesas,pci-r8a7790", },
 364         { .compatible = "renesas,pci-r8a7791", },
 365         { .compatible = "renesas,pci-r8a7794", },
 366         { },
 367 };
 368
 369 MODULE_DEVICE_TABLE(of, rcar_pci_of_match);
 370
 371 static struct platform_driver rcar_pci_driver = {
 372         .driver = {
 373                 .name = "pci-rcar-gen2",
 374                 .suppress_bind_attrs = true,
 375                 .of_match_table = rcar_pci_of_match,
 376         },
 377         .probe = rcar_pci_probe,
 378 };
 379
 380 module_platform_driver(rcar_pci_driver);
 381
 382 MODULE_LICENSE("GPL v2");
 383 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
 384 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");