drivers/pci/host/pcie-hisi.c

   1 /*
   2  * PCIe host controller driver for HiSilicon Hip05 SoC
   3  *
   4  * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
   5  *
   6  * Author: Zhou Wang <wangzhou1@hisilicon.com>
   7  *         Dacai Zhu <zhudacai@hisilicon.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/interrupt.h>
  14 #include <linux/module.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20
  21 #include "pcie-designware.h"
  22
  23 #define PCIE_SUBCTRL_SYS_STATE4_REG                     0x6818
  24 #define PCIE_LTSSM_LINKUP_STATE                         0x11
  25 #define PCIE_LTSSM_STATE_MASK                           0x3F
  26
  27 #define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
  28
  29 struct hisi_pcie {
  30         struct regmap *subctrl;
  31         void __iomem *reg_base;
  32         u32 port_id;
  33         struct pcie_port pp;
  34 };
  35
  36 static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
  37                                         u32 val, u32 reg)
  38 {
  39         writel(val, pcie->reg_base + reg);
  40 }
  41
  42 static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
  43 {
  44         return readl(pcie->reg_base + reg);
  45 }
  46
  47 /* Hip05 PCIe host only supports 32-bit config access */
  48 static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
  49                               u32 *val)
  50 {
  51         u32 reg;
  52         u32 reg_val;
  53         struct hisi_pcie *pcie = to_hisi_pcie(pp);
  54         void *walker = &reg_val;
  55
  56         walker += (where & 0x3);
  57         reg = where & ~0x3;
  58         reg_val = hisi_pcie_apb_readl(pcie, reg);
  59
  60         if (size == 1)
  61                 *val = *(u8 __force *) walker;
  62         else if (size == 2)
  63                 *val = *(u16 __force *) walker;
  64         else if (size == 4)
  65                 *val = reg_val;
  66         else
  67                 return PCIBIOS_BAD_REGISTER_NUMBER;
  68
  69         return PCIBIOS_SUCCESSFUL;
  70 }
  71
  72 /* Hip05 PCIe host only supports 32-bit config access */
  73 static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int  size,
  74                                 u32 val)
  75 {
  76         u32 reg_val;
  77         u32 reg;
  78         struct hisi_pcie *pcie = to_hisi_pcie(pp);
  79         void *walker = &reg_val;
  80
  81         walker += (where & 0x3);
  82         reg = where & ~0x3;
  83         if (size == 4)
  84                 hisi_pcie_apb_writel(pcie, val, reg);
  85         else if (size == 2) {
  86                 reg_val = hisi_pcie_apb_readl(pcie, reg);
  87                 *(u16 __force *) walker = val;
  88                 hisi_pcie_apb_writel(pcie, reg_val, reg);
  89         } else if (size == 1) {
  90                 reg_val = hisi_pcie_apb_readl(pcie, reg);
  91                 *(u8 __force *) walker = val;
  92                 hisi_pcie_apb_writel(pcie, reg_val, reg);
  93         } else
  94                 return PCIBIOS_BAD_REGISTER_NUMBER;
  95
  96         return PCIBIOS_SUCCESSFUL;
  97 }
  98
  99 static int hisi_pcie_link_up(struct pcie_port *pp)
 100 {
 101         u32 val;
 102         struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
 103
 104         regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG +
 105                     0x100 * hisi_pcie->port_id, &val);
 106
 107         return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
 108 }
 109
 110 static struct pcie_host_ops hisi_pcie_host_ops = {
 111         .rd_own_conf = hisi_pcie_cfg_read,
 112         .wr_own_conf = hisi_pcie_cfg_write,
 113         .link_up = hisi_pcie_link_up,
 114 };
 115
 116 static int hisi_add_pcie_port(struct pcie_port *pp,
 117                                      struct platform_device *pdev)
 118 {
 119         int ret;
 120         u32 port_id;
 121         struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
 122
 123         if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) {
 124                 dev_err(&pdev->dev, "failed to read port-id\n");
 125                 return -EINVAL;
 126         }
 127         if (port_id > 3) {
 128                 dev_err(&pdev->dev, "Invalid port-id: %d\n", port_id);
 129                 return -EINVAL;
 130         }
 131         hisi_pcie->port_id = port_id;
 132
 133         pp->ops = &hisi_pcie_host_ops;
 134
 135         ret = dw_pcie_host_init(pp);
 136         if (ret) {
 137                 dev_err(&pdev->dev, "failed to initialize host\n");
 138                 return ret;
 139         }
 140
 141         return 0;
 142 }
 143
 144 static int hisi_pcie_probe(struct platform_device *pdev)
 145 {
 146         struct hisi_pcie *hisi_pcie;
 147         struct pcie_port *pp;
 148         struct resource *reg;
 149         int ret;
 150
 151         hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
 152         if (!hisi_pcie)
 153                 return -ENOMEM;
 154
 155         pp = &hisi_pcie->pp;
 156         pp->dev = &pdev->dev;
 157
 158         hisi_pcie->subctrl =
 159         syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
 160         if (IS_ERR(hisi_pcie->subctrl)) {
 161                 dev_err(pp->dev, "cannot get subctrl base\n");
 162                 return PTR_ERR(hisi_pcie->subctrl);
 163         }
 164
 165         reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
 166         hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg);
 167         if (IS_ERR(hisi_pcie->reg_base)) {
 168                 dev_err(pp->dev, "cannot get rc_dbi base\n");
 169                 return PTR_ERR(hisi_pcie->reg_base);
 170         }
 171
 172         hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
 173
 174         ret = hisi_add_pcie_port(pp, pdev);
 175         if (ret)
 176                 return ret;
 177
 178         platform_set_drvdata(pdev, hisi_pcie);
 179
 180         dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
 181
 182         return 0;
 183 }
 184
 185 static const struct of_device_id hisi_pcie_of_match[] = {
 186         {.compatible = "hisilicon,hip05-pcie",},
 187         {},
 188 };
 189
 190 MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
 191
 192 static struct platform_driver hisi_pcie_driver = {
 193         .probe  = hisi_pcie_probe,
 194         .driver = {
 195                    .name = "hisi-pcie",
 196                    .of_match_table = hisi_pcie_of_match,
 197         },
 198 };
 199
 200 module_platform_driver(hisi_pcie_driver);