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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / pci / host / pcie-rcar.c
blobf4fa6c537448cae9d25519a8697e212aa70facaa
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
30
31 #define DRV_NAME "rcar-pcie"
32
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE (1 << 31)
36 #define TYPE0 (0 << 8)
37 #define TYPE1 (1 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEMSITXR 0x000840
42
43 /* Transfer control */
44 #define PCIETCTLR 0x02000
45 #define CFINIT 1
46 #define PCIETSTR 0x02004
47 #define DATA_LINK_ACTIVE 1
48 #define PCIEERRFR 0x02020
49 #define UNSUPPORTED_REQUEST (1 << 4)
50 #define PCIEMSIFR 0x02044
51 #define PCIEMSIALR 0x02048
52 #define MSIFE 1
53 #define PCIEMSIAUR 0x0204c
54 #define PCIEMSIIER 0x02050
55
56 /* root port address */
57 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
58
59 /* local address reg & mask */
60 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
61 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
62 #define LAM_PREFETCH (1 << 3)
63 #define LAM_64BIT (1 << 2)
64 #define LAR_ENABLE (1 << 1)
65
66 /* PCIe address reg & mask */
67 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
68 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
69 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
70 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
71 #define PAR_ENABLE (1 << 31)
72 #define IO_SPACE (1 << 8)
73
74 /* Configuration */
75 #define PCICONF(x) (0x010000 + ((x) * 0x4))
76 #define PMCAP(x) (0x010040 + ((x) * 0x4))
77 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
78 #define VCCAP(x) (0x010100 + ((x) * 0x4))
79
80 /* link layer */
81 #define IDSETR1 0x011004
82 #define TLCTLR 0x011048
83 #define MACSR 0x011054
84 #define MACCTLR 0x011058
85 #define SCRAMBLE_DISABLE (1 << 27)
86
87 /* R-Car H1 PHY */
88 #define H1_PCIEPHYADRR 0x04000c
89 #define WRITE_CMD (1 << 16)
90 #define PHY_ACK (1 << 24)
91 #define RATE_POS 12
92 #define LANE_POS 8
93 #define ADR_POS 0
94 #define H1_PCIEPHYDOUTR 0x040014
95 #define H1_PCIEPHYSR 0x040018
96
97 #define INT_PCI_MSI_NR 32
98
99 #define RCONF(x) (PCICONF(0)+(x))
100 #define RPMCAP(x) (PMCAP(0)+(x))
101 #define REXPCAP(x) (EXPCAP(0)+(x))
102 #define RVCCAP(x) (VCCAP(0)+(x))
103
104 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
105 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
106 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
107
108 #define RCAR_PCI_MAX_RESOURCES 4
109 #define MAX_NR_INBOUND_MAPS 6
110
111 static unsigned long global_io_offset;
112
113 struct rcar_msi {
114 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
115 struct irq_domain *domain;
116 struct msi_controller chip;
117 unsigned long pages;
118 struct mutex lock;
119 int irq1;
120 int irq2;
121 };
122
123 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
124 {
125 return container_of(chip, struct rcar_msi, chip);
126 }
127
128 /* Structure representing the PCIe interface */
129 /*
130 * ARM pcibios functions expect the ARM struct pci_sys_data as the PCI
131 * sysdata. Add pci_sys_data as the first element in struct gen_pci so
132 * that when we use a gen_pci pointer as sysdata, it is also a pointer to
133 * a struct pci_sys_data.
134 */
135 struct rcar_pcie {
136 #ifdef CONFIG_ARM
137 struct pci_sys_data sys;
138 #endif
139 struct device *dev;
140 void __iomem *base;
141 struct resource res[RCAR_PCI_MAX_RESOURCES];
142 struct resource busn;
143 int root_bus_nr;
144 struct clk *clk;
145 struct clk *bus_clk;
146 struct rcar_msi msi;
147 };
148
149 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
150 unsigned long reg)
151 {
152 writel(val, pcie->base + reg);
153 }
154
155 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
156 unsigned long reg)
157 {
158 return readl(pcie->base + reg);
159 }
160
161 enum {
162 RCAR_PCI_ACCESS_READ,
163 RCAR_PCI_ACCESS_WRITE,
164 };
165
166 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
167 {
168 int shift = 8 * (where & 3);
169 u32 val = rcar_pci_read_reg(pcie, where & ~3);
170
171 val &= ~(mask << shift);
172 val |= data << shift;
173 rcar_pci_write_reg(pcie, val, where & ~3);
174 }
175
176 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
177 {
178 int shift = 8 * (where & 3);
179 u32 val = rcar_pci_read_reg(pcie, where & ~3);
180
181 return val >> shift;
182 }
183
184 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
185 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
186 unsigned char access_type, struct pci_bus *bus,
187 unsigned int devfn, int where, u32 *data)
188 {
189 int dev, func, reg, index;
190
191 dev = PCI_SLOT(devfn);
192 func = PCI_FUNC(devfn);
193 reg = where & ~3;
194 index = reg / 4;
195
196 /*
197 * While each channel has its own memory-mapped extended config
198 * space, it's generally only accessible when in endpoint mode.
199 * When in root complex mode, the controller is unable to target
200 * itself with either type 0 or type 1 accesses, and indeed, any
201 * controller initiated target transfer to its own config space
202 * result in a completer abort.
203 *
204 * Each channel effectively only supports a single device, but as
205 * the same channel <-> device access works for any PCI_SLOT()
206 * value, we cheat a bit here and bind the controller's config
207 * space to devfn 0 in order to enable self-enumeration. In this
208 * case the regular ECAR/ECDR path is sidelined and the mangled
209 * config access itself is initiated as an internal bus transaction.
210 */
211 if (pci_is_root_bus(bus)) {
212 if (dev != 0)
213 return PCIBIOS_DEVICE_NOT_FOUND;
214
215 if (access_type == RCAR_PCI_ACCESS_READ) {
216 *data = rcar_pci_read_reg(pcie, PCICONF(index));
217 } else {
218 /* Keep an eye out for changes to the root bus number */
219 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
220 pcie->root_bus_nr = *data & 0xff;
221
222 rcar_pci_write_reg(pcie, *data, PCICONF(index));
223 }
224
225 return PCIBIOS_SUCCESSFUL;
226 }
227
228 if (pcie->root_bus_nr < 0)
229 return PCIBIOS_DEVICE_NOT_FOUND;
230
231 /* Clear errors */
232 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
233
234 /* Set the PIO address */
235 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
236 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
237
238 /* Enable the configuration access */
239 if (bus->parent->number == pcie->root_bus_nr)
240 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
241 else
242 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
243
244 /* Check for errors */
245 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
246 return PCIBIOS_DEVICE_NOT_FOUND;
247
248 /* Check for master and target aborts */
249 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
250 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
251 return PCIBIOS_DEVICE_NOT_FOUND;
252
253 if (access_type == RCAR_PCI_ACCESS_READ)
254 *data = rcar_pci_read_reg(pcie, PCIECDR);
255 else
256 rcar_pci_write_reg(pcie, *data, PCIECDR);
257
258 /* Disable the configuration access */
259 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
260
261 return PCIBIOS_SUCCESSFUL;
262 }
263
264 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
265 int where, int size, u32 *val)
266 {
267 struct rcar_pcie *pcie = bus->sysdata;
268 int ret;
269
270 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
271 bus, devfn, where, val);
272 if (ret != PCIBIOS_SUCCESSFUL) {
273 *val = 0xffffffff;
274 return ret;
275 }
276
277 if (size == 1)
278 *val = (*val >> (8 * (where & 3))) & 0xff;
279 else if (size == 2)
280 *val = (*val >> (8 * (where & 2))) & 0xffff;
281
282 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
283 bus->number, devfn, where, size, (unsigned long)*val);
284
285 return ret;
286 }
287
288 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
289 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
290 int where, int size, u32 val)
291 {
292 struct rcar_pcie *pcie = bus->sysdata;
293 int shift, ret;
294 u32 data;
295
296 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
297 bus, devfn, where, &data);
298 if (ret != PCIBIOS_SUCCESSFUL)
299 return ret;
300
301 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
302 bus->number, devfn, where, size, (unsigned long)val);
303
304 if (size == 1) {
305 shift = 8 * (where & 3);
306 data &= ~(0xff << shift);
307 data |= ((val & 0xff) << shift);
308 } else if (size == 2) {
309 shift = 8 * (where & 2);
310 data &= ~(0xffff << shift);
311 data |= ((val & 0xffff) << shift);
312 } else
313 data = val;
314
315 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
316 bus, devfn, where, &data);
317
318 return ret;
319 }
320
321 static struct pci_ops rcar_pcie_ops = {
322 .read = rcar_pcie_read_conf,
323 .write = rcar_pcie_write_conf,
324 };
325
326 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie)
327 {
328 struct resource *res = &pcie->res[win];
329
330 /* Setup PCIe address space mappings for each resource */
331 resource_size_t size;
332 resource_size_t res_start;
333 u32 mask;
334
335 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
336
337 /*
338 * The PAMR mask is calculated in units of 128Bytes, which
339 * keeps things pretty simple.
340 */
341 size = resource_size(res);
342 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
343 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
344
345 if (res->flags & IORESOURCE_IO)
346 res_start = pci_pio_to_address(res->start);
347 else
348 res_start = res->start;
349
350 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
351 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
352 PCIEPALR(win));
353
354 /* First resource is for IO */
355 mask = PAR_ENABLE;
356 if (res->flags & IORESOURCE_IO)
357 mask |= IO_SPACE;
358
359 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
360 }
361
362 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pcie)
363 {
364 struct resource *res;
365 int i;
366
367 pcie->root_bus_nr = pcie->busn.start;
368
369 /* Setup PCI resources */
370 for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
371
372 res = &pcie->res[i];
373 if (!res->flags)
374 continue;
375
376 rcar_pcie_setup_window(i, pcie);
377
378 if (res->flags & IORESOURCE_IO) {
379 phys_addr_t io_start = pci_pio_to_address(res->start);
380 pci_ioremap_io(global_io_offset, io_start);
381 global_io_offset += SZ_64K;
382 }
383
384 pci_add_resource(resource, res);
385 }
386 pci_add_resource(resource, &pcie->busn);
387
388 return 1;
389 }
390
391 static int rcar_pcie_enable(struct rcar_pcie *pcie)
392 {
393 struct pci_bus *bus, *child;
394 LIST_HEAD(res);
395
396 rcar_pcie_setup(&res, pcie);
397
398 /* Do not reassign resources if probe only */
399 if (!pci_has_flag(PCI_PROBE_ONLY))
400 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
401
402 if (IS_ENABLED(CONFIG_PCI_MSI))
403 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
404 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
405 else
406 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
407 &rcar_pcie_ops, pcie, &res);
408
409 if (!bus) {
410 dev_err(pcie->dev, "Scanning rootbus failed");
411 return -ENODEV;
412 }
413
414 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
415
416 if (!pci_has_flag(PCI_PROBE_ONLY)) {
417 pci_bus_size_bridges(bus);
418 pci_bus_assign_resources(bus);
419
420 list_for_each_entry(child, &bus->children, node)
421 pcie_bus_configure_settings(child);
422 }
423
424 pci_bus_add_devices(bus);
425
426 return 0;
427 }
428
429 static int phy_wait_for_ack(struct rcar_pcie *pcie)
430 {
431 unsigned int timeout = 100;
432
433 while (timeout--) {
434 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
435 return 0;
436
437 udelay(100);
438 }
439
440 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
441
442 return -ETIMEDOUT;
443 }
444
445 static void phy_write_reg(struct rcar_pcie *pcie,
446 unsigned int rate, unsigned int addr,
447 unsigned int lane, unsigned int data)
448 {
449 unsigned long phyaddr;
450
451 phyaddr = WRITE_CMD |
452 ((rate & 1) << RATE_POS) |
453 ((lane & 0xf) << LANE_POS) |
454 ((addr & 0xff) << ADR_POS);
455
456 /* Set write data */
457 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
458 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
459
460 /* Ignore errors as they will be dealt with if the data link is down */
461 phy_wait_for_ack(pcie);
462
463 /* Clear command */
464 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
465 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
466
467 /* Ignore errors as they will be dealt with if the data link is down */
468 phy_wait_for_ack(pcie);
469 }
470
471 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
472 {
473 unsigned int timeout = 10;
474
475 while (timeout--) {
476 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
477 return 0;
478
479 msleep(5);
480 }
481
482 return -ETIMEDOUT;
483 }
484
485 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
486 {
487 int err;
488
489 /* Begin initialization */
490 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
491
492 /* Set mode */
493 rcar_pci_write_reg(pcie, 1, PCIEMSR);
494
495 /*
496 * Initial header for port config space is type 1, set the device
497 * class to match. Hardware takes care of propagating the IDSETR
498 * settings, so there is no need to bother with a quirk.
499 */
500 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
501
502 /*
503 * Setup Secondary Bus Number & Subordinate Bus Number, even though
504 * they aren't used, to avoid bridge being detected as broken.
505 */
506 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
507 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
508
509 /* Initialize default capabilities. */
510 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
511 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
512 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
513 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
514 PCI_HEADER_TYPE_BRIDGE);
515
516 /* Enable data link layer active state reporting */
517 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
518 PCI_EXP_LNKCAP_DLLLARC);
519
520 /* Write out the physical slot number = 0 */
521 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
522
523 /* Set the completion timer timeout to the maximum 50ms. */
524 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
525
526 /* Terminate list of capabilities (Next Capability Offset=0) */
527 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
528
529 /* Enable MSI */
530 if (IS_ENABLED(CONFIG_PCI_MSI))
531 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
532
533 /* Finish initialization - establish a PCI Express link */
534 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
535
536 /* This will timeout if we don't have a link. */
537 err = rcar_pcie_wait_for_dl(pcie);
538 if (err)
539 return err;
540
541 /* Enable INTx interrupts */
542 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
543
544 wmb();
545
546 return 0;
547 }
548
549 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
550 {
551 unsigned int timeout = 10;
552
553 /* Initialize the phy */
554 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
555 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
556 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
557 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
558 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
559 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
560 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
561 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
562 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
563 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
564 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
565 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
566
567 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
568 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
569 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
570
571 while (timeout--) {
572 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
573 return rcar_pcie_hw_init(pcie);
574
575 msleep(5);
576 }
577
578 return -ETIMEDOUT;
579 }
580
581 static int rcar_msi_alloc(struct rcar_msi *chip)
582 {
583 int msi;
584
585 mutex_lock(&chip->lock);
586
587 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
588 if (msi < INT_PCI_MSI_NR)
589 set_bit(msi, chip->used);
590 else
591 msi = -ENOSPC;
592
593 mutex_unlock(&chip->lock);
594
595 return msi;
596 }
597
598 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
599 {
600 mutex_lock(&chip->lock);
601 clear_bit(irq, chip->used);
602 mutex_unlock(&chip->lock);
603 }
604
605 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
606 {
607 struct rcar_pcie *pcie = data;
608 struct rcar_msi *msi = &pcie->msi;
609 unsigned long reg;
610
611 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
612
613 /* MSI & INTx share an interrupt - we only handle MSI here */
614 if (!reg)
615 return IRQ_NONE;
616
617 while (reg) {
618 unsigned int index = find_first_bit(&reg, 32);
619 unsigned int irq;
620
621 /* clear the interrupt */
622 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
623
624 irq = irq_find_mapping(msi->domain, index);
625 if (irq) {
626 if (test_bit(index, msi->used))
627 generic_handle_irq(irq);
628 else
629 dev_info(pcie->dev, "unhandled MSI\n");
630 } else {
631 /* Unknown MSI, just clear it */
632 dev_dbg(pcie->dev, "unexpected MSI\n");
633 }
634
635 /* see if there's any more pending in this vector */
636 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
637 }
638
639 return IRQ_HANDLED;
640 }
641
642 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
643 struct msi_desc *desc)
644 {
645 struct rcar_msi *msi = to_rcar_msi(chip);
646 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
647 struct msi_msg msg;
648 unsigned int irq;
649 int hwirq;
650
651 hwirq = rcar_msi_alloc(msi);
652 if (hwirq < 0)
653 return hwirq;
654
655 irq = irq_create_mapping(msi->domain, hwirq);
656 if (!irq) {
657 rcar_msi_free(msi, hwirq);
658 return -EINVAL;
659 }
660
661 irq_set_msi_desc(irq, desc);
662
663 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
664 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
665 msg.data = hwirq;
666
667 pci_write_msi_msg(irq, &msg);
668
669 return 0;
670 }
671
672 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
673 {
674 struct rcar_msi *msi = to_rcar_msi(chip);
675 struct irq_data *d = irq_get_irq_data(irq);
676
677 rcar_msi_free(msi, d->hwirq);
678 }
679
680 static struct irq_chip rcar_msi_irq_chip = {
681 .name = "R-Car PCIe MSI",
682 .irq_enable = pci_msi_unmask_irq,
683 .irq_disable = pci_msi_mask_irq,
684 .irq_mask = pci_msi_mask_irq,
685 .irq_unmask = pci_msi_unmask_irq,
686 };
687
688 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
689 irq_hw_number_t hwirq)
690 {
691 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
692 irq_set_chip_data(irq, domain->host_data);
693
694 return 0;
695 }
696
697 static const struct irq_domain_ops msi_domain_ops = {
698 .map = rcar_msi_map,
699 };
700
701 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
702 {
703 struct platform_device *pdev = to_platform_device(pcie->dev);
704 struct rcar_msi *msi = &pcie->msi;
705 unsigned long base;
706 int err;
707
708 mutex_init(&msi->lock);
709
710 msi->chip.dev = pcie->dev;
711 msi->chip.setup_irq = rcar_msi_setup_irq;
712 msi->chip.teardown_irq = rcar_msi_teardown_irq;
713
714 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
715 &msi_domain_ops, &msi->chip);
716 if (!msi->domain) {
717 dev_err(&pdev->dev, "failed to create IRQ domain\n");
718 return -ENOMEM;
719 }
720
721 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
722 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
723 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
724 if (err < 0) {
725 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
726 goto err;
727 }
728
729 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
730 IRQF_SHARED, rcar_msi_irq_chip.name, pcie);
731 if (err < 0) {
732 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
733 goto err;
734 }
735
736 /* setup MSI data target */
737 msi->pages = __get_free_pages(GFP_KERNEL, 0);
738 base = virt_to_phys((void *)msi->pages);
739
740 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
741 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
742
743 /* enable all MSI interrupts */
744 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
745
746 return 0;
747
748 err:
749 irq_domain_remove(msi->domain);
750 return err;
751 }
752
753 static int rcar_pcie_get_resources(struct platform_device *pdev,
754 struct rcar_pcie *pcie)
755 {
756 struct resource res;
757 int err, i;
758
759 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
760 if (err)
761 return err;
762
763 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
764 if (IS_ERR(pcie->clk)) {
765 dev_err(pcie->dev, "cannot get platform clock\n");
766 return PTR_ERR(pcie->clk);
767 }
768 err = clk_prepare_enable(pcie->clk);
769 if (err)
770 goto fail_clk;
771
772 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
773 if (IS_ERR(pcie->bus_clk)) {
774 dev_err(pcie->dev, "cannot get pcie bus clock\n");
775 err = PTR_ERR(pcie->bus_clk);
776 goto fail_clk;
777 }
778 err = clk_prepare_enable(pcie->bus_clk);
779 if (err)
780 goto err_map_reg;
781
782 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
783 if (!i) {
784 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
785 err = -ENOENT;
786 goto err_map_reg;
787 }
788 pcie->msi.irq1 = i;
789
790 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
791 if (!i) {
792 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
793 err = -ENOENT;
794 goto err_map_reg;
795 }
796 pcie->msi.irq2 = i;
797
798 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
799 if (IS_ERR(pcie->base)) {
800 err = PTR_ERR(pcie->base);
801 goto err_map_reg;
802 }
803
804 return 0;
805
806 err_map_reg:
807 clk_disable_unprepare(pcie->bus_clk);
808 fail_clk:
809 clk_disable_unprepare(pcie->clk);
810
811 return err;
812 }
813
814 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
815 struct of_pci_range *range,
816 int *index)
817 {
818 u64 restype = range->flags;
819 u64 cpu_addr = range->cpu_addr;
820 u64 cpu_end = range->cpu_addr + range->size;
821 u64 pci_addr = range->pci_addr;
822 u32 flags = LAM_64BIT | LAR_ENABLE;
823 u64 mask;
824 u64 size;
825 int idx = *index;
826
827 if (restype & IORESOURCE_PREFETCH)
828 flags |= LAM_PREFETCH;
829
830 /*
831 * If the size of the range is larger than the alignment of the start
832 * address, we have to use multiple entries to perform the mapping.
833 */
834 if (cpu_addr > 0) {
835 unsigned long nr_zeros = __ffs64(cpu_addr);
836 u64 alignment = 1ULL << nr_zeros;
837
838 size = min(range->size, alignment);
839 } else {
840 size = range->size;
841 }
842 /* Hardware supports max 4GiB inbound region */
843 size = min(size, 1ULL << 32);
844
845 mask = roundup_pow_of_two(size) - 1;
846 mask &= ~0xf;
847
848 while (cpu_addr < cpu_end) {
849 /*
850 * Set up 64-bit inbound regions as the range parser doesn't
851 * distinguish between 32 and 64-bit types.
852 */
853 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
854 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
855 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
856
857 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
858 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
859 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
860
861 pci_addr += size;
862 cpu_addr += size;
863 idx += 2;
864
865 if (idx > MAX_NR_INBOUND_MAPS) {
866 dev_err(pcie->dev, "Failed to map inbound regions!\n");
867 return -EINVAL;
868 }
869 }
870 *index = idx;
871
872 return 0;
873 }
874
875 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
876 struct device_node *node)
877 {
878 const int na = 3, ns = 2;
879 int rlen;
880
881 parser->node = node;
882 parser->pna = of_n_addr_cells(node);
883 parser->np = parser->pna + na + ns;
884
885 parser->range = of_get_property(node, "dma-ranges", &rlen);
886 if (!parser->range)
887 return -ENOENT;
888
889 parser->end = parser->range + rlen / sizeof(__be32);
890 return 0;
891 }
892
893 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
894 struct device_node *np)
895 {
896 struct of_pci_range range;
897 struct of_pci_range_parser parser;
898 int index = 0;
899 int err;
900
901 if (pci_dma_range_parser_init(&parser, np))
902 return -EINVAL;
903
904 /* Get the dma-ranges from DT */
905 for_each_of_pci_range(&parser, &range) {
906 u64 end = range.cpu_addr + range.size - 1;
907 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
908 range.flags, range.cpu_addr, end, range.pci_addr);
909
910 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
911 if (err)
912 return err;
913 }
914
915 return 0;
916 }
917
918 static const struct of_device_id rcar_pcie_of_match[] = {
919 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
920 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
921 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
922 {},
923 };
924 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
925
926 static int rcar_pcie_probe(struct platform_device *pdev)
927 {
928 struct rcar_pcie *pcie;
929 unsigned int data;
930 struct of_pci_range range;
931 struct of_pci_range_parser parser;
932 const struct of_device_id *of_id;
933 int err, win = 0;
934 int (*hw_init_fn)(struct rcar_pcie *);
935
936 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
937 if (!pcie)
938 return -ENOMEM;
939
940 pcie->dev = &pdev->dev;
941 platform_set_drvdata(pdev, pcie);
942
943 /* Get the bus range */
944 if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
945 dev_err(&pdev->dev, "failed to parse bus-range property\n");
946 return -EINVAL;
947 }
948
949 if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
950 dev_err(&pdev->dev, "missing ranges property\n");
951 return -EINVAL;
952 }
953
954 err = rcar_pcie_get_resources(pdev, pcie);
955 if (err < 0) {
956 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
957 return err;
958 }
959
960 for_each_of_pci_range(&parser, &range) {
961 err = of_pci_range_to_resource(&range, pdev->dev.of_node,
962 &pcie->res[win++]);
963 if (err < 0)
964 return err;
965
966 if (win > RCAR_PCI_MAX_RESOURCES)
967 break;
968 }
969
970 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
971 if (err)
972 return err;
973
974 if (IS_ENABLED(CONFIG_PCI_MSI)) {
975 err = rcar_pcie_enable_msi(pcie);
976 if (err < 0) {
977 dev_err(&pdev->dev,
978 "failed to enable MSI support: %d\n",
979 err);
980 return err;
981 }
982 }
983
984 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
985 if (!of_id || !of_id->data)
986 return -EINVAL;
987 hw_init_fn = of_id->data;
988
989 /* Failure to get a link might just be that no cards are inserted */
990 err = hw_init_fn(pcie);
991 if (err) {
992 dev_info(&pdev->dev, "PCIe link down\n");
993 return 0;
994 }
995
996 data = rcar_pci_read_reg(pcie, MACSR);
997 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
998
999 return rcar_pcie_enable(pcie);
1000 }
1001
1002 static struct platform_driver rcar_pcie_driver = {
1003 .driver = {
1004 .name = DRV_NAME,
1005 .of_match_table = rcar_pcie_of_match,
1006 .suppress_bind_attrs = true,
1007 },
1008 .probe = rcar_pcie_probe,
1009 };
1010 module_platform_driver(rcar_pcie_driver);
1011
1012 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1013 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1014 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support