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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / pci / probe.c
blob553a029e37f15586c96198a098cbb40de91ef49a
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
233 }
234
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
240
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
244 }
245
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
248
249 if (!sz64)
250 goto fail;
251
252 sz64 = pci_size(l64, sz64, mask64);
253 if (!sz64) {
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 pos);
256 goto fail;
257 }
258
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
263 res->start = 0;
264 res->end = 0;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
267 goto out;
268 }
269
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
273 res->start = 0;
274 res->end = sz64;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
277 goto out;
278 }
279 }
280
281 region.start = l64;
282 region.end = l64 + sz64;
283
284 pcibios_bus_to_resource(dev->bus, res, &region);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
286
287 /*
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
292 *
293 * resource_to_bus(bus_to_resource(A)) == A
294 *
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
297 */
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
300 res->start = 0;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
304 }
305
306 goto out;
307
308
309 fail:
310 res->flags = 0;
311 out:
312 if (res->flags)
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
316 }
317
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 {
320 unsigned int pos, reg;
321
322 for (pos = 0; pos < howmany; pos++) {
323 struct resource *res = &dev->resource[pos];
324 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
325 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
326 }
327
328 if (rom) {
329 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
330 dev->rom_base_reg = rom;
331 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
332 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
333 __pci_read_base(dev, pci_bar_mem32, res, rom);
334 }
335 }
336
337 static void pci_read_bridge_io(struct pci_bus *child)
338 {
339 struct pci_dev *dev = child->self;
340 u8 io_base_lo, io_limit_lo;
341 unsigned long io_mask, io_granularity, base, limit;
342 struct pci_bus_region region;
343 struct resource *res;
344
345 io_mask = PCI_IO_RANGE_MASK;
346 io_granularity = 0x1000;
347 if (dev->io_window_1k) {
348 /* Support 1K I/O space granularity */
349 io_mask = PCI_IO_1K_RANGE_MASK;
350 io_granularity = 0x400;
351 }
352
353 res = child->resource[0];
354 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
355 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
356 base = (io_base_lo & io_mask) << 8;
357 limit = (io_limit_lo & io_mask) << 8;
358
359 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
360 u16 io_base_hi, io_limit_hi;
361
362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
364 base |= ((unsigned long) io_base_hi << 16);
365 limit |= ((unsigned long) io_limit_hi << 16);
366 }
367
368 if (base <= limit) {
369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 region.start = base;
371 region.end = limit + io_granularity - 1;
372 pcibios_bus_to_resource(dev->bus, res, &region);
373 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
374 }
375 }
376
377 static void pci_read_bridge_mmio(struct pci_bus *child)
378 {
379 struct pci_dev *dev = child->self;
380 u16 mem_base_lo, mem_limit_lo;
381 unsigned long base, limit;
382 struct pci_bus_region region;
383 struct resource *res;
384
385 res = child->resource[1];
386 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
387 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
388 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
389 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
390 if (base <= limit) {
391 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
392 region.start = base;
393 region.end = limit + 0xfffff;
394 pcibios_bus_to_resource(dev->bus, res, &region);
395 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
396 }
397 }
398
399 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
400 {
401 struct pci_dev *dev = child->self;
402 u16 mem_base_lo, mem_limit_lo;
403 u64 base64, limit64;
404 pci_bus_addr_t base, limit;
405 struct pci_bus_region region;
406 struct resource *res;
407
408 res = child->resource[2];
409 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
410 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
411 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
412 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
413
414 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
415 u32 mem_base_hi, mem_limit_hi;
416
417 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
418 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
419
420 /*
421 * Some bridges set the base > limit by default, and some
422 * (broken) BIOSes do not initialize them. If we find
423 * this, just assume they are not being used.
424 */
425 if (mem_base_hi <= mem_limit_hi) {
426 base64 |= (u64) mem_base_hi << 32;
427 limit64 |= (u64) mem_limit_hi << 32;
428 }
429 }
430
431 base = (pci_bus_addr_t) base64;
432 limit = (pci_bus_addr_t) limit64;
433
434 if (base != base64) {
435 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
436 (unsigned long long) base64);
437 return;
438 }
439
440 if (base <= limit) {
441 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
442 IORESOURCE_MEM | IORESOURCE_PREFETCH;
443 if (res->flags & PCI_PREF_RANGE_TYPE_64)
444 res->flags |= IORESOURCE_MEM_64;
445 region.start = base;
446 region.end = limit + 0xfffff;
447 pcibios_bus_to_resource(dev->bus, res, &region);
448 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
449 }
450 }
451
452 void pci_read_bridge_bases(struct pci_bus *child)
453 {
454 struct pci_dev *dev = child->self;
455 struct resource *res;
456 int i;
457
458 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
459 return;
460
461 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
462 &child->busn_res,
463 dev->transparent ? " (subtractive decode)" : "");
464
465 pci_bus_remove_resources(child);
466 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
467 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
468
469 pci_read_bridge_io(child);
470 pci_read_bridge_mmio(child);
471 pci_read_bridge_mmio_pref(child);
472
473 if (dev->transparent) {
474 pci_bus_for_each_resource(child->parent, res, i) {
475 if (res && res->flags) {
476 pci_bus_add_resource(child, res,
477 PCI_SUBTRACTIVE_DECODE);
478 dev_printk(KERN_DEBUG, &dev->dev,
479 " bridge window %pR (subtractive decode)\n",
480 res);
481 }
482 }
483 }
484 }
485
486 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
487 {
488 struct pci_bus *b;
489
490 b = kzalloc(sizeof(*b), GFP_KERNEL);
491 if (!b)
492 return NULL;
493
494 INIT_LIST_HEAD(&b->node);
495 INIT_LIST_HEAD(&b->children);
496 INIT_LIST_HEAD(&b->devices);
497 INIT_LIST_HEAD(&b->slots);
498 INIT_LIST_HEAD(&b->resources);
499 b->max_bus_speed = PCI_SPEED_UNKNOWN;
500 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
501 #ifdef CONFIG_PCI_DOMAINS_GENERIC
502 if (parent)
503 b->domain_nr = parent->domain_nr;
504 #endif
505 return b;
506 }
507
508 static void pci_release_host_bridge_dev(struct device *dev)
509 {
510 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
511
512 if (bridge->release_fn)
513 bridge->release_fn(bridge);
514
515 pci_free_resource_list(&bridge->windows);
516
517 kfree(bridge);
518 }
519
520 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
521 {
522 struct pci_host_bridge *bridge;
523
524 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
525 if (!bridge)
526 return NULL;
527
528 INIT_LIST_HEAD(&bridge->windows);
529 bridge->bus = b;
530 return bridge;
531 }
532
533 static const unsigned char pcix_bus_speed[] = {
534 PCI_SPEED_UNKNOWN, /* 0 */
535 PCI_SPEED_66MHz_PCIX, /* 1 */
536 PCI_SPEED_100MHz_PCIX, /* 2 */
537 PCI_SPEED_133MHz_PCIX, /* 3 */
538 PCI_SPEED_UNKNOWN, /* 4 */
539 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
540 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
541 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
542 PCI_SPEED_UNKNOWN, /* 8 */
543 PCI_SPEED_66MHz_PCIX_266, /* 9 */
544 PCI_SPEED_100MHz_PCIX_266, /* A */
545 PCI_SPEED_133MHz_PCIX_266, /* B */
546 PCI_SPEED_UNKNOWN, /* C */
547 PCI_SPEED_66MHz_PCIX_533, /* D */
548 PCI_SPEED_100MHz_PCIX_533, /* E */
549 PCI_SPEED_133MHz_PCIX_533 /* F */
550 };
551
552 const unsigned char pcie_link_speed[] = {
553 PCI_SPEED_UNKNOWN, /* 0 */
554 PCIE_SPEED_2_5GT, /* 1 */
555 PCIE_SPEED_5_0GT, /* 2 */
556 PCIE_SPEED_8_0GT, /* 3 */
557 PCI_SPEED_UNKNOWN, /* 4 */
558 PCI_SPEED_UNKNOWN, /* 5 */
559 PCI_SPEED_UNKNOWN, /* 6 */
560 PCI_SPEED_UNKNOWN, /* 7 */
561 PCI_SPEED_UNKNOWN, /* 8 */
562 PCI_SPEED_UNKNOWN, /* 9 */
563 PCI_SPEED_UNKNOWN, /* A */
564 PCI_SPEED_UNKNOWN, /* B */
565 PCI_SPEED_UNKNOWN, /* C */
566 PCI_SPEED_UNKNOWN, /* D */
567 PCI_SPEED_UNKNOWN, /* E */
568 PCI_SPEED_UNKNOWN /* F */
569 };
570
571 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
572 {
573 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
574 }
575 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
576
577 static unsigned char agp_speeds[] = {
578 AGP_UNKNOWN,
579 AGP_1X,
580 AGP_2X,
581 AGP_4X,
582 AGP_8X
583 };
584
585 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
586 {
587 int index = 0;
588
589 if (agpstat & 4)
590 index = 3;
591 else if (agpstat & 2)
592 index = 2;
593 else if (agpstat & 1)
594 index = 1;
595 else
596 goto out;
597
598 if (agp3) {
599 index += 2;
600 if (index == 5)
601 index = 0;
602 }
603
604 out:
605 return agp_speeds[index];
606 }
607
608 static void pci_set_bus_speed(struct pci_bus *bus)
609 {
610 struct pci_dev *bridge = bus->self;
611 int pos;
612
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
614 if (!pos)
615 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
616 if (pos) {
617 u32 agpstat, agpcmd;
618
619 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
620 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
623 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
624 }
625
626 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
627 if (pos) {
628 u16 status;
629 enum pci_bus_speed max;
630
631 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
632 &status);
633
634 if (status & PCI_X_SSTATUS_533MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_533;
636 } else if (status & PCI_X_SSTATUS_266MHZ) {
637 max = PCI_SPEED_133MHz_PCIX_266;
638 } else if (status & PCI_X_SSTATUS_133MHZ) {
639 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
640 max = PCI_SPEED_133MHz_PCIX_ECC;
641 else
642 max = PCI_SPEED_133MHz_PCIX;
643 } else {
644 max = PCI_SPEED_66MHz_PCIX;
645 }
646
647 bus->max_bus_speed = max;
648 bus->cur_bus_speed = pcix_bus_speed[
649 (status & PCI_X_SSTATUS_FREQ) >> 6];
650
651 return;
652 }
653
654 if (pci_is_pcie(bridge)) {
655 u32 linkcap;
656 u16 linksta;
657
658 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
659 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
660
661 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
662 pcie_update_link_speed(bus, linksta);
663 }
664 }
665
666 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
667 {
668 struct irq_domain *d;
669
670 /*
671 * Any firmware interface that can resolve the msi_domain
672 * should be called from here.
673 */
674 d = pci_host_bridge_of_msi_domain(bus);
675 if (!d)
676 d = pci_host_bridge_acpi_msi_domain(bus);
677
678 return d;
679 }
680
681 static void pci_set_bus_msi_domain(struct pci_bus *bus)
682 {
683 struct irq_domain *d;
684 struct pci_bus *b;
685
686 /*
687 * The bus can be a root bus, a subordinate bus, or a virtual bus
688 * created by an SR-IOV device. Walk up to the first bridge device
689 * found or derive the domain from the host bridge.
690 */
691 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
692 if (b->self)
693 d = dev_get_msi_domain(&b->self->dev);
694 }
695
696 if (!d)
697 d = pci_host_bridge_msi_domain(b);
698
699 dev_set_msi_domain(&bus->dev, d);
700 }
701
702 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
703 struct pci_dev *bridge, int busnr)
704 {
705 struct pci_bus *child;
706 int i;
707 int ret;
708
709 /*
710 * Allocate a new bus, and inherit stuff from the parent..
711 */
712 child = pci_alloc_bus(parent);
713 if (!child)
714 return NULL;
715
716 child->parent = parent;
717 child->ops = parent->ops;
718 child->msi = parent->msi;
719 child->sysdata = parent->sysdata;
720 child->bus_flags = parent->bus_flags;
721
722 /* initialize some portions of the bus device, but don't register it
723 * now as the parent is not properly set up yet.
724 */
725 child->dev.class = &pcibus_class;
726 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
727
728 /*
729 * Set up the primary, secondary and subordinate
730 * bus numbers.
731 */
732 child->number = child->busn_res.start = busnr;
733 child->primary = parent->busn_res.start;
734 child->busn_res.end = 0xff;
735
736 if (!bridge) {
737 child->dev.parent = parent->bridge;
738 goto add_dev;
739 }
740
741 child->self = bridge;
742 child->bridge = get_device(&bridge->dev);
743 child->dev.parent = child->bridge;
744 pci_set_bus_of_node(child);
745 pci_set_bus_speed(child);
746
747 /* Set up default resource pointers and names.. */
748 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
749 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
750 child->resource[i]->name = child->name;
751 }
752 bridge->subordinate = child;
753
754 add_dev:
755 pci_set_bus_msi_domain(child);
756 ret = device_register(&child->dev);
757 WARN_ON(ret < 0);
758
759 pcibios_add_bus(child);
760
761 /* Create legacy_io and legacy_mem files for this bus */
762 pci_create_legacy_files(child);
763
764 return child;
765 }
766
767 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
768 int busnr)
769 {
770 struct pci_bus *child;
771
772 child = pci_alloc_child_bus(parent, dev, busnr);
773 if (child) {
774 down_write(&pci_bus_sem);
775 list_add_tail(&child->node, &parent->children);
776 up_write(&pci_bus_sem);
777 }
778 return child;
779 }
780 EXPORT_SYMBOL(pci_add_new_bus);
781
782 static void pci_enable_crs(struct pci_dev *pdev)
783 {
784 u16 root_cap = 0;
785
786 /* Enable CRS Software Visibility if supported */
787 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
788 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
789 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
790 PCI_EXP_RTCTL_CRSSVE);
791 }
792
793 /*
794 * If it's a bridge, configure it and scan the bus behind it.
795 * For CardBus bridges, we don't scan behind as the devices will
796 * be handled by the bridge driver itself.
797 *
798 * We need to process bridges in two passes -- first we scan those
799 * already configured by the BIOS and after we are done with all of
800 * them, we proceed to assigning numbers to the remaining buses in
801 * order to avoid overlaps between old and new bus numbers.
802 */
803 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
804 {
805 struct pci_bus *child;
806 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
807 u32 buses, i, j = 0;
808 u16 bctl;
809 u8 primary, secondary, subordinate;
810 int broken = 0;
811
812 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
813 primary = buses & 0xFF;
814 secondary = (buses >> 8) & 0xFF;
815 subordinate = (buses >> 16) & 0xFF;
816
817 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
818 secondary, subordinate, pass);
819
820 if (!primary && (primary != bus->number) && secondary && subordinate) {
821 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
822 primary = bus->number;
823 }
824
825 /* Check if setup is sensible at all */
826 if (!pass &&
827 (primary != bus->number || secondary <= bus->number ||
828 secondary > subordinate)) {
829 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
830 secondary, subordinate);
831 broken = 1;
832 }
833
834 /* Disable MasterAbortMode during probing to avoid reporting
835 of bus errors (in some architectures) */
836 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
837 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
838 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
839
840 pci_enable_crs(dev);
841
842 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
843 !is_cardbus && !broken) {
844 unsigned int cmax;
845 /*
846 * Bus already configured by firmware, process it in the first
847 * pass and just note the configuration.
848 */
849 if (pass)
850 goto out;
851
852 /*
853 * The bus might already exist for two reasons: Either we are
854 * rescanning the bus or the bus is reachable through more than
855 * one bridge. The second case can happen with the i450NX
856 * chipset.
857 */
858 child = pci_find_bus(pci_domain_nr(bus), secondary);
859 if (!child) {
860 child = pci_add_new_bus(bus, dev, secondary);
861 if (!child)
862 goto out;
863 child->primary = primary;
864 pci_bus_insert_busn_res(child, secondary, subordinate);
865 child->bridge_ctl = bctl;
866 }
867
868 cmax = pci_scan_child_bus(child);
869 if (cmax > subordinate)
870 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
871 subordinate, cmax);
872 /* subordinate should equal child->busn_res.end */
873 if (subordinate > max)
874 max = subordinate;
875 } else {
876 /*
877 * We need to assign a number to this bus which we always
878 * do in the second pass.
879 */
880 if (!pass) {
881 if (pcibios_assign_all_busses() || broken || is_cardbus)
882 /* Temporarily disable forwarding of the
883 configuration cycles on all bridges in
884 this bus segment to avoid possible
885 conflicts in the second pass between two
886 bridges programmed with overlapping
887 bus ranges. */
888 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
889 buses & ~0xffffff);
890 goto out;
891 }
892
893 /* Clear errors */
894 pci_write_config_word(dev, PCI_STATUS, 0xffff);
895
896 /* Prevent assigning a bus number that already exists.
897 * This can happen when a bridge is hot-plugged, so in
898 * this case we only re-scan this bus. */
899 child = pci_find_bus(pci_domain_nr(bus), max+1);
900 if (!child) {
901 child = pci_add_new_bus(bus, dev, max+1);
902 if (!child)
903 goto out;
904 pci_bus_insert_busn_res(child, max+1, 0xff);
905 }
906 max++;
907 buses = (buses & 0xff000000)
908 | ((unsigned int)(child->primary) << 0)
909 | ((unsigned int)(child->busn_res.start) << 8)
910 | ((unsigned int)(child->busn_res.end) << 16);
911
912 /*
913 * yenta.c forces a secondary latency timer of 176.
914 * Copy that behaviour here.
915 */
916 if (is_cardbus) {
917 buses &= ~0xff000000;
918 buses |= CARDBUS_LATENCY_TIMER << 24;
919 }
920
921 /*
922 * We need to blast all three values with a single write.
923 */
924 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
925
926 if (!is_cardbus) {
927 child->bridge_ctl = bctl;
928 max = pci_scan_child_bus(child);
929 } else {
930 /*
931 * For CardBus bridges, we leave 4 bus numbers
932 * as cards with a PCI-to-PCI bridge can be
933 * inserted later.
934 */
935 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
936 struct pci_bus *parent = bus;
937 if (pci_find_bus(pci_domain_nr(bus),
938 max+i+1))
939 break;
940 while (parent->parent) {
941 if ((!pcibios_assign_all_busses()) &&
942 (parent->busn_res.end > max) &&
943 (parent->busn_res.end <= max+i)) {
944 j = 1;
945 }
946 parent = parent->parent;
947 }
948 if (j) {
949 /*
950 * Often, there are two cardbus bridges
951 * -- try to leave one valid bus number
952 * for each one.
953 */
954 i /= 2;
955 break;
956 }
957 }
958 max += i;
959 }
960 /*
961 * Set the subordinate bus number to its real value.
962 */
963 pci_bus_update_busn_res_end(child, max);
964 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
965 }
966
967 sprintf(child->name,
968 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
969 pci_domain_nr(bus), child->number);
970
971 /* Has only triggered on CardBus, fixup is in yenta_socket */
972 while (bus->parent) {
973 if ((child->busn_res.end > bus->busn_res.end) ||
974 (child->number > bus->busn_res.end) ||
975 (child->number < bus->number) ||
976 (child->busn_res.end < bus->number)) {
977 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
978 &child->busn_res,
979 (bus->number > child->busn_res.end &&
980 bus->busn_res.end < child->number) ?
981 "wholly" : "partially",
982 bus->self->transparent ? " transparent" : "",
983 dev_name(&bus->dev),
984 &bus->busn_res);
985 }
986 bus = bus->parent;
987 }
988
989 out:
990 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
991
992 return max;
993 }
994 EXPORT_SYMBOL(pci_scan_bridge);
995
996 /*
997 * Read interrupt line and base address registers.
998 * The architecture-dependent code can tweak these, of course.
999 */
1000 static void pci_read_irq(struct pci_dev *dev)
1001 {
1002 unsigned char irq;
1003
1004 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1005 dev->pin = irq;
1006 if (irq)
1007 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1008 dev->irq = irq;
1009 }
1010
1011 void set_pcie_port_type(struct pci_dev *pdev)
1012 {
1013 int pos;
1014 u16 reg16;
1015 int type;
1016 struct pci_dev *parent;
1017
1018 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1019 if (!pos)
1020 return;
1021 pdev->pcie_cap = pos;
1022 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1023 pdev->pcie_flags_reg = reg16;
1024 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1025 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1026
1027 /*
1028 * A Root Port is always the upstream end of a Link. No PCIe
1029 * component has two Links. Two Links are connected by a Switch
1030 * that has a Port on each Link and internal logic to connect the
1031 * two Ports.
1032 */
1033 type = pci_pcie_type(pdev);
1034 if (type == PCI_EXP_TYPE_ROOT_PORT)
1035 pdev->has_secondary_link = 1;
1036 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1037 type == PCI_EXP_TYPE_DOWNSTREAM) {
1038 parent = pci_upstream_bridge(pdev);
1039
1040 /*
1041 * Usually there's an upstream device (Root Port or Switch
1042 * Downstream Port), but we can't assume one exists.
1043 */
1044 if (parent && !parent->has_secondary_link)
1045 pdev->has_secondary_link = 1;
1046 }
1047 }
1048
1049 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1050 {
1051 u32 reg32;
1052
1053 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1054 if (reg32 & PCI_EXP_SLTCAP_HPC)
1055 pdev->is_hotplug_bridge = 1;
1056 }
1057
1058 /**
1059 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1060 * @dev: PCI device
1061 *
1062 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1063 * when forwarding a type1 configuration request the bridge must check that
1064 * the extended register address field is zero. The bridge is not permitted
1065 * to forward the transactions and must handle it as an Unsupported Request.
1066 * Some bridges do not follow this rule and simply drop the extended register
1067 * bits, resulting in the standard config space being aliased, every 256
1068 * bytes across the entire configuration space. Test for this condition by
1069 * comparing the first dword of each potential alias to the vendor/device ID.
1070 * Known offenders:
1071 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1072 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1073 */
1074 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1075 {
1076 #ifdef CONFIG_PCI_QUIRKS
1077 int pos;
1078 u32 header, tmp;
1079
1080 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1081
1082 for (pos = PCI_CFG_SPACE_SIZE;
1083 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1084 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1085 || header != tmp)
1086 return false;
1087 }
1088
1089 return true;
1090 #else
1091 return false;
1092 #endif
1093 }
1094
1095 /**
1096 * pci_cfg_space_size - get the configuration space size of the PCI device.
1097 * @dev: PCI device
1098 *
1099 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1100 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1101 * access it. Maybe we don't have a way to generate extended config space
1102 * accesses, or the device is behind a reverse Express bridge. So we try
1103 * reading the dword at 0x100 which must either be 0 or a valid extended
1104 * capability header.
1105 */
1106 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1107 {
1108 u32 status;
1109 int pos = PCI_CFG_SPACE_SIZE;
1110
1111 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1112 goto fail;
1113 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1114 goto fail;
1115
1116 return PCI_CFG_SPACE_EXP_SIZE;
1117
1118 fail:
1119 return PCI_CFG_SPACE_SIZE;
1120 }
1121
1122 int pci_cfg_space_size(struct pci_dev *dev)
1123 {
1124 int pos;
1125 u32 status;
1126 u16 class;
1127
1128 class = dev->class >> 8;
1129 if (class == PCI_CLASS_BRIDGE_HOST)
1130 return pci_cfg_space_size_ext(dev);
1131
1132 if (!pci_is_pcie(dev)) {
1133 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1134 if (!pos)
1135 goto fail;
1136
1137 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1138 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1139 goto fail;
1140 }
1141
1142 return pci_cfg_space_size_ext(dev);
1143
1144 fail:
1145 return PCI_CFG_SPACE_SIZE;
1146 }
1147
1148 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1149
1150 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1151 {
1152 /*
1153 * Disable the MSI hardware to avoid screaming interrupts
1154 * during boot. This is the power on reset default so
1155 * usually this should be a noop.
1156 */
1157 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1158 if (dev->msi_cap)
1159 pci_msi_set_enable(dev, 0);
1160
1161 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1162 if (dev->msix_cap)
1163 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1164 }
1165
1166 /**
1167 * pci_setup_device - fill in class and map information of a device
1168 * @dev: the device structure to fill
1169 *
1170 * Initialize the device structure with information about the device's
1171 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1172 * Called at initialisation of the PCI subsystem and by CardBus services.
1173 * Returns 0 on success and negative if unknown type of device (not normal,
1174 * bridge or CardBus).
1175 */
1176 int pci_setup_device(struct pci_dev *dev)
1177 {
1178 u32 class;
1179 u8 hdr_type;
1180 int pos = 0;
1181 struct pci_bus_region region;
1182 struct resource *res;
1183
1184 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1185 return -EIO;
1186
1187 dev->sysdata = dev->bus->sysdata;
1188 dev->dev.parent = dev->bus->bridge;
1189 dev->dev.bus = &pci_bus_type;
1190 dev->hdr_type = hdr_type & 0x7f;
1191 dev->multifunction = !!(hdr_type & 0x80);
1192 dev->error_state = pci_channel_io_normal;
1193 set_pcie_port_type(dev);
1194
1195 pci_dev_assign_slot(dev);
1196 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1197 set this higher, assuming the system even supports it. */
1198 dev->dma_mask = 0xffffffff;
1199
1200 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1201 dev->bus->number, PCI_SLOT(dev->devfn),
1202 PCI_FUNC(dev->devfn));
1203
1204 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1205 dev->revision = class & 0xff;
1206 dev->class = class >> 8; /* upper 3 bytes */
1207
1208 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1209 dev->vendor, dev->device, dev->hdr_type, dev->class);
1210
1211 /* need to have dev->class ready */
1212 dev->cfg_size = pci_cfg_space_size(dev);
1213
1214 /* "Unknown power state" */
1215 dev->current_state = PCI_UNKNOWN;
1216
1217 pci_msi_setup_pci_dev(dev);
1218
1219 /* Early fixups, before probing the BARs */
1220 pci_fixup_device(pci_fixup_early, dev);
1221 /* device class may be changed after fixup */
1222 class = dev->class >> 8;
1223
1224 switch (dev->hdr_type) { /* header type */
1225 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1226 if (class == PCI_CLASS_BRIDGE_PCI)
1227 goto bad;
1228 pci_read_irq(dev);
1229 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1230 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1231 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1232
1233 /*
1234 * Do the ugly legacy mode stuff here rather than broken chip
1235 * quirk code. Legacy mode ATA controllers have fixed
1236 * addresses. These are not always echoed in BAR0-3, and
1237 * BAR0-3 in a few cases contain junk!
1238 */
1239 if (class == PCI_CLASS_STORAGE_IDE) {
1240 u8 progif;
1241 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1242 if ((progif & 1) == 0) {
1243 region.start = 0x1F0;
1244 region.end = 0x1F7;
1245 res = &dev->resource[0];
1246 res->flags = LEGACY_IO_RESOURCE;
1247 pcibios_bus_to_resource(dev->bus, res, &region);
1248 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1249 res);
1250 region.start = 0x3F6;
1251 region.end = 0x3F6;
1252 res = &dev->resource[1];
1253 res->flags = LEGACY_IO_RESOURCE;
1254 pcibios_bus_to_resource(dev->bus, res, &region);
1255 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1256 res);
1257 }
1258 if ((progif & 4) == 0) {
1259 region.start = 0x170;
1260 region.end = 0x177;
1261 res = &dev->resource[2];
1262 res->flags = LEGACY_IO_RESOURCE;
1263 pcibios_bus_to_resource(dev->bus, res, &region);
1264 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1265 res);
1266 region.start = 0x376;
1267 region.end = 0x376;
1268 res = &dev->resource[3];
1269 res->flags = LEGACY_IO_RESOURCE;
1270 pcibios_bus_to_resource(dev->bus, res, &region);
1271 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1272 res);
1273 }
1274 }
1275 break;
1276
1277 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1278 if (class != PCI_CLASS_BRIDGE_PCI)
1279 goto bad;
1280 /* The PCI-to-PCI bridge spec requires that subtractive
1281 decoding (i.e. transparent) bridge must have programming
1282 interface code of 0x01. */
1283 pci_read_irq(dev);
1284 dev->transparent = ((dev->class & 0xff) == 1);
1285 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1286 set_pcie_hotplug_bridge(dev);
1287 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1288 if (pos) {
1289 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1290 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1291 }
1292 break;
1293
1294 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1295 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1296 goto bad;
1297 pci_read_irq(dev);
1298 pci_read_bases(dev, 1, 0);
1299 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1300 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1301 break;
1302
1303 default: /* unknown header */
1304 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1305 dev->hdr_type);
1306 return -EIO;
1307
1308 bad:
1309 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1310 dev->class, dev->hdr_type);
1311 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1312 }
1313
1314 /* We found a fine healthy device, go go go... */
1315 return 0;
1316 }
1317
1318 static void pci_configure_mps(struct pci_dev *dev)
1319 {
1320 struct pci_dev *bridge = pci_upstream_bridge(dev);
1321 int mps, p_mps, rc;
1322
1323 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1324 return;
1325
1326 mps = pcie_get_mps(dev);
1327 p_mps = pcie_get_mps(bridge);
1328
1329 if (mps == p_mps)
1330 return;
1331
1332 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1333 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1334 mps, pci_name(bridge), p_mps);
1335 return;
1336 }
1337
1338 /*
1339 * Fancier MPS configuration is done later by
1340 * pcie_bus_configure_settings()
1341 */
1342 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1343 return;
1344
1345 rc = pcie_set_mps(dev, p_mps);
1346 if (rc) {
1347 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1348 p_mps);
1349 return;
1350 }
1351
1352 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1353 p_mps, mps, 128 << dev->pcie_mpss);
1354 }
1355
1356 static struct hpp_type0 pci_default_type0 = {
1357 .revision = 1,
1358 .cache_line_size = 8,
1359 .latency_timer = 0x40,
1360 .enable_serr = 0,
1361 .enable_perr = 0,
1362 };
1363
1364 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1365 {
1366 u16 pci_cmd, pci_bctl;
1367
1368 if (!hpp)
1369 hpp = &pci_default_type0;
1370
1371 if (hpp->revision > 1) {
1372 dev_warn(&dev->dev,
1373 "PCI settings rev %d not supported; using defaults\n",
1374 hpp->revision);
1375 hpp = &pci_default_type0;
1376 }
1377
1378 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1379 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1380 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1381 if (hpp->enable_serr)
1382 pci_cmd |= PCI_COMMAND_SERR;
1383 if (hpp->enable_perr)
1384 pci_cmd |= PCI_COMMAND_PARITY;
1385 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1386
1387 /* Program bridge control value */
1388 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1389 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1390 hpp->latency_timer);
1391 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1392 if (hpp->enable_serr)
1393 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1394 if (hpp->enable_perr)
1395 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1396 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1397 }
1398 }
1399
1400 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1401 {
1402 if (hpp)
1403 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1404 }
1405
1406 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1407 {
1408 int pos;
1409 u32 reg32;
1410
1411 if (!hpp)
1412 return;
1413
1414 if (hpp->revision > 1) {
1415 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1416 hpp->revision);
1417 return;
1418 }
1419
1420 /*
1421 * Don't allow _HPX to change MPS or MRRS settings. We manage
1422 * those to make sure they're consistent with the rest of the
1423 * platform.
1424 */
1425 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1426 PCI_EXP_DEVCTL_READRQ;
1427 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1428 PCI_EXP_DEVCTL_READRQ);
1429
1430 /* Initialize Device Control Register */
1431 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1432 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1433
1434 /* Initialize Link Control Register */
1435 if (pcie_cap_has_lnkctl(dev))
1436 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1437 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1438
1439 /* Find Advanced Error Reporting Enhanced Capability */
1440 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1441 if (!pos)
1442 return;
1443
1444 /* Initialize Uncorrectable Error Mask Register */
1445 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1446 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1447 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1448
1449 /* Initialize Uncorrectable Error Severity Register */
1450 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1451 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1452 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1453
1454 /* Initialize Correctable Error Mask Register */
1455 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1456 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1457 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1458
1459 /* Initialize Advanced Error Capabilities and Control Register */
1460 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1461 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1462 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1463
1464 /*
1465 * FIXME: The following two registers are not supported yet.
1466 *
1467 * o Secondary Uncorrectable Error Severity Register
1468 * o Secondary Uncorrectable Error Mask Register
1469 */
1470 }
1471
1472 static void pci_configure_device(struct pci_dev *dev)
1473 {
1474 struct hotplug_params hpp;
1475 int ret;
1476
1477 pci_configure_mps(dev);
1478
1479 memset(&hpp, 0, sizeof(hpp));
1480 ret = pci_get_hp_params(dev, &hpp);
1481 if (ret)
1482 return;
1483
1484 program_hpp_type2(dev, hpp.t2);
1485 program_hpp_type1(dev, hpp.t1);
1486 program_hpp_type0(dev, hpp.t0);
1487 }
1488
1489 static void pci_release_capabilities(struct pci_dev *dev)
1490 {
1491 pci_vpd_release(dev);
1492 pci_iov_release(dev);
1493 pci_free_cap_save_buffers(dev);
1494 }
1495
1496 /**
1497 * pci_release_dev - free a pci device structure when all users of it are finished.
1498 * @dev: device that's been disconnected
1499 *
1500 * Will be called only by the device core when all users of this pci device are
1501 * done.
1502 */
1503 static void pci_release_dev(struct device *dev)
1504 {
1505 struct pci_dev *pci_dev;
1506
1507 pci_dev = to_pci_dev(dev);
1508 pci_release_capabilities(pci_dev);
1509 pci_release_of_node(pci_dev);
1510 pcibios_release_device(pci_dev);
1511 pci_bus_put(pci_dev->bus);
1512 kfree(pci_dev->driver_override);
1513 kfree(pci_dev);
1514 }
1515
1516 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1517 {
1518 struct pci_dev *dev;
1519
1520 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1521 if (!dev)
1522 return NULL;
1523
1524 INIT_LIST_HEAD(&dev->bus_list);
1525 dev->dev.type = &pci_dev_type;
1526 dev->bus = pci_bus_get(bus);
1527
1528 return dev;
1529 }
1530 EXPORT_SYMBOL(pci_alloc_dev);
1531
1532 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1533 int crs_timeout)
1534 {
1535 int delay = 1;
1536
1537 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1538 return false;
1539
1540 /* some broken boards return 0 or ~0 if a slot is empty: */
1541 if (*l == 0xffffffff || *l == 0x00000000 ||
1542 *l == 0x0000ffff || *l == 0xffff0000)
1543 return false;
1544
1545 /*
1546 * Configuration Request Retry Status. Some root ports return the
1547 * actual device ID instead of the synthetic ID (0xFFFF) required
1548 * by the PCIe spec. Ignore the device ID and only check for
1549 * (vendor id == 1).
1550 */
1551 while ((*l & 0xffff) == 0x0001) {
1552 if (!crs_timeout)
1553 return false;
1554
1555 msleep(delay);
1556 delay *= 2;
1557 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1558 return false;
1559 /* Card hasn't responded in 60 seconds? Must be stuck. */
1560 if (delay > crs_timeout) {
1561 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1562 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1563 PCI_FUNC(devfn));
1564 return false;
1565 }
1566 }
1567
1568 return true;
1569 }
1570 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1571
1572 /*
1573 * Read the config data for a PCI device, sanity-check it
1574 * and fill in the dev structure...
1575 */
1576 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1577 {
1578 struct pci_dev *dev;
1579 u32 l;
1580
1581 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1582 return NULL;
1583
1584 dev = pci_alloc_dev(bus);
1585 if (!dev)
1586 return NULL;
1587
1588 dev->devfn = devfn;
1589 dev->vendor = l & 0xffff;
1590 dev->device = (l >> 16) & 0xffff;
1591
1592 pci_set_of_node(dev);
1593
1594 if (pci_setup_device(dev)) {
1595 pci_bus_put(dev->bus);
1596 kfree(dev);
1597 return NULL;
1598 }
1599
1600 return dev;
1601 }
1602
1603 static void pci_init_capabilities(struct pci_dev *dev)
1604 {
1605 /* Enhanced Allocation */
1606 pci_ea_init(dev);
1607
1608 /* MSI/MSI-X list */
1609 pci_msi_init_pci_dev(dev);
1610
1611 /* Buffers for saving PCIe and PCI-X capabilities */
1612 pci_allocate_cap_save_buffers(dev);
1613
1614 /* Power Management */
1615 pci_pm_init(dev);
1616
1617 /* Vital Product Data */
1618 pci_vpd_pci22_init(dev);
1619
1620 /* Alternative Routing-ID Forwarding */
1621 pci_configure_ari(dev);
1622
1623 /* Single Root I/O Virtualization */
1624 pci_iov_init(dev);
1625
1626 /* Address Translation Services */
1627 pci_ats_init(dev);
1628
1629 /* Enable ACS P2P upstream forwarding */
1630 pci_enable_acs(dev);
1631
1632 pci_cleanup_aer_error_status_regs(dev);
1633 }
1634
1635 /*
1636 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1637 * devices. Firmware interfaces that can select the MSI domain on a
1638 * per-device basis should be called from here.
1639 */
1640 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1641 {
1642 struct irq_domain *d;
1643
1644 /*
1645 * If a domain has been set through the pcibios_add_device
1646 * callback, then this is the one (platform code knows best).
1647 */
1648 d = dev_get_msi_domain(&dev->dev);
1649 if (d)
1650 return d;
1651
1652 /*
1653 * Let's see if we have a firmware interface able to provide
1654 * the domain.
1655 */
1656 d = pci_msi_get_device_domain(dev);
1657 if (d)
1658 return d;
1659
1660 return NULL;
1661 }
1662
1663 static void pci_set_msi_domain(struct pci_dev *dev)
1664 {
1665 struct irq_domain *d;
1666
1667 /*
1668 * If the platform or firmware interfaces cannot supply a
1669 * device-specific MSI domain, then inherit the default domain
1670 * from the host bridge itself.
1671 */
1672 d = pci_dev_msi_domain(dev);
1673 if (!d)
1674 d = dev_get_msi_domain(&dev->bus->dev);
1675
1676 dev_set_msi_domain(&dev->dev, d);
1677 }
1678
1679 /**
1680 * pci_dma_configure - Setup DMA configuration
1681 * @dev: ptr to pci_dev struct of the PCI device
1682 *
1683 * Function to update PCI devices's DMA configuration using the same
1684 * info from the OF node or ACPI node of host bridge's parent (if any).
1685 */
1686 static void pci_dma_configure(struct pci_dev *dev)
1687 {
1688 struct device *bridge = pci_get_host_bridge_device(dev);
1689
1690 if (IS_ENABLED(CONFIG_OF) &&
1691 bridge->parent && bridge->parent->of_node) {
1692 of_dma_configure(&dev->dev, bridge->parent->of_node);
1693 } else if (has_acpi_companion(bridge)) {
1694 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1695 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1696
1697 if (attr == DEV_DMA_NOT_SUPPORTED)
1698 dev_warn(&dev->dev, "DMA not supported.\n");
1699 else
1700 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1701 attr == DEV_DMA_COHERENT);
1702 }
1703
1704 pci_put_host_bridge_device(bridge);
1705 }
1706
1707 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1708 {
1709 int ret;
1710
1711 pci_configure_device(dev);
1712
1713 device_initialize(&dev->dev);
1714 dev->dev.release = pci_release_dev;
1715
1716 set_dev_node(&dev->dev, pcibus_to_node(bus));
1717 dev->dev.dma_mask = &dev->dma_mask;
1718 dev->dev.dma_parms = &dev->dma_parms;
1719 dev->dev.coherent_dma_mask = 0xffffffffull;
1720 pci_dma_configure(dev);
1721
1722 pci_set_dma_max_seg_size(dev, 65536);
1723 pci_set_dma_seg_boundary(dev, 0xffffffff);
1724
1725 /* Fix up broken headers */
1726 pci_fixup_device(pci_fixup_header, dev);
1727
1728 /* moved out from quirk header fixup code */
1729 pci_reassigndev_resource_alignment(dev);
1730
1731 /* Clear the state_saved flag. */
1732 dev->state_saved = false;
1733
1734 /* Initialize various capabilities */
1735 pci_init_capabilities(dev);
1736
1737 /*
1738 * Add the device to our list of discovered devices
1739 * and the bus list for fixup functions, etc.
1740 */
1741 down_write(&pci_bus_sem);
1742 list_add_tail(&dev->bus_list, &bus->devices);
1743 up_write(&pci_bus_sem);
1744
1745 ret = pcibios_add_device(dev);
1746 WARN_ON(ret < 0);
1747
1748 /* Setup MSI irq domain */
1749 pci_set_msi_domain(dev);
1750
1751 /* Notifier could use PCI capabilities */
1752 dev->match_driver = false;
1753 ret = device_add(&dev->dev);
1754 WARN_ON(ret < 0);
1755 }
1756
1757 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1758 {
1759 struct pci_dev *dev;
1760
1761 dev = pci_get_slot(bus, devfn);
1762 if (dev) {
1763 pci_dev_put(dev);
1764 return dev;
1765 }
1766
1767 dev = pci_scan_device(bus, devfn);
1768 if (!dev)
1769 return NULL;
1770
1771 pci_device_add(dev, bus);
1772
1773 return dev;
1774 }
1775 EXPORT_SYMBOL(pci_scan_single_device);
1776
1777 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1778 {
1779 int pos;
1780 u16 cap = 0;
1781 unsigned next_fn;
1782
1783 if (pci_ari_enabled(bus)) {
1784 if (!dev)
1785 return 0;
1786 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1787 if (!pos)
1788 return 0;
1789
1790 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1791 next_fn = PCI_ARI_CAP_NFN(cap);
1792 if (next_fn <= fn)
1793 return 0; /* protect against malformed list */
1794
1795 return next_fn;
1796 }
1797
1798 /* dev may be NULL for non-contiguous multifunction devices */
1799 if (!dev || dev->multifunction)
1800 return (fn + 1) % 8;
1801
1802 return 0;
1803 }
1804
1805 static int only_one_child(struct pci_bus *bus)
1806 {
1807 struct pci_dev *parent = bus->self;
1808
1809 if (!parent || !pci_is_pcie(parent))
1810 return 0;
1811 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1812 return 1;
1813 if (parent->has_secondary_link &&
1814 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1815 return 1;
1816 return 0;
1817 }
1818
1819 /**
1820 * pci_scan_slot - scan a PCI slot on a bus for devices.
1821 * @bus: PCI bus to scan
1822 * @devfn: slot number to scan (must have zero function.)
1823 *
1824 * Scan a PCI slot on the specified PCI bus for devices, adding
1825 * discovered devices to the @bus->devices list. New devices
1826 * will not have is_added set.
1827 *
1828 * Returns the number of new devices found.
1829 */
1830 int pci_scan_slot(struct pci_bus *bus, int devfn)
1831 {
1832 unsigned fn, nr = 0;
1833 struct pci_dev *dev;
1834
1835 if (only_one_child(bus) && (devfn > 0))
1836 return 0; /* Already scanned the entire slot */
1837
1838 dev = pci_scan_single_device(bus, devfn);
1839 if (!dev)
1840 return 0;
1841 if (!dev->is_added)
1842 nr++;
1843
1844 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1845 dev = pci_scan_single_device(bus, devfn + fn);
1846 if (dev) {
1847 if (!dev->is_added)
1848 nr++;
1849 dev->multifunction = 1;
1850 }
1851 }
1852
1853 /* only one slot has pcie device */
1854 if (bus->self && nr)
1855 pcie_aspm_init_link_state(bus->self);
1856
1857 return nr;
1858 }
1859 EXPORT_SYMBOL(pci_scan_slot);
1860
1861 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1862 {
1863 u8 *smpss = data;
1864
1865 if (!pci_is_pcie(dev))
1866 return 0;
1867
1868 /*
1869 * We don't have a way to change MPS settings on devices that have
1870 * drivers attached. A hot-added device might support only the minimum
1871 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1872 * where devices may be hot-added, we limit the fabric MPS to 128 so
1873 * hot-added devices will work correctly.
1874 *
1875 * However, if we hot-add a device to a slot directly below a Root
1876 * Port, it's impossible for there to be other existing devices below
1877 * the port. We don't limit the MPS in this case because we can
1878 * reconfigure MPS on both the Root Port and the hot-added device,
1879 * and there are no other devices involved.
1880 *
1881 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1882 */
1883 if (dev->is_hotplug_bridge &&
1884 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1885 *smpss = 0;
1886
1887 if (*smpss > dev->pcie_mpss)
1888 *smpss = dev->pcie_mpss;
1889
1890 return 0;
1891 }
1892
1893 static void pcie_write_mps(struct pci_dev *dev, int mps)
1894 {
1895 int rc;
1896
1897 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1898 mps = 128 << dev->pcie_mpss;
1899
1900 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1901 dev->bus->self)
1902 /* For "Performance", the assumption is made that
1903 * downstream communication will never be larger than
1904 * the MRRS. So, the MPS only needs to be configured
1905 * for the upstream communication. This being the case,
1906 * walk from the top down and set the MPS of the child
1907 * to that of the parent bus.
1908 *
1909 * Configure the device MPS with the smaller of the
1910 * device MPSS or the bridge MPS (which is assumed to be
1911 * properly configured at this point to the largest
1912 * allowable MPS based on its parent bus).
1913 */
1914 mps = min(mps, pcie_get_mps(dev->bus->self));
1915 }
1916
1917 rc = pcie_set_mps(dev, mps);
1918 if (rc)
1919 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1920 }
1921
1922 static void pcie_write_mrrs(struct pci_dev *dev)
1923 {
1924 int rc, mrrs;
1925
1926 /* In the "safe" case, do not configure the MRRS. There appear to be
1927 * issues with setting MRRS to 0 on a number of devices.
1928 */
1929 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1930 return;
1931
1932 /* For Max performance, the MRRS must be set to the largest supported
1933 * value. However, it cannot be configured larger than the MPS the
1934 * device or the bus can support. This should already be properly
1935 * configured by a prior call to pcie_write_mps.
1936 */
1937 mrrs = pcie_get_mps(dev);
1938
1939 /* MRRS is a R/W register. Invalid values can be written, but a
1940 * subsequent read will verify if the value is acceptable or not.
1941 * If the MRRS value provided is not acceptable (e.g., too large),
1942 * shrink the value until it is acceptable to the HW.
1943 */
1944 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1945 rc = pcie_set_readrq(dev, mrrs);
1946 if (!rc)
1947 break;
1948
1949 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1950 mrrs /= 2;
1951 }
1952
1953 if (mrrs < 128)
1954 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1955 }
1956
1957 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1958 {
1959 int mps, orig_mps;
1960
1961 if (!pci_is_pcie(dev))
1962 return 0;
1963
1964 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1965 pcie_bus_config == PCIE_BUS_DEFAULT)
1966 return 0;
1967
1968 mps = 128 << *(u8 *)data;
1969 orig_mps = pcie_get_mps(dev);
1970
1971 pcie_write_mps(dev, mps);
1972 pcie_write_mrrs(dev);
1973
1974 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1975 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1976 orig_mps, pcie_get_readrq(dev));
1977
1978 return 0;
1979 }
1980
1981 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1982 * parents then children fashion. If this changes, then this code will not
1983 * work as designed.
1984 */
1985 void pcie_bus_configure_settings(struct pci_bus *bus)
1986 {
1987 u8 smpss = 0;
1988
1989 if (!bus->self)
1990 return;
1991
1992 if (!pci_is_pcie(bus->self))
1993 return;
1994
1995 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1996 * to be aware of the MPS of the destination. To work around this,
1997 * simply force the MPS of the entire system to the smallest possible.
1998 */
1999 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2000 smpss = 0;
2001
2002 if (pcie_bus_config == PCIE_BUS_SAFE) {
2003 smpss = bus->self->pcie_mpss;
2004
2005 pcie_find_smpss(bus->self, &smpss);
2006 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2007 }
2008
2009 pcie_bus_configure_set(bus->self, &smpss);
2010 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2011 }
2012 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2013
2014 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2015 {
2016 unsigned int devfn, pass, max = bus->busn_res.start;
2017 struct pci_dev *dev;
2018
2019 dev_dbg(&bus->dev, "scanning bus\n");
2020
2021 /* Go find them, Rover! */
2022 for (devfn = 0; devfn < 0x100; devfn += 8)
2023 pci_scan_slot(bus, devfn);
2024
2025 /* Reserve buses for SR-IOV capability. */
2026 max += pci_iov_bus_range(bus);
2027
2028 /*
2029 * After performing arch-dependent fixup of the bus, look behind
2030 * all PCI-to-PCI bridges on this bus.
2031 */
2032 if (!bus->is_added) {
2033 dev_dbg(&bus->dev, "fixups for bus\n");
2034 pcibios_fixup_bus(bus);
2035 bus->is_added = 1;
2036 }
2037
2038 for (pass = 0; pass < 2; pass++)
2039 list_for_each_entry(dev, &bus->devices, bus_list) {
2040 if (pci_is_bridge(dev))
2041 max = pci_scan_bridge(bus, dev, max, pass);
2042 }
2043
2044 /*
2045 * We've scanned the bus and so we know all about what's on
2046 * the other side of any bridges that may be on this bus plus
2047 * any devices.
2048 *
2049 * Return how far we've got finding sub-buses.
2050 */
2051 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2052 return max;
2053 }
2054 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2055
2056 /**
2057 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2058 * @bridge: Host bridge to set up.
2059 *
2060 * Default empty implementation. Replace with an architecture-specific setup
2061 * routine, if necessary.
2062 */
2063 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2064 {
2065 return 0;
2066 }
2067
2068 void __weak pcibios_add_bus(struct pci_bus *bus)
2069 {
2070 }
2071
2072 void __weak pcibios_remove_bus(struct pci_bus *bus)
2073 {
2074 }
2075
2076 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2077 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2078 {
2079 int error;
2080 struct pci_host_bridge *bridge;
2081 struct pci_bus *b, *b2;
2082 struct resource_entry *window, *n;
2083 struct resource *res;
2084 resource_size_t offset;
2085 char bus_addr[64];
2086 char *fmt;
2087
2088 b = pci_alloc_bus(NULL);
2089 if (!b)
2090 return NULL;
2091
2092 b->sysdata = sysdata;
2093 b->ops = ops;
2094 b->number = b->busn_res.start = bus;
2095 pci_bus_assign_domain_nr(b, parent);
2096 b2 = pci_find_bus(pci_domain_nr(b), bus);
2097 if (b2) {
2098 /* If we already got to this bus through a different bridge, ignore it */
2099 dev_dbg(&b2->dev, "bus already known\n");
2100 goto err_out;
2101 }
2102
2103 bridge = pci_alloc_host_bridge(b);
2104 if (!bridge)
2105 goto err_out;
2106
2107 bridge->dev.parent = parent;
2108 bridge->dev.release = pci_release_host_bridge_dev;
2109 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2110 error = pcibios_root_bridge_prepare(bridge);
2111 if (error) {
2112 kfree(bridge);
2113 goto err_out;
2114 }
2115
2116 error = device_register(&bridge->dev);
2117 if (error) {
2118 put_device(&bridge->dev);
2119 goto err_out;
2120 }
2121 b->bridge = get_device(&bridge->dev);
2122 device_enable_async_suspend(b->bridge);
2123 pci_set_bus_of_node(b);
2124 pci_set_bus_msi_domain(b);
2125
2126 if (!parent)
2127 set_dev_node(b->bridge, pcibus_to_node(b));
2128
2129 b->dev.class = &pcibus_class;
2130 b->dev.parent = b->bridge;
2131 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2132 error = device_register(&b->dev);
2133 if (error)
2134 goto class_dev_reg_err;
2135
2136 pcibios_add_bus(b);
2137
2138 /* Create legacy_io and legacy_mem files for this bus */
2139 pci_create_legacy_files(b);
2140
2141 if (parent)
2142 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2143 else
2144 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2145
2146 /* Add initial resources to the bus */
2147 resource_list_for_each_entry_safe(window, n, resources) {
2148 list_move_tail(&window->node, &bridge->windows);
2149 res = window->res;
2150 offset = window->offset;
2151 if (res->flags & IORESOURCE_BUS)
2152 pci_bus_insert_busn_res(b, bus, res->end);
2153 else
2154 pci_bus_add_resource(b, res, 0);
2155 if (offset) {
2156 if (resource_type(res) == IORESOURCE_IO)
2157 fmt = " (bus address [%#06llx-%#06llx])";
2158 else
2159 fmt = " (bus address [%#010llx-%#010llx])";
2160 snprintf(bus_addr, sizeof(bus_addr), fmt,
2161 (unsigned long long) (res->start - offset),
2162 (unsigned long long) (res->end - offset));
2163 } else
2164 bus_addr[0] = '\0';
2165 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2166 }
2167
2168 down_write(&pci_bus_sem);
2169 list_add_tail(&b->node, &pci_root_buses);
2170 up_write(&pci_bus_sem);
2171
2172 return b;
2173
2174 class_dev_reg_err:
2175 put_device(&bridge->dev);
2176 device_unregister(&bridge->dev);
2177 err_out:
2178 kfree(b);
2179 return NULL;
2180 }
2181 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2182
2183 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2184 {
2185 struct resource *res = &b->busn_res;
2186 struct resource *parent_res, *conflict;
2187
2188 res->start = bus;
2189 res->end = bus_max;
2190 res->flags = IORESOURCE_BUS;
2191
2192 if (!pci_is_root_bus(b))
2193 parent_res = &b->parent->busn_res;
2194 else {
2195 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2196 res->flags |= IORESOURCE_PCI_FIXED;
2197 }
2198
2199 conflict = request_resource_conflict(parent_res, res);
2200
2201 if (conflict)
2202 dev_printk(KERN_DEBUG, &b->dev,
2203 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2204 res, pci_is_root_bus(b) ? "domain " : "",
2205 parent_res, conflict->name, conflict);
2206
2207 return conflict == NULL;
2208 }
2209
2210 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2211 {
2212 struct resource *res = &b->busn_res;
2213 struct resource old_res = *res;
2214 resource_size_t size;
2215 int ret;
2216
2217 if (res->start > bus_max)
2218 return -EINVAL;
2219
2220 size = bus_max - res->start + 1;
2221 ret = adjust_resource(res, res->start, size);
2222 dev_printk(KERN_DEBUG, &b->dev,
2223 "busn_res: %pR end %s updated to %02x\n",
2224 &old_res, ret ? "can not be" : "is", bus_max);
2225
2226 if (!ret && !res->parent)
2227 pci_bus_insert_busn_res(b, res->start, res->end);
2228
2229 return ret;
2230 }
2231
2232 void pci_bus_release_busn_res(struct pci_bus *b)
2233 {
2234 struct resource *res = &b->busn_res;
2235 int ret;
2236
2237 if (!res->flags || !res->parent)
2238 return;
2239
2240 ret = release_resource(res);
2241 dev_printk(KERN_DEBUG, &b->dev,
2242 "busn_res: %pR %s released\n",
2243 res, ret ? "can not be" : "is");
2244 }
2245
2246 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2247 struct pci_ops *ops, void *sysdata,
2248 struct list_head *resources, struct msi_controller *msi)
2249 {
2250 struct resource_entry *window;
2251 bool found = false;
2252 struct pci_bus *b;
2253 int max;
2254
2255 resource_list_for_each_entry(window, resources)
2256 if (window->res->flags & IORESOURCE_BUS) {
2257 found = true;
2258 break;
2259 }
2260
2261 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2262 if (!b)
2263 return NULL;
2264
2265 b->msi = msi;
2266
2267 if (!found) {
2268 dev_info(&b->dev,
2269 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2270 bus);
2271 pci_bus_insert_busn_res(b, bus, 255);
2272 }
2273
2274 max = pci_scan_child_bus(b);
2275
2276 if (!found)
2277 pci_bus_update_busn_res_end(b, max);
2278
2279 return b;
2280 }
2281
2282 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2283 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2284 {
2285 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2286 NULL);
2287 }
2288 EXPORT_SYMBOL(pci_scan_root_bus);
2289
2290 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2291 void *sysdata)
2292 {
2293 LIST_HEAD(resources);
2294 struct pci_bus *b;
2295
2296 pci_add_resource(&resources, &ioport_resource);
2297 pci_add_resource(&resources, &iomem_resource);
2298 pci_add_resource(&resources, &busn_resource);
2299 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2300 if (b) {
2301 pci_scan_child_bus(b);
2302 } else {
2303 pci_free_resource_list(&resources);
2304 }
2305 return b;
2306 }
2307 EXPORT_SYMBOL(pci_scan_bus);
2308
2309 /**
2310 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2311 * @bridge: PCI bridge for the bus to scan
2312 *
2313 * Scan a PCI bus and child buses for new devices, add them,
2314 * and enable them, resizing bridge mmio/io resource if necessary
2315 * and possible. The caller must ensure the child devices are already
2316 * removed for resizing to occur.
2317 *
2318 * Returns the max number of subordinate bus discovered.
2319 */
2320 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2321 {
2322 unsigned int max;
2323 struct pci_bus *bus = bridge->subordinate;
2324
2325 max = pci_scan_child_bus(bus);
2326
2327 pci_assign_unassigned_bridge_resources(bridge);
2328
2329 pci_bus_add_devices(bus);
2330
2331 return max;
2332 }
2333
2334 /**
2335 * pci_rescan_bus - scan a PCI bus for devices.
2336 * @bus: PCI bus to scan
2337 *
2338 * Scan a PCI bus and child buses for new devices, adds them,
2339 * and enables them.
2340 *
2341 * Returns the max number of subordinate bus discovered.
2342 */
2343 unsigned int pci_rescan_bus(struct pci_bus *bus)
2344 {
2345 unsigned int max;
2346
2347 max = pci_scan_child_bus(bus);
2348 pci_assign_unassigned_bus_resources(bus);
2349 pci_bus_add_devices(bus);
2350
2351 return max;
2352 }
2353 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2354
2355 /*
2356 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2357 * routines should always be executed under this mutex.
2358 */
2359 static DEFINE_MUTEX(pci_rescan_remove_lock);
2360
2361 void pci_lock_rescan_remove(void)
2362 {
2363 mutex_lock(&pci_rescan_remove_lock);
2364 }
2365 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2366
2367 void pci_unlock_rescan_remove(void)
2368 {
2369 mutex_unlock(&pci_rescan_remove_lock);
2370 }
2371 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2372
2373 static int __init pci_sort_bf_cmp(const struct device *d_a,
2374 const struct device *d_b)
2375 {
2376 const struct pci_dev *a = to_pci_dev(d_a);
2377 const struct pci_dev *b = to_pci_dev(d_b);
2378
2379 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2380 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2381
2382 if (a->bus->number < b->bus->number) return -1;
2383 else if (a->bus->number > b->bus->number) return 1;
2384
2385 if (a->devfn < b->devfn) return -1;
2386 else if (a->devfn > b->devfn) return 1;
2387
2388 return 0;
2389 }
2390
2391 void __init pci_sort_breadthfirst(void)
2392 {
2393 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2394 }
Linux with added FPC-III support