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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / pinctrl / sirf / pinctrl-atlas7.c
blob829018c812bdda3690f7449626cecccb2de8874b
1 /*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/io.h>
13 #include <linux/bitops.h>
14 #include <linux/irq.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/gpio.h>
30
31 /* Definition of Pad&Mux Properties */
32 #define N 0
33
34 /* The Bank contains input-disable regisgers */
35 #define BANK_DS 0
36
37 /* Clear Register offset */
38 #define CLR_REG(r) ((r) + 0x04)
39
40 /* Definition of multiple function select register */
41 #define FUNC_CLEAR_MASK 0x7
42 #define FUNC_GPIO 0
43 #define FUNC_ANALOGUE 0x8
44 #define ANA_CLEAR_MASK 0x1
45
46 /* The Atlas7's Pad Type List */
47 enum altas7_pad_type {
48 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
49 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
50 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
51 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
52 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
53 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
54 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
55 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
56 };
57
58 /* Raw value of Driver-Strength Bits */
59 #define DS3 BIT(3)
60 #define DS2 BIT(2)
61 #define DS1 BIT(1)
62 #define DS0 BIT(0)
63 #define DSZ 0
64
65 /* Drive-Strength Intermediate Values */
66 #define DS_NULL -1
67 #define DS_1BIT_IM_VAL DS0
68 #define DS_1BIT_MASK 0x1
69 #define DS_2BIT_IM_VAL (DS1 | DS0)
70 #define DS_2BIT_MASK 0x3
71 #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
72 #define DS_4BIT_MASK 0xf
73
74 /* The Drive-Strength of 4WE Pad DS1 0 CO */
75 #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
76 #define DS_4WE_2 (DS1) /* 1 0 2 */
77 #define DS_4WE_1 (DS0) /* 0 1 1 */
78 #define DS_4WE_0 (DSZ) /* 0 0 0 */
79
80 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
81 #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
82 #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
83 #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
84 #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
85 #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
86 #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
87 #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
88 #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
89 #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
90 #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
91 #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
92 #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
93 #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
94 #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
95 #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
96 #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
97
98 /* The Drive-Strength of M31 Pad DS0 CO */
99 #define DS_M31_0 (DSZ) /* 0 0 */
100 #define DS_M31_1 (DS0) /* 1 1 */
101
102 /* Raw values of Pull Option Bits */
103 #define PUN BIT(1)
104 #define PD BIT(0)
105 #define PE BIT(0)
106 #define PZ 0
107
108 /* Definition of Pull Types */
109 #define PULL_UP 0
110 #define HIGH_HYSTERESIS 1
111 #define HIGH_Z 2
112 #define PULL_DOWN 3
113 #define PULL_DISABLE 4
114 #define PULL_ENABLE 5
115 #define PULL_UNKNOWN -1
116
117 /* Pull Options for 4WE Pad PUN PD CO */
118 #define P4WE_PULL_MASK 0x3
119 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
120 #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
121 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122 #define P4WE_PULL_UP (PZ) /* 0 0 0 */
123
124 /* Pull Options for 16ST Pad PUN PD CO */
125 #define P16ST_PULL_MASK 0x3
126 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
127 #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
128 #define P16ST_PULL_UP (PZ) /* 0 0 0 */
129
130 /* Pull Options for M31 Pad PE */
131 #define PM31_PULL_MASK 0x1
132 #define PM31_PULL_ENABLED (PE) /* 1 */
133 #define PM31_PULL_DISABLED (PZ) /* 0 */
134
135 /* Pull Options for A/D Pad PUN PD CO */
136 #define PANGD_PULL_MASK 0x3
137 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
138 #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
139 #define PANGD_PULL_UP (PZ) /* 0 0 0 */
140
141 /* Definition of Input Disable */
142 #define DI_MASK 0x1
143 #define DI_DISABLE 0x1
144 #define DI_ENABLE 0x0
145
146 /* Definition of Input Disable Value */
147 #define DIV_MASK 0x1
148 #define DIV_DISABLE 0x1
149 #define DIV_ENABLE 0x0
150
151 /* Number of Function input disable registers */
152 #define NUM_OF_IN_DISABLE_REG 0x2
153
154 /* Offset of Function input disable registers */
155 #define IN_DISABLE_0_REG_SET 0x0A00
156 #define IN_DISABLE_0_REG_CLR 0x0A04
157 #define IN_DISABLE_1_REG_SET 0x0A08
158 #define IN_DISABLE_1_REG_CLR 0x0A0C
159 #define IN_DISABLE_VAL_0_REG_SET 0x0A80
160 #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
161 #define IN_DISABLE_VAL_1_REG_SET 0x0A88
162 #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
163
164 struct dt_params {
165 const char *property;
166 int value;
167 };
168
169 /**
170 * struct atlas7_pad_conf - Atlas7 Pad Configuration
171 * @id The ID of this Pad.
172 * @type: The type of this Pad.
173 * @mux_reg: The mux register offset.
174 * This register contains the mux.
175 * @pupd_reg: The pull-up/down register offset.
176 * @drvstr_reg: The drive-strength register offset.
177 * @ad_ctrl_reg: The Analogue/Digital Control register.
178 *
179 * @mux_bit: The start bit of mux register.
180 * @pupd_bit: The start bit of pull-up/down register.
181 * @drvstr_bit: The start bit of drive-strength register.
182 * @ad_ctrl_bit: The start bit of analogue/digital register.
183 */
184 struct atlas7_pad_config {
185 const u32 id;
186 u32 type;
187 u32 mux_reg;
188 u32 pupd_reg;
189 u32 drvstr_reg;
190 u32 ad_ctrl_reg;
191 /* bits in register */
192 u8 mux_bit;
193 u8 pupd_bit;
194 u8 drvstr_bit;
195 u8 ad_ctrl_bit;
196 };
197
198 #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
199 { \
200 .id = pad, \
201 .type = t, \
202 .mux_reg = mr, \
203 .pupd_reg = pr, \
204 .drvstr_reg = dsr, \
205 .ad_ctrl_reg = adr, \
206 .mux_bit = mb, \
207 .pupd_bit = pb, \
208 .drvstr_bit = dsb, \
209 .ad_ctrl_bit = adb, \
210 }
211
212 /**
213 * struct atlas7_pad_status - Atlas7 Pad status
214 */
215 struct atlas7_pad_status {
216 u8 func;
217 u8 pull;
218 u8 dstr;
219 u8 reserved;
220 };
221
222 /**
223 * struct atlas7_pad_mux - Atlas7 mux
224 * @bank: The bank of this pad's registers on.
225 * @pin : The ID of this Pad.
226 * @func: The mux func on this Pad.
227 * @dinput_reg: The Input-Disable register offset.
228 * @dinput_bit: The start bit of Input-Disable register.
229 * @dinput_val_reg: The Input-Disable-value register offset.
230 * This register is used to set the value of this pad
231 * if this pad was disabled.
232 * @dinput_val_bit: The start bit of Input-Disable Value register.
233 */
234 struct atlas7_pad_mux {
235 u32 bank;
236 u32 pin;
237 u32 func;
238 u32 dinput_reg;
239 u32 dinput_bit;
240 u32 dinput_val_reg;
241 u32 dinput_val_bit;
242 };
243
244 #define MUX(b, pad, f, dr, db, dvr, dvb) \
245 { \
246 .bank = b, \
247 .pin = pad, \
248 .func = f, \
249 .dinput_reg = dr, \
250 .dinput_bit = db, \
251 .dinput_val_reg = dvr, \
252 .dinput_val_bit = dvb, \
253 }
254
255 struct atlas7_grp_mux {
256 unsigned int group;
257 unsigned int pad_mux_count;
258 const struct atlas7_pad_mux *pad_mux_list;
259 };
260
261 /**
262 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
263 * @name: the name of this specific pin group
264 * @pins: an array of discrete physical pins used in this group, taken
265 * from the driver-local pin enumeration space
266 * @num_pins: the number of pins in this group array, i.e. the number of
267 * elements in .pins so we can iterate over that array
268 */
269 struct atlas7_pin_group {
270 const char *name;
271 const unsigned int *pins;
272 const unsigned num_pins;
273 };
274
275 #define GROUP(n, p) \
276 { \
277 .name = n, \
278 .pins = p, \
279 .num_pins = ARRAY_SIZE(p), \
280 }
281
282 struct atlas7_pmx_func {
283 const char *name;
284 const char * const *groups;
285 const unsigned num_groups;
286 const struct atlas7_grp_mux *grpmux;
287 };
288
289 #define FUNCTION(n, g, m) \
290 { \
291 .name = n, \
292 .groups = g, \
293 .num_groups = ARRAY_SIZE(g), \
294 .grpmux = m, \
295 }
296
297 struct atlas7_pinctrl_data {
298 struct pinctrl_pin_desc *pads;
299 int pads_cnt;
300 struct atlas7_pin_group *grps;
301 int grps_cnt;
302 struct atlas7_pmx_func *funcs;
303 int funcs_cnt;
304 struct atlas7_pad_config *confs;
305 int confs_cnt;
306 };
307
308 /* Platform info of atlas7 pinctrl */
309 #define ATLAS7_PINCTRL_REG_BANKS 2
310 #define ATLAS7_PINCTRL_BANK_0_PINS 18
311 #define ATLAS7_PINCTRL_BANK_1_PINS 141
312 #define ATLAS7_PINCTRL_TOTAL_PINS \
313 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
314
315 /**
316 * Atlas7 GPIO Chip
317 */
318
319 #define NGPIO_OF_BANK 32
320 #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
321
322 /* Registers of GPIO Controllers */
323 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
324 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
325 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
326
327 /* Definition bits of GPIO Control Registers */
328 #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
329 #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
330 #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
331 #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
332 #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
333 #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
334 #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
335 #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
336
337 struct atlas7_gpio_bank {
338 struct pinctrl_dev *pctldev;
339 int id;
340 int irq;
341 void __iomem *base;
342 unsigned int gpio_offset;
343 unsigned int ngpio;
344 const unsigned int *gpio_pins;
345 u32 sleep_data[NGPIO_OF_BANK];
346 };
347
348 struct atlas7_gpio_chip {
349 const char *name;
350 void __iomem *reg;
351 struct clk *clk;
352 int nbank;
353 spinlock_t lock;
354 struct gpio_chip chip;
355 struct atlas7_gpio_bank banks[0];
356 };
357
358 static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc)
359 {
360 return container_of(gc, struct atlas7_gpio_chip, chip);
361 }
362
363 /**
364 * @dev: a pointer back to containing device
365 * @virtbase: the offset to the controller in virtual memory
366 */
367 struct atlas7_pmx {
368 struct device *dev;
369 struct pinctrl_dev *pctl;
370 struct pinctrl_desc pctl_desc;
371 struct atlas7_pinctrl_data *pctl_data;
372 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
373 u32 status_ds[NUM_OF_IN_DISABLE_REG];
374 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
375 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
376 };
377
378 /*
379 * Pad list for the pinmux subsystem
380 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
381 */
382
383 /*Pads in IOC RTC & TOP */
384 static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
385 /* RTC PADs */
386 PINCTRL_PIN(0, "rtc_gpio_0"),
387 PINCTRL_PIN(1, "rtc_gpio_1"),
388 PINCTRL_PIN(2, "rtc_gpio_2"),
389 PINCTRL_PIN(3, "rtc_gpio_3"),
390 PINCTRL_PIN(4, "low_bat_ind_b"),
391 PINCTRL_PIN(5, "on_key_b"),
392 PINCTRL_PIN(6, "ext_on"),
393 PINCTRL_PIN(7, "mem_on"),
394 PINCTRL_PIN(8, "core_on"),
395 PINCTRL_PIN(9, "io_on"),
396 PINCTRL_PIN(10, "can0_tx"),
397 PINCTRL_PIN(11, "can0_rx"),
398 PINCTRL_PIN(12, "spi0_clk"),
399 PINCTRL_PIN(13, "spi0_cs_b"),
400 PINCTRL_PIN(14, "spi0_io_0"),
401 PINCTRL_PIN(15, "spi0_io_1"),
402 PINCTRL_PIN(16, "spi0_io_2"),
403 PINCTRL_PIN(17, "spi0_io_3"),
404
405 /* TOP PADs */
406 PINCTRL_PIN(18, "spi1_en"),
407 PINCTRL_PIN(19, "spi1_clk"),
408 PINCTRL_PIN(20, "spi1_din"),
409 PINCTRL_PIN(21, "spi1_dout"),
410 PINCTRL_PIN(22, "trg_spi_clk"),
411 PINCTRL_PIN(23, "trg_spi_di"),
412 PINCTRL_PIN(24, "trg_spi_do"),
413 PINCTRL_PIN(25, "trg_spi_cs_b"),
414 PINCTRL_PIN(26, "trg_acq_d1"),
415 PINCTRL_PIN(27, "trg_irq_b"),
416 PINCTRL_PIN(28, "trg_acq_d0"),
417 PINCTRL_PIN(29, "trg_acq_clk"),
418 PINCTRL_PIN(30, "trg_shutdown_b_out"),
419 PINCTRL_PIN(31, "sdio2_clk"),
420 PINCTRL_PIN(32, "sdio2_cmd"),
421 PINCTRL_PIN(33, "sdio2_dat_0"),
422 PINCTRL_PIN(34, "sdio2_dat_1"),
423 PINCTRL_PIN(35, "sdio2_dat_2"),
424 PINCTRL_PIN(36, "sdio2_dat_3"),
425 PINCTRL_PIN(37, "df_ad_7"),
426 PINCTRL_PIN(38, "df_ad_6"),
427 PINCTRL_PIN(39, "df_ad_5"),
428 PINCTRL_PIN(40, "df_ad_4"),
429 PINCTRL_PIN(41, "df_ad_3"),
430 PINCTRL_PIN(42, "df_ad_2"),
431 PINCTRL_PIN(43, "df_ad_1"),
432 PINCTRL_PIN(44, "df_ad_0"),
433 PINCTRL_PIN(45, "df_dqs"),
434 PINCTRL_PIN(46, "df_cle"),
435 PINCTRL_PIN(47, "df_ale"),
436 PINCTRL_PIN(48, "df_we_b"),
437 PINCTRL_PIN(49, "df_re_b"),
438 PINCTRL_PIN(50, "df_ry_by"),
439 PINCTRL_PIN(51, "df_cs_b_1"),
440 PINCTRL_PIN(52, "df_cs_b_0"),
441 PINCTRL_PIN(53, "l_pclk"),
442 PINCTRL_PIN(54, "l_lck"),
443 PINCTRL_PIN(55, "l_fck"),
444 PINCTRL_PIN(56, "l_de"),
445 PINCTRL_PIN(57, "ldd_0"),
446 PINCTRL_PIN(58, "ldd_1"),
447 PINCTRL_PIN(59, "ldd_2"),
448 PINCTRL_PIN(60, "ldd_3"),
449 PINCTRL_PIN(61, "ldd_4"),
450 PINCTRL_PIN(62, "ldd_5"),
451 PINCTRL_PIN(63, "ldd_6"),
452 PINCTRL_PIN(64, "ldd_7"),
453 PINCTRL_PIN(65, "ldd_8"),
454 PINCTRL_PIN(66, "ldd_9"),
455 PINCTRL_PIN(67, "ldd_10"),
456 PINCTRL_PIN(68, "ldd_11"),
457 PINCTRL_PIN(69, "ldd_12"),
458 PINCTRL_PIN(70, "ldd_13"),
459 PINCTRL_PIN(71, "ldd_14"),
460 PINCTRL_PIN(72, "ldd_15"),
461 PINCTRL_PIN(73, "lcd_gpio_20"),
462 PINCTRL_PIN(74, "vip_0"),
463 PINCTRL_PIN(75, "vip_1"),
464 PINCTRL_PIN(76, "vip_2"),
465 PINCTRL_PIN(77, "vip_3"),
466 PINCTRL_PIN(78, "vip_4"),
467 PINCTRL_PIN(79, "vip_5"),
468 PINCTRL_PIN(80, "vip_6"),
469 PINCTRL_PIN(81, "vip_7"),
470 PINCTRL_PIN(82, "vip_pxclk"),
471 PINCTRL_PIN(83, "vip_hsync"),
472 PINCTRL_PIN(84, "vip_vsync"),
473 PINCTRL_PIN(85, "sdio3_clk"),
474 PINCTRL_PIN(86, "sdio3_cmd"),
475 PINCTRL_PIN(87, "sdio3_dat_0"),
476 PINCTRL_PIN(88, "sdio3_dat_1"),
477 PINCTRL_PIN(89, "sdio3_dat_2"),
478 PINCTRL_PIN(90, "sdio3_dat_3"),
479 PINCTRL_PIN(91, "sdio5_clk"),
480 PINCTRL_PIN(92, "sdio5_cmd"),
481 PINCTRL_PIN(93, "sdio5_dat_0"),
482 PINCTRL_PIN(94, "sdio5_dat_1"),
483 PINCTRL_PIN(95, "sdio5_dat_2"),
484 PINCTRL_PIN(96, "sdio5_dat_3"),
485 PINCTRL_PIN(97, "rgmii_txd_0"),
486 PINCTRL_PIN(98, "rgmii_txd_1"),
487 PINCTRL_PIN(99, "rgmii_txd_2"),
488 PINCTRL_PIN(100, "rgmii_txd_3"),
489 PINCTRL_PIN(101, "rgmii_txclk"),
490 PINCTRL_PIN(102, "rgmii_tx_ctl"),
491 PINCTRL_PIN(103, "rgmii_rxd_0"),
492 PINCTRL_PIN(104, "rgmii_rxd_1"),
493 PINCTRL_PIN(105, "rgmii_rxd_2"),
494 PINCTRL_PIN(106, "rgmii_rxd_3"),
495 PINCTRL_PIN(107, "rgmii_rx_clk"),
496 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
497 PINCTRL_PIN(109, "rgmii_mdio"),
498 PINCTRL_PIN(110, "rgmii_mdc"),
499 PINCTRL_PIN(111, "rgmii_intr_n"),
500 PINCTRL_PIN(112, "i2s_mclk"),
501 PINCTRL_PIN(113, "i2s_bclk"),
502 PINCTRL_PIN(114, "i2s_ws"),
503 PINCTRL_PIN(115, "i2s_dout0"),
504 PINCTRL_PIN(116, "i2s_dout1"),
505 PINCTRL_PIN(117, "i2s_dout2"),
506 PINCTRL_PIN(118, "i2s_din"),
507 PINCTRL_PIN(119, "gpio_0"),
508 PINCTRL_PIN(120, "gpio_1"),
509 PINCTRL_PIN(121, "gpio_2"),
510 PINCTRL_PIN(122, "gpio_3"),
511 PINCTRL_PIN(123, "gpio_4"),
512 PINCTRL_PIN(124, "gpio_5"),
513 PINCTRL_PIN(125, "gpio_6"),
514 PINCTRL_PIN(126, "gpio_7"),
515 PINCTRL_PIN(127, "sda_0"),
516 PINCTRL_PIN(128, "scl_0"),
517 PINCTRL_PIN(129, "coex_pio_0"),
518 PINCTRL_PIN(130, "coex_pio_1"),
519 PINCTRL_PIN(131, "coex_pio_2"),
520 PINCTRL_PIN(132, "coex_pio_3"),
521 PINCTRL_PIN(133, "uart0_tx"),
522 PINCTRL_PIN(134, "uart0_rx"),
523 PINCTRL_PIN(135, "uart1_tx"),
524 PINCTRL_PIN(136, "uart1_rx"),
525 PINCTRL_PIN(137, "uart3_tx"),
526 PINCTRL_PIN(138, "uart3_rx"),
527 PINCTRL_PIN(139, "uart4_tx"),
528 PINCTRL_PIN(140, "uart4_rx"),
529 PINCTRL_PIN(141, "usp0_clk"),
530 PINCTRL_PIN(142, "usp0_tx"),
531 PINCTRL_PIN(143, "usp0_rx"),
532 PINCTRL_PIN(144, "usp0_fs"),
533 PINCTRL_PIN(145, "usp1_clk"),
534 PINCTRL_PIN(146, "usp1_tx"),
535 PINCTRL_PIN(147, "usp1_rx"),
536 PINCTRL_PIN(148, "usp1_fs"),
537 PINCTRL_PIN(149, "lvds_tx0d4p"),
538 PINCTRL_PIN(150, "lvds_tx0d4n"),
539 PINCTRL_PIN(151, "lvds_tx0d3p"),
540 PINCTRL_PIN(152, "lvds_tx0d3n"),
541 PINCTRL_PIN(153, "lvds_tx0d2p"),
542 PINCTRL_PIN(154, "lvds_tx0d2n"),
543 PINCTRL_PIN(155, "lvds_tx0d1p"),
544 PINCTRL_PIN(156, "lvds_tx0d1n"),
545 PINCTRL_PIN(157, "lvds_tx0d0p"),
546 PINCTRL_PIN(158, "lvds_tx0d0n"),
547 PINCTRL_PIN(159, "jtag_tdo"),
548 PINCTRL_PIN(160, "jtag_tms"),
549 PINCTRL_PIN(161, "jtag_tck"),
550 PINCTRL_PIN(162, "jtag_tdi"),
551 PINCTRL_PIN(163, "jtag_trstn"),
552 };
553
554 struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
555 /* The Configuration of IOC_RTC Pads */
556 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
557 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
558 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
559 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
560 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
561 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
562 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
563 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
564 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
565 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
566 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
567 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
568 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
569 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
570 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
571 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
572 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
573 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
574 /* The Configuration of IOC_TOP Pads */
575 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
576 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
577 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
578 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
579 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
580 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
581 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
582 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
583 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
584 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
585 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
586 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
587 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
588 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
589 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
590 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
591 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
592 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
593 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
594 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
595 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
596 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
597 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
598 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
599 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
600 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
601 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
602 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
603 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
604 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
605 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
606 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
607 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
608 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
609 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
610 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
611 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
612 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
613 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
614 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
615 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
616 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
617 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
618 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
619 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
620 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
621 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
622 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
623 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
624 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
625 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
626 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
627 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
628 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
629 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
630 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
631 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
632 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
633 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
634 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
635 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
636 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
637 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
638 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
639 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
640 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
641 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
642 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
643 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
644 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
645 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
646 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
647 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
648 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
649 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
650 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
651 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
652 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
653 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
654 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
655 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
656 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
657 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
658 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
659 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
660 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
661 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
662 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
663 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
664 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
665 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
666 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
667 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
668 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
669 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
670 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
671 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
672 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
673 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
674 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
675 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
676 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
677 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
678 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
679 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
680 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
681 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
682 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
683 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
684 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
685 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
686 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
687 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
688 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
689 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
690 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
691 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
692 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
693 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
694 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
695 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
696 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
697 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
698 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
699 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
700 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
701 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
702 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
703 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
704 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
705 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
706 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
707 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
708 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
709 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
710 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
711 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
712 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
713 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
714 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
715 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
716 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
717 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
718 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
719 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
720 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
721 };
722
723 /* pin list of each pin group */
724 static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
725 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
726 static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
727 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
728 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
729 static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
730 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
731 95, 96, 112, 113, 114, 115, 116, 117, 118, };
732 static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
733 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
734 141, 142, 143, 144, 145, 146, 147, 148, };
735 static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
736 151, 152, 149, 150, };
737 static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
738 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
739 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
740 static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
741 14, 15, 16, 17, 9, };
742 static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
743 static const unsigned int audio_digmic_pins0[] = { 51, };
744 static const unsigned int audio_digmic_pins1[] = { 122, };
745 static const unsigned int audio_digmic_pins2[] = { 161, };
746 static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
747 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
748 115, 49, 50, 142, 143, 80, };
749 static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
750 114, };
751 static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
752 static const unsigned int audio_i2s_extclk_pins[] = { 112, };
753 static const unsigned int audio_spdif_out_pins0[] = { 112, };
754 static const unsigned int audio_spdif_out_pins1[] = { 116, };
755 static const unsigned int audio_spdif_out_pins2[] = { 142, };
756 static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
757 static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
758 static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
759 static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
760 static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
761 static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
762 static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
763 static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
764 static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
765 static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
766 static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
767 static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
768 static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
769 static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
770 static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
771 static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
772 static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
773 static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
774 static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
775 static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
776 static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
777 static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
778 static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
779 static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
780 static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
781 static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
782 static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
783 static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
784 static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
785 static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
786 static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
787 static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
788 static const unsigned int c1_can_rxd_pins0[] = { 138, };
789 static const unsigned int c1_can_rxd_pins1[] = { 147, };
790 static const unsigned int c1_can_rxd_pins2[] = { 2, };
791 static const unsigned int c1_can_rxd_pins3[] = { 162, };
792 static const unsigned int c1_can_txd_pins0[] = { 137, };
793 static const unsigned int c1_can_txd_pins1[] = { 146, };
794 static const unsigned int c1_can_txd_pins2[] = { 3, };
795 static const unsigned int c1_can_txd_pins3[] = { 161, };
796 static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
797 69, 70, 71, };
798 static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
799 static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
800 static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
801 static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
802 static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
803 49, 50, 54, 55, 56, };
804 static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
805 static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
806 static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
807 76, 77, };
808 static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
809 static const unsigned int clkc_pins0[] = { 30, 47, };
810 static const unsigned int clkc_pins1[] = { 78, 54, };
811 static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
812 static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
813 static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
814 static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
815 static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
816 static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
817 79, 80, 81, 83, 84, 73, 55, 56, };
818 static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
819 static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
820 static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
821 static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
822 static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
823 static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
824 static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
825 static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
826 static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
827 static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
828 static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
829 static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
830 static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
831 static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
832 static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
833 static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
834 static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
835 120, };
836 static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
837 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
838 static const unsigned int gn_gnss_eclk_pins[] = { 113, };
839 static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
840 static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
841 static const unsigned int gn_gnss_tm_pins[] = { 115, };
842 static const unsigned int gn_gnss_tsync_pins[] = { 114, };
843 static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
844 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
845 static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
846 static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
847 static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
848 static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
849 static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
850 static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
851 static const unsigned int i2c0_pins[] = { 128, 127, };
852 static const unsigned int i2c1_pins[] = { 126, 125, };
853 static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
854 static const unsigned int i2s1_basic_pins[] = { 95, 96, };
855 static const unsigned int i2s1_rxd0_pins0[] = { 61, };
856 static const unsigned int i2s1_rxd0_pins1[] = { 131, };
857 static const unsigned int i2s1_rxd0_pins2[] = { 129, };
858 static const unsigned int i2s1_rxd0_pins3[] = { 117, };
859 static const unsigned int i2s1_rxd0_pins4[] = { 83, };
860 static const unsigned int i2s1_rxd1_pins0[] = { 72, };
861 static const unsigned int i2s1_rxd1_pins1[] = { 132, };
862 static const unsigned int i2s1_rxd1_pins2[] = { 130, };
863 static const unsigned int i2s1_rxd1_pins3[] = { 118, };
864 static const unsigned int i2s1_rxd1_pins4[] = { 84, };
865 static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
866 static const unsigned int jtag_ntrst_pins0[] = { 4, };
867 static const unsigned int jtag_ntrst_pins1[] = { 163, };
868 static const unsigned int jtag_swdiotms_pins0[] = { 2, };
869 static const unsigned int jtag_swdiotms_pins1[] = { 160, };
870 static const unsigned int jtag_tck_pins0[] = { 0, };
871 static const unsigned int jtag_tck_pins1[] = { 161, };
872 static const unsigned int jtag_tdi_pins0[] = { 1, };
873 static const unsigned int jtag_tdi_pins1[] = { 162, };
874 static const unsigned int jtag_tdo_pins0[] = { 3, };
875 static const unsigned int jtag_tdo_pins1[] = { 159, };
876 static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
877 static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
878 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
879 81, 56, 53, };
880 static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
881 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
882 static const unsigned int ld_ldd_fck_pins[] = { 55, };
883 static const unsigned int ld_ldd_lck_pins[] = { 54, };
884 static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
885 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
886 static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
887 155, 156, 157, 158, };
888 static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37,
889 47, 46, 52, 51, 45, 49, 50, 48, 124, };
890 static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38,
891 37, 47, 46, 52, 51, 45, 49, 50, 48, };
892 static const unsigned int ps_pins[] = { 120, 119, 121, };
893 static const unsigned int pwc_core_on_pins[] = { 8, };
894 static const unsigned int pwc_ext_on_pins[] = { 6, };
895 static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
896 static const unsigned int pwc_io_on_pins[] = { 9, };
897 static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
898 static const unsigned int pwc_mem_on_pins[] = { 7, };
899 static const unsigned int pwc_on_key_b_pins0[] = { 5, };
900 static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
901 static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
902 static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
903 static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
904 static const unsigned int pw_cko0_pins0[] = { 123, };
905 static const unsigned int pw_cko0_pins1[] = { 101, };
906 static const unsigned int pw_cko0_pins2[] = { 82, };
907 static const unsigned int pw_cko0_pins3[] = { 162, };
908 static const unsigned int pw_cko1_pins0[] = { 124, };
909 static const unsigned int pw_cko1_pins1[] = { 110, };
910 static const unsigned int pw_cko1_pins2[] = { 163, };
911 static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
912 static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
913 static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
914 static const unsigned int pw_pwm0_pins0[] = { 119, };
915 static const unsigned int pw_pwm0_pins1[] = { 159, };
916 static const unsigned int pw_pwm1_pins0[] = { 120, };
917 static const unsigned int pw_pwm1_pins1[] = { 160, };
918 static const unsigned int pw_pwm1_pins2[] = { 131, };
919 static const unsigned int pw_pwm2_pins0[] = { 121, };
920 static const unsigned int pw_pwm2_pins1[] = { 98, };
921 static const unsigned int pw_pwm2_pins2[] = { 161, };
922 static const unsigned int pw_pwm3_pins0[] = { 122, };
923 static const unsigned int pw_pwm3_pins1[] = { 73, };
924 static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
925 static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
926 static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
927 static const unsigned int pw_backlight_pins0[] = { 122, };
928 static const unsigned int pw_backlight_pins1[] = { 73, };
929 static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
930 102, 97, 98, 99, 100, 101, };
931 static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
932 static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
933 static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
934 static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
935 static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
936 37, };
937 static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
938 static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
939 37, };
940 static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
941 static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
942 static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
943 static const unsigned int sd2_cdb_pins0[] = { 124, };
944 static const unsigned int sd2_cdb_pins1[] = { 161, };
945 static const unsigned int sd2_wpb_pins0[] = { 123, };
946 static const unsigned int sd2_wpb_pins1[] = { 163, };
947 static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, };
948 static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
949 static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
950 static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
951 static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
952 static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
953 static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
954 static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
955 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
956 static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
957 static const unsigned int uart0_nopause_pins[] = { 134, 133, };
958 static const unsigned int uart1_pins[] = { 136, 135, };
959 static const unsigned int uart2_cts_pins0[] = { 132, };
960 static const unsigned int uart2_cts_pins1[] = { 162, };
961 static const unsigned int uart2_rts_pins0[] = { 131, };
962 static const unsigned int uart2_rts_pins1[] = { 161, };
963 static const unsigned int uart2_rxd_pins0[] = { 11, };
964 static const unsigned int uart2_rxd_pins1[] = { 160, };
965 static const unsigned int uart2_rxd_pins2[] = { 130, };
966 static const unsigned int uart2_txd_pins0[] = { 10, };
967 static const unsigned int uart2_txd_pins1[] = { 159, };
968 static const unsigned int uart2_txd_pins2[] = { 129, };
969 static const unsigned int uart3_cts_pins0[] = { 125, };
970 static const unsigned int uart3_cts_pins1[] = { 111, };
971 static const unsigned int uart3_cts_pins2[] = { 140, };
972 static const unsigned int uart3_rts_pins0[] = { 126, };
973 static const unsigned int uart3_rts_pins1[] = { 109, };
974 static const unsigned int uart3_rts_pins2[] = { 139, };
975 static const unsigned int uart3_rxd_pins0[] = { 138, };
976 static const unsigned int uart3_rxd_pins1[] = { 84, };
977 static const unsigned int uart3_rxd_pins2[] = { 162, };
978 static const unsigned int uart3_txd_pins0[] = { 137, };
979 static const unsigned int uart3_txd_pins1[] = { 83, };
980 static const unsigned int uart3_txd_pins2[] = { 161, };
981 static const unsigned int uart4_basic_pins[] = { 140, 139, };
982 static const unsigned int uart4_cts_pins0[] = { 122, };
983 static const unsigned int uart4_cts_pins1[] = { 100, };
984 static const unsigned int uart4_cts_pins2[] = { 117, };
985 static const unsigned int uart4_rts_pins0[] = { 123, };
986 static const unsigned int uart4_rts_pins1[] = { 99, };
987 static const unsigned int uart4_rts_pins2[] = { 116, };
988 static const unsigned int usb0_drvvbus_pins0[] = { 51, };
989 static const unsigned int usb0_drvvbus_pins1[] = { 162, };
990 static const unsigned int usb1_drvvbus_pins0[] = { 134, };
991 static const unsigned int usb1_drvvbus_pins1[] = { 163, };
992 static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
993 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
994 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
995 static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
996 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
997 static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
998 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
999 99, 100, };
1000 static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
1001 80, 81, };
1002 static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103,
1003 104, 105, 106, };
1004
1005 /* definition of pin group table */
1006 struct atlas7_pin_group altas7_pin_groups[] = {
1007 GROUP("gnss_gpio_grp", gnss_gpio_pins),
1008 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
1009 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
1010 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
1011 GROUP("lvds_gpio_grp", lvds_gpio_pins),
1012 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
1013 GROUP("rtc_gpio_grp", rtc_gpio_pins),
1014 GROUP("audio_ac97_grp", audio_ac97_pins),
1015 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1016 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1017 GROUP("audio_digmic_grp2", audio_digmic_pins2),
1018 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
1019 GROUP("audio_i2s_grp", audio_i2s_pins),
1020 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
1021 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
1022 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
1023 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
1024 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
1025 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
1026 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
1027 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
1028 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
1029 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
1030 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
1031 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1032 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1033 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1034 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1035 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1036 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1037 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1038 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1039 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1040 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1041 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1042 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1043 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1044 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1045 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1046 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1047 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1048 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1049 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1050 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1051 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1052 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1053 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1054 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1055 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1056 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1057 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1058 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1059 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1060 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1061 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1062 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1063 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1064 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
1065 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
1066 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
1067 GROUP("ca_coex_grp", ca_coex_pins),
1068 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
1069 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
1070 GROUP("ca_pio_grp", ca_pio_pins),
1071 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
1072 GROUP("ca_spi_grp", ca_spi_pins),
1073 GROUP("ca_trb_grp", ca_trb_pins),
1074 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
1075 GROUP("clkc_grp0", clkc_pins0),
1076 GROUP("clkc_grp1", clkc_pins1),
1077 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
1078 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
1079 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
1080 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
1081 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
1082 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
1083 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
1084 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
1085 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
1086 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
1087 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
1088 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
1089 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
1090 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
1091 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
1092 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
1093 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
1094 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
1095 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
1096 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
1097 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
1098 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
1099 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
1100 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
1101 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
1102 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
1103 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
1104 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
1105 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
1106 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
1107 GROUP("gn_trg_grp0", gn_trg_pins0),
1108 GROUP("gn_trg_grp1", gn_trg_pins1),
1109 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
1110 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
1111 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
1112 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
1113 GROUP("i2c0_grp", i2c0_pins),
1114 GROUP("i2c1_grp", i2c1_pins),
1115 GROUP("i2s0_grp", i2s0_pins),
1116 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1117 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1118 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1119 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1120 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1121 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1122 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1123 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1124 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1125 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1126 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1127 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1128 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1129 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1130 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1131 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1132 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1133 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1134 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1135 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1136 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1137 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
1138 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
1139 GROUP("ld_ldd_grp", ld_ldd_pins),
1140 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
1141 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
1142 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
1143 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
1144 GROUP("lvds_analog_grp", lvds_analog_pins),
1145 GROUP("nd_df_grp", nd_df_pins),
1146 GROUP("nd_df_nowp_grp", nd_df_nowp_pins),
1147 GROUP("ps_grp", ps_pins),
1148 GROUP("pwc_core_on_grp", pwc_core_on_pins),
1149 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
1150 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
1151 GROUP("pwc_io_on_grp", pwc_io_on_pins),
1152 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
1153 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
1154 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
1155 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
1156 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
1157 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
1158 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
1159 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1160 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1161 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1162 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1163 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1164 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1165 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1166 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1167 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1168 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1169 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1170 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1171 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1172 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1173 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1174 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1175 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1176 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1177 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1178 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1179 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1180 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1181 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1182 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1183 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1184 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
1185 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
1186 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
1187 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
1188 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
1189 GROUP("sd0_grp", sd0_pins),
1190 GROUP("sd0_4bit_grp", sd0_4bit_pins),
1191 GROUP("sd1_grp", sd1_pins),
1192 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1193 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1194 GROUP("sd2_basic_grp", sd2_basic_pins),
1195 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1196 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1197 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1198 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1199 GROUP("sd3_grp", sd3_pins),
1200 GROUP("sd5_grp", sd5_pins),
1201 GROUP("sd6_grp0", sd6_pins0),
1202 GROUP("sd6_grp1", sd6_pins1),
1203 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1204 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1205 GROUP("sp1_spi_grp", sp1_spi_pins),
1206 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1207 GROUP("uart0_grp", uart0_pins),
1208 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1209 GROUP("uart1_grp", uart1_pins),
1210 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1211 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1212 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1213 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1214 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1215 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1216 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1217 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1218 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1219 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1220 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1221 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1222 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1223 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1224 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1225 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1226 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1227 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1228 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1229 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1230 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1231 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1232 GROUP("uart4_basic_grp", uart4_basic_pins),
1233 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1234 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1235 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1236 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1237 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1238 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1239 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1240 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1241 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1242 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1243 GROUP("visbus_dout_grp", visbus_dout_pins),
1244 GROUP("vi_vip1_grp", vi_vip1_pins),
1245 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1246 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1247 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1248 };
1249
1250 /* How many groups that a function can use */
1251 static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1252 static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1253 static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1254 static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1255 static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1256 static const char * const jtag_uart_nand_gpio_grp[] = {
1257 "jtag_uart_nand_gpio_grp", };
1258 static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1259 static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1260 static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1261 static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1262 static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1263 static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1264 static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1265 static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1266 static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1267 static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1268 static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1269 static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1270 static const char * const audio_uart0_basic_grp[] = {
1271 "audio_uart0_basic_grp", };
1272 static const char * const audio_uart0_urfs_grp0[] = {
1273 "audio_uart0_urfs_grp0", };
1274 static const char * const audio_uart0_urfs_grp1[] = {
1275 "audio_uart0_urfs_grp1", };
1276 static const char * const audio_uart0_urfs_grp2[] = {
1277 "audio_uart0_urfs_grp2", };
1278 static const char * const audio_uart0_urfs_grp3[] = {
1279 "audio_uart0_urfs_grp3", };
1280 static const char * const audio_uart1_basic_grp[] = {
1281 "audio_uart1_basic_grp", };
1282 static const char * const audio_uart1_urfs_grp0[] = {
1283 "audio_uart1_urfs_grp0", };
1284 static const char * const audio_uart1_urfs_grp1[] = {
1285 "audio_uart1_urfs_grp1", };
1286 static const char * const audio_uart1_urfs_grp2[] = {
1287 "audio_uart1_urfs_grp2", };
1288 static const char * const audio_uart2_urfs_grp0[] = {
1289 "audio_uart2_urfs_grp0", };
1290 static const char * const audio_uart2_urfs_grp1[] = {
1291 "audio_uart2_urfs_grp1", };
1292 static const char * const audio_uart2_urfs_grp2[] = {
1293 "audio_uart2_urfs_grp2", };
1294 static const char * const audio_uart2_urxd_grp0[] = {
1295 "audio_uart2_urxd_grp0", };
1296 static const char * const audio_uart2_urxd_grp1[] = {
1297 "audio_uart2_urxd_grp1", };
1298 static const char * const audio_uart2_urxd_grp2[] = {
1299 "audio_uart2_urxd_grp2", };
1300 static const char * const audio_uart2_usclk_grp0[] = {
1301 "audio_uart2_usclk_grp0", };
1302 static const char * const audio_uart2_usclk_grp1[] = {
1303 "audio_uart2_usclk_grp1", };
1304 static const char * const audio_uart2_usclk_grp2[] = {
1305 "audio_uart2_usclk_grp2", };
1306 static const char * const audio_uart2_utfs_grp0[] = {
1307 "audio_uart2_utfs_grp0", };
1308 static const char * const audio_uart2_utfs_grp1[] = {
1309 "audio_uart2_utfs_grp1", };
1310 static const char * const audio_uart2_utfs_grp2[] = {
1311 "audio_uart2_utfs_grp2", };
1312 static const char * const audio_uart2_utxd_grp0[] = {
1313 "audio_uart2_utxd_grp0", };
1314 static const char * const audio_uart2_utxd_grp1[] = {
1315 "audio_uart2_utxd_grp1", };
1316 static const char * const audio_uart2_utxd_grp2[] = {
1317 "audio_uart2_utxd_grp2", };
1318 static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1319 static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1320 static const char * const c_can_trnsvr_intr_grp[] = {
1321 "c_can_trnsvr_intr_grp", };
1322 static const char * const c_can_trnsvr_stb_n_grp[] = {
1323 "c_can_trnsvr_stb_n_grp", };
1324 static const char * const c0_can_rxd_trnsv0_grp[] = {
1325 "c0_can_rxd_trnsv0_grp", };
1326 static const char * const c0_can_rxd_trnsv1_grp[] = {
1327 "c0_can_rxd_trnsv1_grp", };
1328 static const char * const c0_can_txd_trnsv0_grp[] = {
1329 "c0_can_txd_trnsv0_grp", };
1330 static const char * const c0_can_txd_trnsv1_grp[] = {
1331 "c0_can_txd_trnsv1_grp", };
1332 static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1333 static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1334 static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1335 static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1336 static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1337 static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1338 static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1339 static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1340 static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1341 static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1342 static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1343 static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1344 static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1345 static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1346 static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1347 static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1348 static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1349 static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1350 static const char * const clkc_grp0[] = { "clkc_grp0", };
1351 static const char * const clkc_grp1[] = { "clkc_grp1", };
1352 static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1353 static const char * const gn_gnss_uart_nopause_grp[] = {
1354 "gn_gnss_uart_nopause_grp", };
1355 static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1356 static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1357 static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1358 static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1359 static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1360 static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1361 static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1362 static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1363 static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1364 static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1365 static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1366 static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1367 static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1368 static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1369 static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1370 static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1371 static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1372 static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1373 static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1374 static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1375 static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1376 static const char * const gn_gnss_sw_status_grp[] = {
1377 "gn_gnss_sw_status_grp", };
1378 static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1379 static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1380 static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1381 static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1382 static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1383 static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1384 "gn_io_gnsssys_sw_cfg_grp", };
1385 static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1386 static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1387 static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1388 static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1389 static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1390 static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1391 static const char * const i2c0_grp[] = { "i2c0_grp", };
1392 static const char * const i2c1_grp[] = { "i2c1_grp", };
1393 static const char * const i2s0_grp[] = { "i2s0_grp", };
1394 static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1395 static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1396 static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1397 static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1398 static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1399 static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1400 static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1401 static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1402 static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1403 static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1404 static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1405 static const char * const jtag_jt_dbg_nsrst_grp[] = {
1406 "jtag_jt_dbg_nsrst_grp", };
1407 static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1408 static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1409 static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1410 static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1411 static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1412 static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1413 static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1414 static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1415 static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1416 static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1417 static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1418 static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1419 static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1420 static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1421 static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1422 static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1423 static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1424 static const char * const nd_df_grp[] = { "nd_df_grp", };
1425 static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", };
1426 static const char * const ps_grp[] = { "ps_grp", };
1427 static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1428 static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1429 static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1430 static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1431 static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1432 static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1433 static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1434 static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1435 static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1436 static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1437 static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1438 static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1439 static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1440 static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1441 static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1442 static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1443 static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1444 static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1445 static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1446 static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1447 static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1448 static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1449 static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1450 static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1451 static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1452 static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1453 static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1454 static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1455 static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1456 static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1457 static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1458 static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1459 static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1460 static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1461 static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1462 static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1463 static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1464 static const char * const rg_gmac_phy_intr_n_grp[] = {
1465 "rg_gmac_phy_intr_n_grp", };
1466 static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1467 static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1468 "rg_rgmii_phy_ref_clk_grp0", };
1469 static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1470 "rg_rgmii_phy_ref_clk_grp1", };
1471 static const char * const sd0_grp[] = { "sd0_grp", };
1472 static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1473 static const char * const sd1_grp[] = { "sd1_grp", };
1474 static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1475 static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1476 static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1477 static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1478 static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1479 static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1480 static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1481 static const char * const sd3_grp[] = { "sd3_grp", };
1482 static const char * const sd5_grp[] = { "sd5_grp", };
1483 static const char * const sd6_grp0[] = { "sd6_grp0", };
1484 static const char * const sd6_grp1[] = { "sd6_grp1", };
1485 static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1486 static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1487 static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1488 static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1489 static const char * const uart0_grp[] = { "uart0_grp", };
1490 static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1491 static const char * const uart1_grp[] = { "uart1_grp", };
1492 static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1493 static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1494 static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1495 static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1496 static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1497 static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1498 static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1499 static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1500 static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1501 static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1502 static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1503 static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1504 static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1505 static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1506 static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1507 static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1508 static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1509 static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1510 static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1511 static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1512 static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1513 static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1514 static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1515 static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1516 static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1517 static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1518 static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1519 static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1520 static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1521 static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1522 static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1523 static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1524 static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1525 static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1526 static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1527 static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1528 static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1529 static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1530
1531 static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1532 MUX(1, 119, 0, N, N, N, N),
1533 MUX(1, 120, 0, N, N, N, N),
1534 MUX(1, 121, 0, N, N, N, N),
1535 MUX(1, 122, 0, N, N, N, N),
1536 MUX(1, 123, 0, N, N, N, N),
1537 MUX(1, 124, 0, N, N, N, N),
1538 MUX(1, 125, 0, N, N, N, N),
1539 MUX(1, 126, 0, N, N, N, N),
1540 MUX(1, 127, 0, N, N, N, N),
1541 MUX(1, 128, 0, N, N, N, N),
1542 MUX(1, 22, 0, N, N, N, N),
1543 MUX(1, 23, 0, N, N, N, N),
1544 MUX(1, 24, 0, N, N, N, N),
1545 MUX(1, 25, 0, N, N, N, N),
1546 MUX(1, 26, 0, N, N, N, N),
1547 MUX(1, 27, 0, N, N, N, N),
1548 MUX(1, 28, 0, N, N, N, N),
1549 MUX(1, 29, 0, N, N, N, N),
1550 MUX(1, 30, 0, N, N, N, N),
1551 };
1552
1553 static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1554 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1555 .pad_mux_list = gnss_gpio_grp_pad_mux,
1556 };
1557
1558 static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1559 MUX(1, 74, 0, N, N, N, N),
1560 MUX(1, 75, 0, N, N, N, N),
1561 MUX(1, 76, 0, N, N, N, N),
1562 MUX(1, 77, 0, N, N, N, N),
1563 MUX(1, 78, 0, N, N, N, N),
1564 MUX(1, 79, 0, N, N, N, N),
1565 MUX(1, 80, 0, N, N, N, N),
1566 MUX(1, 81, 0, N, N, N, N),
1567 MUX(1, 82, 0, N, N, N, N),
1568 MUX(1, 83, 0, N, N, N, N),
1569 MUX(1, 84, 0, N, N, N, N),
1570 MUX(1, 53, 0, N, N, N, N),
1571 MUX(1, 54, 0, N, N, N, N),
1572 MUX(1, 55, 0, N, N, N, N),
1573 MUX(1, 56, 0, N, N, N, N),
1574 MUX(1, 57, 0, N, N, N, N),
1575 MUX(1, 58, 0, N, N, N, N),
1576 MUX(1, 59, 0, N, N, N, N),
1577 MUX(1, 60, 0, N, N, N, N),
1578 MUX(1, 61, 0, N, N, N, N),
1579 MUX(1, 62, 0, N, N, N, N),
1580 MUX(1, 63, 0, N, N, N, N),
1581 MUX(1, 64, 0, N, N, N, N),
1582 MUX(1, 65, 0, N, N, N, N),
1583 MUX(1, 66, 0, N, N, N, N),
1584 MUX(1, 67, 0, N, N, N, N),
1585 MUX(1, 68, 0, N, N, N, N),
1586 MUX(1, 69, 0, N, N, N, N),
1587 MUX(1, 70, 0, N, N, N, N),
1588 MUX(1, 71, 0, N, N, N, N),
1589 MUX(1, 72, 0, N, N, N, N),
1590 MUX(1, 73, 0, N, N, N, N),
1591 };
1592
1593 static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1594 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1595 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1596 };
1597
1598 static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1599 MUX(1, 31, 0, N, N, N, N),
1600 MUX(1, 32, 0, N, N, N, N),
1601 MUX(1, 33, 0, N, N, N, N),
1602 MUX(1, 34, 0, N, N, N, N),
1603 MUX(1, 35, 0, N, N, N, N),
1604 MUX(1, 36, 0, N, N, N, N),
1605 MUX(1, 85, 0, N, N, N, N),
1606 MUX(1, 86, 0, N, N, N, N),
1607 MUX(1, 87, 0, N, N, N, N),
1608 MUX(1, 88, 0, N, N, N, N),
1609 MUX(1, 89, 0, N, N, N, N),
1610 MUX(1, 90, 0, N, N, N, N),
1611 MUX(1, 129, 0, N, N, N, N),
1612 MUX(1, 130, 0, N, N, N, N),
1613 MUX(1, 131, 0, N, N, N, N),
1614 MUX(1, 132, 0, N, N, N, N),
1615 MUX(1, 91, 0, N, N, N, N),
1616 MUX(1, 92, 0, N, N, N, N),
1617 MUX(1, 93, 0, N, N, N, N),
1618 MUX(1, 94, 0, N, N, N, N),
1619 MUX(1, 95, 0, N, N, N, N),
1620 MUX(1, 96, 0, N, N, N, N),
1621 MUX(1, 112, 0, N, N, N, N),
1622 MUX(1, 113, 0, N, N, N, N),
1623 MUX(1, 114, 0, N, N, N, N),
1624 MUX(1, 115, 0, N, N, N, N),
1625 MUX(1, 116, 0, N, N, N, N),
1626 MUX(1, 117, 0, N, N, N, N),
1627 MUX(1, 118, 0, N, N, N, N),
1628 };
1629
1630 static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1631 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1632 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1633 };
1634
1635 static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1636 MUX(1, 97, 0, N, N, N, N),
1637 MUX(1, 98, 0, N, N, N, N),
1638 MUX(1, 99, 0, N, N, N, N),
1639 MUX(1, 100, 0, N, N, N, N),
1640 MUX(1, 101, 0, N, N, N, N),
1641 MUX(1, 102, 0, N, N, N, N),
1642 MUX(1, 103, 0, N, N, N, N),
1643 MUX(1, 104, 0, N, N, N, N),
1644 MUX(1, 105, 0, N, N, N, N),
1645 MUX(1, 106, 0, N, N, N, N),
1646 MUX(1, 107, 0, N, N, N, N),
1647 MUX(1, 108, 0, N, N, N, N),
1648 MUX(1, 109, 0, N, N, N, N),
1649 MUX(1, 110, 0, N, N, N, N),
1650 MUX(1, 111, 0, N, N, N, N),
1651 MUX(1, 18, 0, N, N, N, N),
1652 MUX(1, 19, 0, N, N, N, N),
1653 MUX(1, 20, 0, N, N, N, N),
1654 MUX(1, 21, 0, N, N, N, N),
1655 MUX(1, 141, 0, N, N, N, N),
1656 MUX(1, 142, 0, N, N, N, N),
1657 MUX(1, 143, 0, N, N, N, N),
1658 MUX(1, 144, 0, N, N, N, N),
1659 MUX(1, 145, 0, N, N, N, N),
1660 MUX(1, 146, 0, N, N, N, N),
1661 MUX(1, 147, 0, N, N, N, N),
1662 MUX(1, 148, 0, N, N, N, N),
1663 };
1664
1665 static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1666 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1667 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1668 };
1669
1670 static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1671 MUX(1, 157, 0, N, N, N, N),
1672 MUX(1, 158, 0, N, N, N, N),
1673 MUX(1, 155, 0, N, N, N, N),
1674 MUX(1, 156, 0, N, N, N, N),
1675 MUX(1, 153, 0, N, N, N, N),
1676 MUX(1, 154, 0, N, N, N, N),
1677 MUX(1, 151, 0, N, N, N, N),
1678 MUX(1, 152, 0, N, N, N, N),
1679 MUX(1, 149, 0, N, N, N, N),
1680 MUX(1, 150, 0, N, N, N, N),
1681 };
1682
1683 static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1684 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1685 .pad_mux_list = lvds_gpio_grp_pad_mux,
1686 };
1687
1688 static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1689 MUX(1, 44, 0, N, N, N, N),
1690 MUX(1, 43, 0, N, N, N, N),
1691 MUX(1, 42, 0, N, N, N, N),
1692 MUX(1, 41, 0, N, N, N, N),
1693 MUX(1, 40, 0, N, N, N, N),
1694 MUX(1, 39, 0, N, N, N, N),
1695 MUX(1, 38, 0, N, N, N, N),
1696 MUX(1, 37, 0, N, N, N, N),
1697 MUX(1, 46, 0, N, N, N, N),
1698 MUX(1, 47, 0, N, N, N, N),
1699 MUX(1, 48, 0, N, N, N, N),
1700 MUX(1, 49, 0, N, N, N, N),
1701 MUX(1, 50, 0, N, N, N, N),
1702 MUX(1, 52, 0, N, N, N, N),
1703 MUX(1, 51, 0, N, N, N, N),
1704 MUX(1, 45, 0, N, N, N, N),
1705 MUX(1, 133, 0, N, N, N, N),
1706 MUX(1, 134, 0, N, N, N, N),
1707 MUX(1, 135, 0, N, N, N, N),
1708 MUX(1, 136, 0, N, N, N, N),
1709 MUX(1, 137, 0, N, N, N, N),
1710 MUX(1, 138, 0, N, N, N, N),
1711 MUX(1, 139, 0, N, N, N, N),
1712 MUX(1, 140, 0, N, N, N, N),
1713 MUX(1, 159, 0, N, N, N, N),
1714 MUX(1, 160, 0, N, N, N, N),
1715 MUX(1, 161, 0, N, N, N, N),
1716 MUX(1, 162, 0, N, N, N, N),
1717 MUX(1, 163, 0, N, N, N, N),
1718 };
1719
1720 static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1721 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1722 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1723 };
1724
1725 static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1726 MUX(0, 0, 0, N, N, N, N),
1727 MUX(0, 1, 0, N, N, N, N),
1728 MUX(0, 2, 0, N, N, N, N),
1729 MUX(0, 3, 0, N, N, N, N),
1730 MUX(0, 4, 0, N, N, N, N),
1731 MUX(0, 10, 0, N, N, N, N),
1732 MUX(0, 11, 0, N, N, N, N),
1733 MUX(0, 12, 0, N, N, N, N),
1734 MUX(0, 13, 0, N, N, N, N),
1735 MUX(0, 14, 0, N, N, N, N),
1736 MUX(0, 15, 0, N, N, N, N),
1737 MUX(0, 16, 0, N, N, N, N),
1738 MUX(0, 17, 0, N, N, N, N),
1739 MUX(0, 9, 0, N, N, N, N),
1740 };
1741
1742 static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1743 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1744 .pad_mux_list = rtc_gpio_grp_pad_mux,
1745 };
1746
1747 static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1748 MUX(1, 113, 2, N, N, N, N),
1749 MUX(1, 118, 2, N, N, N, N),
1750 MUX(1, 115, 2, N, N, N, N),
1751 MUX(1, 114, 2, N, N, N, N),
1752 };
1753
1754 static struct atlas7_grp_mux audio_ac97_grp_mux = {
1755 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1756 .pad_mux_list = audio_ac97_grp_pad_mux,
1757 };
1758
1759 static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1760 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1761 };
1762
1763 static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1764 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1765 .pad_mux_list = audio_digmic_grp0_pad_mux,
1766 };
1767
1768 static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1769 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1770 };
1771
1772 static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1773 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1774 .pad_mux_list = audio_digmic_grp1_pad_mux,
1775 };
1776
1777 static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1778 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1779 };
1780
1781 static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1782 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1783 .pad_mux_list = audio_digmic_grp2_pad_mux,
1784 };
1785
1786 static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1787 MUX(1, 141, 4, N, N, N, N),
1788 MUX(1, 144, 4, N, N, N, N),
1789 MUX(1, 44, 6, N, N, N, N),
1790 MUX(1, 43, 6, N, N, N, N),
1791 MUX(1, 42, 6, N, N, N, N),
1792 MUX(1, 41, 6, N, N, N, N),
1793 MUX(1, 40, 6, N, N, N, N),
1794 MUX(1, 39, 6, N, N, N, N),
1795 MUX(1, 38, 6, N, N, N, N),
1796 MUX(1, 37, 6, N, N, N, N),
1797 MUX(1, 74, 6, N, N, N, N),
1798 MUX(1, 75, 6, N, N, N, N),
1799 MUX(1, 76, 6, N, N, N, N),
1800 MUX(1, 77, 6, N, N, N, N),
1801 MUX(1, 78, 6, N, N, N, N),
1802 MUX(1, 79, 6, N, N, N, N),
1803 MUX(1, 81, 6, N, N, N, N),
1804 MUX(1, 113, 6, N, N, N, N),
1805 MUX(1, 114, 6, N, N, N, N),
1806 MUX(1, 118, 6, N, N, N, N),
1807 MUX(1, 115, 6, N, N, N, N),
1808 MUX(1, 49, 6, N, N, N, N),
1809 MUX(1, 50, 6, N, N, N, N),
1810 MUX(1, 142, 4, N, N, N, N),
1811 MUX(1, 143, 4, N, N, N, N),
1812 MUX(1, 80, 6, N, N, N, N),
1813 };
1814
1815 static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1816 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1817 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1818 };
1819
1820 static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1821 MUX(1, 118, 1, N, N, N, N),
1822 MUX(1, 115, 1, N, N, N, N),
1823 MUX(1, 116, 1, N, N, N, N),
1824 MUX(1, 117, 1, N, N, N, N),
1825 MUX(1, 112, 1, N, N, N, N),
1826 MUX(1, 113, 1, N, N, N, N),
1827 MUX(1, 114, 1, N, N, N, N),
1828 };
1829
1830 static struct atlas7_grp_mux audio_i2s_grp_mux = {
1831 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1832 .pad_mux_list = audio_i2s_grp_pad_mux,
1833 };
1834
1835 static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1836 MUX(1, 118, 1, N, N, N, N),
1837 MUX(1, 115, 1, N, N, N, N),
1838 MUX(1, 112, 1, N, N, N, N),
1839 MUX(1, 113, 1, N, N, N, N),
1840 MUX(1, 114, 1, N, N, N, N),
1841 };
1842
1843 static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1844 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1845 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1846 };
1847
1848 static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1849 MUX(1, 112, 2, N, N, N, N),
1850 };
1851
1852 static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1853 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1854 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1855 };
1856
1857 static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1858 MUX(1, 112, 3, N, N, N, N),
1859 };
1860
1861 static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1862 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1863 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1864 };
1865
1866 static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1867 MUX(1, 116, 3, N, N, N, N),
1868 };
1869
1870 static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1871 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1872 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1873 };
1874
1875 static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1876 MUX(1, 142, 3, N, N, N, N),
1877 };
1878
1879 static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1880 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1881 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1882 };
1883
1884 static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1885 MUX(1, 143, 1, N, N, N, N),
1886 MUX(1, 142, 1, N, N, N, N),
1887 MUX(1, 141, 1, N, N, N, N),
1888 MUX(1, 144, 1, N, N, N, N),
1889 };
1890
1891 static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1892 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1893 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1894 };
1895
1896 static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1897 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1898 };
1899
1900 static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1901 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1902 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1903 };
1904
1905 static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1906 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1907 };
1908
1909 static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1910 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1911 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1912 };
1913
1914 static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1915 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1916 };
1917
1918 static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1919 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1920 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1921 };
1922
1923 static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1924 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1925 };
1926
1927 static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1928 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1929 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1930 };
1931
1932 static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1933 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1934 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1935 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1936 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1937 };
1938
1939 static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1940 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1941 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1942 };
1943
1944 static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1945 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1946 };
1947
1948 static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1949 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1950 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1951 };
1952
1953 static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1954 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1955 };
1956
1957 static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1958 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1959 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1960 };
1961
1962 static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1963 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1964 };
1965
1966 static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1967 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1968 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1969 };
1970
1971 static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1972 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1973 };
1974
1975 static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1976 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1977 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1978 };
1979
1980 static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1981 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1982 };
1983
1984 static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1985 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1986 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1987 };
1988
1989 static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1990 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1991 };
1992
1993 static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1994 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1995 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1996 };
1997
1998 static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
1999 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
2000 };
2001
2002 static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
2003 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
2004 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
2005 };
2006
2007 static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
2008 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
2009 };
2010
2011 static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2012 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2013 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2014 };
2015
2016 static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2017 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2018 };
2019
2020 static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2021 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2022 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2023 };
2024
2025 static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2026 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2027 };
2028
2029 static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2030 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2031 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2032 };
2033
2034 static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
2035 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2036 };
2037
2038 static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2039 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2040 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2041 };
2042
2043 static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2044 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2045 };
2046
2047 static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2048 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2049 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2050 };
2051
2052 static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2053 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2054 };
2055
2056 static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2057 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2058 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2059 };
2060
2061 static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
2062 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
2063 };
2064
2065 static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
2066 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
2067 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2068 };
2069
2070 static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2071 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2072 };
2073
2074 static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2075 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2076 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2077 };
2078
2079 static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2080 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2081 };
2082
2083 static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2084 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2085 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2086 };
2087
2088 static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2089 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2090 };
2091
2092 static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2093 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2094 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2095 };
2096
2097 static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2098 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2099 };
2100
2101 static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2102 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2103 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2104 };
2105
2106 static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2107 MUX(0, 2, 6, N, N, N, N),
2108 };
2109
2110 static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2111 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2112 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2113 };
2114
2115 static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2116 MUX(0, 0, 2, N, N, N, N),
2117 };
2118
2119 static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2120 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2121 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2122 };
2123
2124 static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
2125 MUX(0, 1, 2, N, N, N, N),
2126 };
2127
2128 static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
2129 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
2130 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
2131 };
2132
2133 static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2134 MUX(0, 3, 6, N, N, N, N),
2135 };
2136
2137 static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2138 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2139 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2140 };
2141
2142 static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
2143 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2144 };
2145
2146 static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2147 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2148 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2149 };
2150
2151 static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2152 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2153 };
2154
2155 static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2156 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2157 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2158 };
2159
2160 static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
2161 MUX(0, 10, 1, N, N, N, N),
2162 };
2163
2164 static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
2165 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
2166 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
2167 };
2168
2169 static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
2170 MUX(0, 3, 5, N, N, N, N),
2171 };
2172
2173 static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
2174 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
2175 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
2176 };
2177
2178 static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
2179 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
2180 };
2181
2182 static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
2183 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
2184 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
2185 };
2186
2187 static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
2188 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
2189 };
2190
2191 static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
2192 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
2193 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
2194 };
2195
2196 static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
2197 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2198 };
2199
2200 static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2201 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2202 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2203 };
2204
2205 static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2206 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2207 };
2208
2209 static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2210 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2211 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2212 };
2213
2214 static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2215 MUX(1, 137, 2, N, N, N, N),
2216 };
2217
2218 static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2219 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2220 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2221 };
2222
2223 static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2224 MUX(1, 146, 2, N, N, N, N),
2225 };
2226
2227 static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2228 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2229 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2230 };
2231
2232 static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
2233 MUX(0, 3, 2, N, N, N, N),
2234 };
2235
2236 static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
2237 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
2238 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2239 };
2240
2241 static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2242 MUX(1, 161, 4, N, N, N, N),
2243 };
2244
2245 static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2246 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2247 .pad_mux_list = c1_can_txd_grp3_pad_mux,
2248 };
2249
2250 static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
2251 MUX(1, 62, 4, N, N, N, N),
2252 MUX(1, 63, 4, N, N, N, N),
2253 MUX(1, 64, 4, N, N, N, N),
2254 MUX(1, 65, 4, N, N, N, N),
2255 MUX(1, 66, 4, N, N, N, N),
2256 MUX(1, 67, 4, N, N, N, N),
2257 MUX(1, 68, 4, N, N, N, N),
2258 MUX(1, 69, 4, N, N, N, N),
2259 MUX(1, 70, 4, N, N, N, N),
2260 MUX(1, 71, 4, N, N, N, N),
2261 };
2262
2263 static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
2264 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
2265 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
2266 };
2267
2268 static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
2269 MUX(1, 85, 5, N, N, N, N),
2270 MUX(1, 86, 5, N, N, N, N),
2271 MUX(1, 87, 5, N, N, N, N),
2272 MUX(1, 88, 5, N, N, N, N),
2273 MUX(1, 89, 5, N, N, N, N),
2274 MUX(1, 90, 5, N, N, N, N),
2275 };
2276
2277 static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
2278 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
2279 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
2280 };
2281
2282 static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
2283 MUX(1, 129, 1, N, N, N, N),
2284 MUX(1, 130, 1, N, N, N, N),
2285 MUX(1, 131, 1, N, N, N, N),
2286 MUX(1, 132, 1, N, N, N, N),
2287 };
2288
2289 static struct atlas7_grp_mux ca_coex_grp_mux = {
2290 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
2291 .pad_mux_list = ca_coex_grp_pad_mux,
2292 };
2293
2294 static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
2295 MUX(1, 57, 4, N, N, N, N),
2296 MUX(1, 58, 4, N, N, N, N),
2297 MUX(1, 59, 4, N, N, N, N),
2298 MUX(1, 60, 4, N, N, N, N),
2299 };
2300
2301 static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
2302 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
2303 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
2304 };
2305
2306 static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
2307 MUX(1, 91, 5, N, N, N, N),
2308 MUX(1, 93, 5, N, N, N, N),
2309 MUX(1, 94, 5, N, N, N, N),
2310 MUX(1, 92, 5, N, N, N, N),
2311 };
2312
2313 static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
2314 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
2315 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
2316 };
2317
2318 static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
2319 MUX(1, 121, 2, N, N, N, N),
2320 MUX(1, 122, 2, N, N, N, N),
2321 MUX(1, 125, 6, N, N, N, N),
2322 MUX(1, 126, 6, N, N, N, N),
2323 MUX(1, 38, 5, N, N, N, N),
2324 MUX(1, 37, 5, N, N, N, N),
2325 MUX(1, 47, 5, N, N, N, N),
2326 MUX(1, 49, 5, N, N, N, N),
2327 MUX(1, 50, 5, N, N, N, N),
2328 MUX(1, 54, 4, N, N, N, N),
2329 MUX(1, 55, 4, N, N, N, N),
2330 MUX(1, 56, 4, N, N, N, N),
2331 };
2332
2333 static struct atlas7_grp_mux ca_pio_grp_mux = {
2334 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
2335 .pad_mux_list = ca_pio_grp_pad_mux,
2336 };
2337
2338 static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
2339 MUX(1, 40, 5, N, N, N, N),
2340 MUX(1, 39, 5, N, N, N, N),
2341 MUX(1, 44, 5, N, N, N, N),
2342 MUX(1, 43, 5, N, N, N, N),
2343 MUX(1, 42, 5, N, N, N, N),
2344 MUX(1, 41, 5, N, N, N, N),
2345 };
2346
2347 static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
2348 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
2349 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
2350 };
2351
2352 static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
2353 MUX(1, 82, 5, N, N, N, N),
2354 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
2355 MUX(1, 80, 5, N, N, N, N),
2356 MUX(1, 81, 5, N, N, N, N),
2357 };
2358
2359 static struct atlas7_grp_mux ca_spi_grp_mux = {
2360 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
2361 .pad_mux_list = ca_spi_grp_pad_mux,
2362 };
2363
2364 static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
2365 MUX(1, 91, 4, N, N, N, N),
2366 MUX(1, 93, 4, N, N, N, N),
2367 MUX(1, 94, 4, N, N, N, N),
2368 MUX(1, 95, 4, N, N, N, N),
2369 MUX(1, 96, 4, N, N, N, N),
2370 MUX(1, 78, 5, N, N, N, N),
2371 MUX(1, 74, 5, N, N, N, N),
2372 MUX(1, 75, 5, N, N, N, N),
2373 MUX(1, 76, 5, N, N, N, N),
2374 MUX(1, 77, 5, N, N, N, N),
2375 };
2376
2377 static struct atlas7_grp_mux ca_trb_grp_mux = {
2378 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
2379 .pad_mux_list = ca_trb_grp_pad_mux,
2380 };
2381
2382 static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
2383 MUX(1, 136, 3, N, N, N, N),
2384 MUX(1, 135, 3, N, N, N, N),
2385 MUX(1, 134, 3, N, N, N, N),
2386 MUX(1, 133, 3, N, N, N, N),
2387 };
2388
2389 static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
2390 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
2391 .pad_mux_list = ca_uart_debug_grp_pad_mux,
2392 };
2393
2394 static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
2395 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
2396 MUX(1, 47, 6, N, N, N, N),
2397 };
2398
2399 static struct atlas7_grp_mux clkc_grp0_mux = {
2400 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
2401 .pad_mux_list = clkc_grp0_pad_mux,
2402 };
2403
2404 static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
2405 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
2406 MUX(1, 54, 5, N, N, N, N),
2407 };
2408
2409 static struct atlas7_grp_mux clkc_grp1_mux = {
2410 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
2411 .pad_mux_list = clkc_grp1_pad_mux,
2412 };
2413
2414 static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
2415 MUX(1, 128, 2, N, N, N, N),
2416 MUX(1, 127, 2, N, N, N, N),
2417 };
2418
2419 static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
2420 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
2421 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
2422 };
2423
2424 static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
2425 MUX(1, 134, 4, N, N, N, N),
2426 MUX(1, 133, 4, N, N, N, N),
2427 };
2428
2429 static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
2430 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
2431 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
2432 };
2433
2434 static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
2435 MUX(1, 134, 4, N, N, N, N),
2436 MUX(1, 133, 4, N, N, N, N),
2437 MUX(1, 136, 4, N, N, N, N),
2438 MUX(1, 135, 4, N, N, N, N),
2439 };
2440
2441 static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
2442 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
2443 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
2444 };
2445
2446 static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
2447 MUX(1, 22, 1, N, N, N, N),
2448 MUX(1, 25, 1, N, N, N, N),
2449 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
2450 MUX(1, 24, 1, N, N, N, N),
2451 };
2452
2453 static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
2454 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
2455 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
2456 };
2457
2458 static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
2459 MUX(1, 82, 3, N, N, N, N),
2460 MUX(1, 79, 3, N, N, N, N),
2461 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
2462 MUX(1, 81, 3, N, N, N, N),
2463 };
2464
2465 static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
2466 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
2467 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
2468 };
2469
2470 static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
2471 MUX(1, 54, 3, N, N, N, N),
2472 MUX(1, 53, 3, N, N, N, N),
2473 MUX(1, 82, 7, N, N, N, N),
2474 MUX(1, 74, 7, N, N, N, N),
2475 MUX(1, 75, 7, N, N, N, N),
2476 MUX(1, 76, 7, N, N, N, N),
2477 MUX(1, 77, 7, N, N, N, N),
2478 MUX(1, 78, 7, N, N, N, N),
2479 MUX(1, 79, 7, N, N, N, N),
2480 MUX(1, 80, 7, N, N, N, N),
2481 MUX(1, 81, 7, N, N, N, N),
2482 MUX(1, 83, 7, N, N, N, N),
2483 MUX(1, 84, 7, N, N, N, N),
2484 MUX(1, 73, 3, N, N, N, N),
2485 MUX(1, 55, 3, N, N, N, N),
2486 MUX(1, 56, 3, N, N, N, N),
2487 };
2488
2489 static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
2490 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
2491 .pad_mux_list = cvbs_dbg_grp_pad_mux,
2492 };
2493
2494 static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
2495 MUX(1, 57, 3, N, N, N, N),
2496 };
2497
2498 static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
2499 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
2500 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
2501 };
2502
2503 static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
2504 MUX(1, 58, 3, N, N, N, N),
2505 };
2506
2507 static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
2508 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
2509 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
2510 };
2511
2512 static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
2513 MUX(1, 59, 3, N, N, N, N),
2514 };
2515
2516 static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
2517 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
2518 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
2519 };
2520
2521 static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
2522 MUX(1, 60, 3, N, N, N, N),
2523 };
2524
2525 static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
2526 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
2527 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
2528 };
2529
2530 static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
2531 MUX(1, 61, 3, N, N, N, N),
2532 };
2533
2534 static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
2535 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
2536 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
2537 };
2538
2539 static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
2540 MUX(1, 62, 3, N, N, N, N),
2541 };
2542
2543 static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
2544 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
2545 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
2546 };
2547
2548 static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
2549 MUX(1, 63, 3, N, N, N, N),
2550 };
2551
2552 static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
2553 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
2554 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
2555 };
2556
2557 static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
2558 MUX(1, 64, 3, N, N, N, N),
2559 };
2560
2561 static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
2562 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
2563 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
2564 };
2565
2566 static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
2567 MUX(1, 65, 3, N, N, N, N),
2568 };
2569
2570 static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
2571 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
2572 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
2573 };
2574
2575 static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
2576 MUX(1, 66, 3, N, N, N, N),
2577 };
2578
2579 static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
2580 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
2581 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
2582 };
2583
2584 static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
2585 MUX(1, 67, 3, N, N, N, N),
2586 };
2587
2588 static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
2589 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
2590 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
2591 };
2592
2593 static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
2594 MUX(1, 68, 3, N, N, N, N),
2595 };
2596
2597 static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
2598 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
2599 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
2600 };
2601
2602 static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
2603 MUX(1, 69, 3, N, N, N, N),
2604 };
2605
2606 static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
2607 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
2608 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
2609 };
2610
2611 static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
2612 MUX(1, 70, 3, N, N, N, N),
2613 };
2614
2615 static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
2616 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
2617 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
2618 };
2619
2620 static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
2621 MUX(1, 71, 3, N, N, N, N),
2622 };
2623
2624 static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
2625 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
2626 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
2627 };
2628
2629 static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
2630 MUX(1, 72, 3, N, N, N, N),
2631 };
2632
2633 static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
2634 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
2635 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
2636 };
2637
2638 static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
2639 MUX(1, 123, 7, N, N, N, N),
2640 MUX(1, 124, 7, N, N, N, N),
2641 MUX(1, 121, 7, N, N, N, N),
2642 MUX(1, 122, 7, N, N, N, N),
2643 MUX(1, 125, 7, N, N, N, N),
2644 MUX(1, 120, 7, N, N, N, N),
2645 };
2646
2647 static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
2648 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
2649 .pad_mux_list = gn_gnss_power_grp_pad_mux,
2650 };
2651
2652 static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
2653 MUX(1, 57, 7, N, N, N, N),
2654 MUX(1, 58, 7, N, N, N, N),
2655 MUX(1, 59, 7, N, N, N, N),
2656 MUX(1, 60, 7, N, N, N, N),
2657 MUX(1, 61, 7, N, N, N, N),
2658 MUX(1, 62, 7, N, N, N, N),
2659 MUX(1, 63, 7, N, N, N, N),
2660 MUX(1, 64, 7, N, N, N, N),
2661 MUX(1, 65, 7, N, N, N, N),
2662 MUX(1, 66, 7, N, N, N, N),
2663 MUX(1, 67, 7, N, N, N, N),
2664 MUX(1, 68, 7, N, N, N, N),
2665 MUX(1, 69, 7, N, N, N, N),
2666 MUX(1, 70, 7, N, N, N, N),
2667 MUX(1, 71, 7, N, N, N, N),
2668 MUX(1, 72, 7, N, N, N, N),
2669 MUX(1, 53, 7, N, N, N, N),
2670 MUX(1, 55, 7, N, N, N, N),
2671 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2672 MUX(1, 54, 7, N, N, N, N),
2673 };
2674
2675 static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2676 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2677 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2678 };
2679
2680 static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2681 MUX(1, 113, 4, N, N, N, N),
2682 };
2683
2684 static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2685 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2686 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2687 };
2688
2689 static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2690 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2691 };
2692
2693 static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2694 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2695 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2696 };
2697
2698 static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2699 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2700 };
2701
2702 static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2703 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2704 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2705 };
2706
2707 static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2708 MUX(1, 115, 4, N, N, N, N),
2709 };
2710
2711 static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2712 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2713 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2714 };
2715
2716 static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2717 MUX(1, 114, 4, N, N, N, N),
2718 };
2719
2720 static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2721 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2722 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2723 };
2724
2725 static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2726 MUX(1, 44, 7, N, N, N, N),
2727 MUX(1, 43, 7, N, N, N, N),
2728 MUX(1, 42, 7, N, N, N, N),
2729 MUX(1, 41, 7, N, N, N, N),
2730 MUX(1, 40, 7, N, N, N, N),
2731 MUX(1, 39, 7, N, N, N, N),
2732 MUX(1, 38, 7, N, N, N, N),
2733 MUX(1, 37, 7, N, N, N, N),
2734 MUX(1, 49, 7, N, N, N, N),
2735 MUX(1, 50, 7, N, N, N, N),
2736 MUX(1, 91, 7, N, N, N, N),
2737 MUX(1, 92, 7, N, N, N, N),
2738 MUX(1, 93, 7, N, N, N, N),
2739 MUX(1, 94, 7, N, N, N, N),
2740 MUX(1, 95, 7, N, N, N, N),
2741 MUX(1, 96, 7, N, N, N, N),
2742 };
2743
2744 static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2745 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2746 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2747 };
2748
2749 static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2750 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2751 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2752 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2753 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2754 };
2755
2756 static struct atlas7_grp_mux gn_trg_grp0_mux = {
2757 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2758 .pad_mux_list = gn_trg_grp0_pad_mux,
2759 };
2760
2761 static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2762 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2763 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2764 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2765 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2766 };
2767
2768 static struct atlas7_grp_mux gn_trg_grp1_mux = {
2769 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2770 .pad_mux_list = gn_trg_grp1_pad_mux,
2771 };
2772
2773 static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2774 MUX(1, 30, 1, N, N, N, N),
2775 };
2776
2777 static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2778 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2779 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2780 };
2781
2782 static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2783 MUX(1, 83, 3, N, N, N, N),
2784 };
2785
2786 static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2787 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2788 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2789 };
2790
2791 static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2792 MUX(1, 117, 4, N, N, N, N),
2793 };
2794
2795 static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2796 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2797 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2798 };
2799
2800 static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2801 MUX(1, 123, 5, N, N, N, N),
2802 };
2803
2804 static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2805 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2806 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2807 };
2808
2809 static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2810 MUX(1, 128, 1, N, N, N, N),
2811 MUX(1, 127, 1, N, N, N, N),
2812 };
2813
2814 static struct atlas7_grp_mux i2c0_grp_mux = {
2815 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2816 .pad_mux_list = i2c0_grp_pad_mux,
2817 };
2818
2819 static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2820 MUX(1, 126, 4, N, N, N, N),
2821 MUX(1, 125, 4, N, N, N, N),
2822 };
2823
2824 static struct atlas7_grp_mux i2c1_grp_mux = {
2825 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2826 .pad_mux_list = i2c1_grp_pad_mux,
2827 };
2828
2829 static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2830 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2831 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2832 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2833 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2834 };
2835
2836 static struct atlas7_grp_mux i2s0_grp_mux = {
2837 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2838 .pad_mux_list = i2s0_grp_pad_mux,
2839 };
2840
2841 static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2842 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2843 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2844 };
2845
2846 static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2847 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2848 .pad_mux_list = i2s1_basic_grp_pad_mux,
2849 };
2850
2851 static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2852 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2853 };
2854
2855 static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2856 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2857 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2858 };
2859
2860 static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2861 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2862 };
2863
2864 static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2865 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2866 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2867 };
2868
2869 static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2870 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2871 };
2872
2873 static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2874 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2875 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2876 };
2877
2878 static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2879 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2880 };
2881
2882 static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2883 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2884 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2885 };
2886
2887 static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2888 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2889 };
2890
2891 static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2892 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2893 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2894 };
2895
2896 static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2897 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2898 };
2899
2900 static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2901 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2902 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2903 };
2904
2905 static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2906 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2907 };
2908
2909 static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2910 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2911 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2912 };
2913
2914 static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2915 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2916 };
2917
2918 static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2919 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2920 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2921 };
2922
2923 static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2924 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2925 };
2926
2927 static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2928 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2929 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2930 };
2931
2932 static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2933 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2934 };
2935
2936 static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2937 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2938 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2939 };
2940
2941 static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2942 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2943 };
2944
2945 static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2946 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2947 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2948 };
2949
2950 static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2951 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2952 };
2953
2954 static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2955 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2956 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2957 };
2958
2959 static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2960 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2961 };
2962
2963 static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2964 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2965 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2966 };
2967
2968 static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2969 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2970 };
2971
2972 static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2973 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2974 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2975 };
2976
2977 static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2978 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2979 };
2980
2981 static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2982 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2983 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2984 };
2985
2986 static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2987 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2988 };
2989
2990 static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2991 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2992 .pad_mux_list = jtag_tck_grp0_pad_mux,
2993 };
2994
2995 static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2996 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
2997 };
2998
2999 static struct atlas7_grp_mux jtag_tck_grp1_mux = {
3000 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
3001 .pad_mux_list = jtag_tck_grp1_pad_mux,
3002 };
3003
3004 static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3005 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3006 };
3007
3008 static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3009 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3010 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3011 };
3012
3013 static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3014 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3015 };
3016
3017 static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3018 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3019 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3020 };
3021
3022 static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
3023 MUX(0, 3, 3, N, N, N, N),
3024 };
3025
3026 static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
3027 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
3028 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3029 };
3030
3031 static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3032 MUX(1, 159, 1, N, N, N, N),
3033 };
3034
3035 static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3036 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3037 .pad_mux_list = jtag_tdo_grp1_pad_mux,
3038 };
3039
3040 static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
3041 MUX(1, 141, 2, N, N, N, N),
3042 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
3043 MUX(1, 143, 2, N, N, N, N),
3044 MUX(1, 142, 2, N, N, N, N),
3045 };
3046
3047 static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
3048 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
3049 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
3050 };
3051
3052 static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
3053 MUX(1, 57, 1, N, N, N, N),
3054 MUX(1, 58, 1, N, N, N, N),
3055 MUX(1, 59, 1, N, N, N, N),
3056 MUX(1, 60, 1, N, N, N, N),
3057 MUX(1, 61, 1, N, N, N, N),
3058 MUX(1, 62, 1, N, N, N, N),
3059 MUX(1, 63, 1, N, N, N, N),
3060 MUX(1, 64, 1, N, N, N, N),
3061 MUX(1, 65, 1, N, N, N, N),
3062 MUX(1, 66, 1, N, N, N, N),
3063 MUX(1, 67, 1, N, N, N, N),
3064 MUX(1, 68, 1, N, N, N, N),
3065 MUX(1, 69, 1, N, N, N, N),
3066 MUX(1, 70, 1, N, N, N, N),
3067 MUX(1, 71, 1, N, N, N, N),
3068 MUX(1, 72, 1, N, N, N, N),
3069 MUX(1, 74, 2, N, N, N, N),
3070 MUX(1, 75, 2, N, N, N, N),
3071 MUX(1, 76, 2, N, N, N, N),
3072 MUX(1, 77, 2, N, N, N, N),
3073 MUX(1, 78, 2, N, N, N, N),
3074 MUX(1, 79, 2, N, N, N, N),
3075 MUX(1, 80, 2, N, N, N, N),
3076 MUX(1, 81, 2, N, N, N, N),
3077 MUX(1, 56, 1, N, N, N, N),
3078 MUX(1, 53, 1, N, N, N, N),
3079 };
3080
3081 static struct atlas7_grp_mux ld_ldd_grp_mux = {
3082 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
3083 .pad_mux_list = ld_ldd_grp_pad_mux,
3084 };
3085
3086 static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
3087 MUX(1, 57, 1, N, N, N, N),
3088 MUX(1, 58, 1, N, N, N, N),
3089 MUX(1, 59, 1, N, N, N, N),
3090 MUX(1, 60, 1, N, N, N, N),
3091 MUX(1, 61, 1, N, N, N, N),
3092 MUX(1, 62, 1, N, N, N, N),
3093 MUX(1, 63, 1, N, N, N, N),
3094 MUX(1, 64, 1, N, N, N, N),
3095 MUX(1, 65, 1, N, N, N, N),
3096 MUX(1, 66, 1, N, N, N, N),
3097 MUX(1, 67, 1, N, N, N, N),
3098 MUX(1, 68, 1, N, N, N, N),
3099 MUX(1, 69, 1, N, N, N, N),
3100 MUX(1, 70, 1, N, N, N, N),
3101 MUX(1, 71, 1, N, N, N, N),
3102 MUX(1, 72, 1, N, N, N, N),
3103 MUX(1, 56, 1, N, N, N, N),
3104 MUX(1, 53, 1, N, N, N, N),
3105 };
3106
3107 static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
3108 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
3109 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
3110 };
3111
3112 static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
3113 MUX(1, 55, 1, N, N, N, N),
3114 };
3115
3116 static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
3117 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
3118 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
3119 };
3120
3121 static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
3122 MUX(1, 54, 1, N, N, N, N),
3123 };
3124
3125 static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
3126 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
3127 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
3128 };
3129
3130 static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
3131 MUX(1, 73, 2, N, N, N, N),
3132 MUX(1, 54, 2, N, N, N, N),
3133 MUX(1, 57, 2, N, N, N, N),
3134 MUX(1, 58, 2, N, N, N, N),
3135 MUX(1, 59, 2, N, N, N, N),
3136 MUX(1, 60, 2, N, N, N, N),
3137 MUX(1, 61, 2, N, N, N, N),
3138 MUX(1, 62, 2, N, N, N, N),
3139 MUX(1, 63, 2, N, N, N, N),
3140 MUX(1, 64, 2, N, N, N, N),
3141 MUX(1, 65, 2, N, N, N, N),
3142 MUX(1, 66, 2, N, N, N, N),
3143 MUX(1, 67, 2, N, N, N, N),
3144 MUX(1, 68, 2, N, N, N, N),
3145 MUX(1, 69, 2, N, N, N, N),
3146 MUX(1, 70, 2, N, N, N, N),
3147 MUX(1, 71, 2, N, N, N, N),
3148 MUX(1, 72, 2, N, N, N, N),
3149 MUX(1, 56, 2, N, N, N, N),
3150 MUX(1, 53, 2, N, N, N, N),
3151 MUX(1, 55, 2, N, N, N, N),
3152 };
3153
3154 static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
3155 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
3156 .pad_mux_list = lr_lcdrom_grp_pad_mux,
3157 };
3158
3159 static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
3160 MUX(1, 149, 8, N, N, N, N),
3161 MUX(1, 150, 8, N, N, N, N),
3162 MUX(1, 151, 8, N, N, N, N),
3163 MUX(1, 152, 8, N, N, N, N),
3164 MUX(1, 153, 8, N, N, N, N),
3165 MUX(1, 154, 8, N, N, N, N),
3166 MUX(1, 155, 8, N, N, N, N),
3167 MUX(1, 156, 8, N, N, N, N),
3168 MUX(1, 157, 8, N, N, N, N),
3169 MUX(1, 158, 8, N, N, N, N),
3170 };
3171
3172 static struct atlas7_grp_mux lvds_analog_grp_mux = {
3173 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
3174 .pad_mux_list = lvds_analog_grp_pad_mux,
3175 };
3176
3177 static struct atlas7_pad_mux nd_df_grp_pad_mux[] = {
3178 MUX(1, 44, 1, N, N, N, N),
3179 MUX(1, 43, 1, N, N, N, N),
3180 MUX(1, 42, 1, N, N, N, N),
3181 MUX(1, 41, 1, N, N, N, N),
3182 MUX(1, 40, 1, N, N, N, N),
3183 MUX(1, 39, 1, N, N, N, N),
3184 MUX(1, 38, 1, N, N, N, N),
3185 MUX(1, 37, 1, N, N, N, N),
3186 MUX(1, 47, 1, N, N, N, N),
3187 MUX(1, 46, 1, N, N, N, N),
3188 MUX(1, 52, 1, N, N, N, N),
3189 MUX(1, 51, 1, N, N, N, N),
3190 MUX(1, 45, 1, N, N, N, N),
3191 MUX(1, 49, 1, N, N, N, N),
3192 MUX(1, 50, 1, N, N, N, N),
3193 MUX(1, 48, 1, N, N, N, N),
3194 MUX(1, 124, 4, N, N, N, N),
3195 };
3196
3197 static struct atlas7_grp_mux nd_df_grp_mux = {
3198 .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux),
3199 .pad_mux_list = nd_df_grp_pad_mux,
3200 };
3201
3202 static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = {
3203 MUX(1, 44, 1, N, N, N, N),
3204 MUX(1, 43, 1, N, N, N, N),
3205 MUX(1, 42, 1, N, N, N, N),
3206 MUX(1, 41, 1, N, N, N, N),
3207 MUX(1, 40, 1, N, N, N, N),
3208 MUX(1, 39, 1, N, N, N, N),
3209 MUX(1, 38, 1, N, N, N, N),
3210 MUX(1, 37, 1, N, N, N, N),
3211 MUX(1, 47, 1, N, N, N, N),
3212 MUX(1, 46, 1, N, N, N, N),
3213 MUX(1, 52, 1, N, N, N, N),
3214 MUX(1, 51, 1, N, N, N, N),
3215 MUX(1, 45, 1, N, N, N, N),
3216 MUX(1, 49, 1, N, N, N, N),
3217 MUX(1, 50, 1, N, N, N, N),
3218 MUX(1, 48, 1, N, N, N, N),
3219 };
3220
3221 static struct atlas7_grp_mux nd_df_nowp_grp_mux = {
3222 .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux),
3223 .pad_mux_list = nd_df_nowp_grp_pad_mux,
3224 };
3225
3226 static struct atlas7_pad_mux ps_grp_pad_mux[] = {
3227 MUX(1, 120, 2, N, N, N, N),
3228 MUX(1, 119, 2, N, N, N, N),
3229 MUX(1, 121, 5, N, N, N, N),
3230 };
3231
3232 static struct atlas7_grp_mux ps_grp_mux = {
3233 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
3234 .pad_mux_list = ps_grp_pad_mux,
3235 };
3236
3237 static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
3238 MUX(0, 8, 1, N, N, N, N),
3239 };
3240
3241 static struct atlas7_grp_mux pwc_core_on_grp_mux = {
3242 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
3243 .pad_mux_list = pwc_core_on_grp_pad_mux,
3244 };
3245
3246 static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
3247 MUX(0, 6, 1, N, N, N, N),
3248 };
3249
3250 static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
3251 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
3252 .pad_mux_list = pwc_ext_on_grp_pad_mux,
3253 };
3254
3255 static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
3256 MUX(0, 3, 4, N, N, N, N),
3257 };
3258
3259 static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
3260 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
3261 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
3262 };
3263
3264 static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
3265 MUX(0, 9, 1, N, N, N, N),
3266 };
3267
3268 static struct atlas7_grp_mux pwc_io_on_grp_mux = {
3269 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
3270 .pad_mux_list = pwc_io_on_grp_pad_mux,
3271 };
3272
3273 static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
3274 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
3275 };
3276
3277 static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
3278 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
3279 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
3280 };
3281
3282 static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
3283 MUX(0, 7, 1, N, N, N, N),
3284 };
3285
3286 static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
3287 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
3288 .pad_mux_list = pwc_mem_on_grp_pad_mux,
3289 };
3290
3291 static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
3292 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
3293 };
3294
3295 static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
3296 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
3297 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
3298 };
3299
3300 static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
3301 MUX(0, 0, 1, N, N, N, N),
3302 };
3303
3304 static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
3305 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
3306 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
3307 };
3308
3309 static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
3310 MUX(0, 1, 1, N, N, N, N),
3311 };
3312
3313 static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
3314 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
3315 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
3316 };
3317
3318 static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
3319 MUX(0, 2, 1, N, N, N, N),
3320 };
3321
3322 static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
3323 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
3324 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
3325 };
3326
3327 static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
3328 MUX(0, 3, 1, N, N, N, N),
3329 };
3330
3331 static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
3332 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
3333 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
3334 };
3335
3336 static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
3337 MUX(1, 123, 3, N, N, N, N),
3338 };
3339
3340 static struct atlas7_grp_mux pw_cko0_grp0_mux = {
3341 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
3342 .pad_mux_list = pw_cko0_grp0_pad_mux,
3343 };
3344
3345 static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
3346 MUX(1, 101, 4, N, N, N, N),
3347 };
3348
3349 static struct atlas7_grp_mux pw_cko0_grp1_mux = {
3350 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
3351 .pad_mux_list = pw_cko0_grp1_pad_mux,
3352 };
3353
3354 static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
3355 MUX(1, 82, 2, N, N, N, N),
3356 };
3357
3358 static struct atlas7_grp_mux pw_cko0_grp2_mux = {
3359 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
3360 .pad_mux_list = pw_cko0_grp2_pad_mux,
3361 };
3362
3363 static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3364 MUX(1, 162, 5, N, N, N, N),
3365 };
3366
3367 static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3368 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3369 .pad_mux_list = pw_cko0_grp3_pad_mux,
3370 };
3371
3372 static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
3373 MUX(1, 124, 3, N, N, N, N),
3374 };
3375
3376 static struct atlas7_grp_mux pw_cko1_grp0_mux = {
3377 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
3378 .pad_mux_list = pw_cko1_grp0_pad_mux,
3379 };
3380
3381 static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
3382 MUX(1, 110, 4, N, N, N, N),
3383 };
3384
3385 static struct atlas7_grp_mux pw_cko1_grp1_mux = {
3386 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
3387 .pad_mux_list = pw_cko1_grp1_pad_mux,
3388 };
3389
3390 static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3391 MUX(1, 163, 5, N, N, N, N),
3392 };
3393
3394 static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3395 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3396 .pad_mux_list = pw_cko1_grp2_pad_mux,
3397 };
3398
3399 static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
3400 MUX(1, 125, 3, N, N, N, N),
3401 };
3402
3403 static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
3404 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
3405 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
3406 };
3407
3408 static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
3409 MUX(1, 117, 3, N, N, N, N),
3410 };
3411
3412 static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
3413 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
3414 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
3415 };
3416
3417 static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3418 MUX(1, 132, 2, N, N, N, N),
3419 };
3420
3421 static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3422 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3423 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3424 };
3425
3426 static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
3427 MUX(1, 119, 3, N, N, N, N),
3428 };
3429
3430 static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
3431 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
3432 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3433 };
3434
3435 static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3436 MUX(1, 159, 5, N, N, N, N),
3437 };
3438
3439 static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3440 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3441 .pad_mux_list = pw_pwm0_grp1_pad_mux,
3442 };
3443
3444 static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
3445 MUX(1, 120, 3, N, N, N, N),
3446 };
3447
3448 static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
3449 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
3450 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3451 };
3452
3453 static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3454 MUX(1, 160, 5, N, N, N, N),
3455 };
3456
3457 static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3458 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3459 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3460 };
3461
3462 static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3463 MUX(1, 131, 2, N, N, N, N),
3464 };
3465
3466 static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3467 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3468 .pad_mux_list = pw_pwm1_grp2_pad_mux,
3469 };
3470
3471 static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
3472 MUX(1, 121, 3, N, N, N, N),
3473 };
3474
3475 static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
3476 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
3477 .pad_mux_list = pw_pwm2_grp0_pad_mux,
3478 };
3479
3480 static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
3481 MUX(1, 98, 3, N, N, N, N),
3482 };
3483
3484 static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
3485 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
3486 .pad_mux_list = pw_pwm2_grp1_pad_mux,
3487 };
3488
3489 static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3490 MUX(1, 161, 5, N, N, N, N),
3491 };
3492
3493 static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3494 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3495 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3496 };
3497
3498 static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
3499 MUX(1, 122, 3, N, N, N, N),
3500 };
3501
3502 static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
3503 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
3504 .pad_mux_list = pw_pwm3_grp0_pad_mux,
3505 };
3506
3507 static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
3508 MUX(1, 73, 4, N, N, N, N),
3509 };
3510
3511 static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
3512 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
3513 .pad_mux_list = pw_pwm3_grp1_pad_mux,
3514 };
3515
3516 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
3517 MUX(1, 121, 3, N, N, N, N),
3518 };
3519
3520 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
3521 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
3522 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
3523 };
3524
3525 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
3526 MUX(1, 98, 3, N, N, N, N),
3527 };
3528
3529 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
3530 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
3531 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
3532 };
3533
3534 static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3535 MUX(1, 161, 5, N, N, N, N),
3536 };
3537
3538 static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3539 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3540 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3541 };
3542
3543 static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
3544 MUX(1, 122, 3, N, N, N, N),
3545 };
3546
3547 static struct atlas7_grp_mux pw_backlight_grp0_mux = {
3548 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
3549 .pad_mux_list = pw_backlight_grp0_pad_mux,
3550 };
3551
3552 static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
3553 MUX(1, 73, 4, N, N, N, N),
3554 };
3555
3556 static struct atlas7_grp_mux pw_backlight_grp1_mux = {
3557 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
3558 .pad_mux_list = pw_backlight_grp1_pad_mux,
3559 };
3560
3561 static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
3562 MUX(1, 108, 1, N, N, N, N),
3563 MUX(1, 103, 1, N, N, N, N),
3564 MUX(1, 104, 1, N, N, N, N),
3565 MUX(1, 105, 1, N, N, N, N),
3566 MUX(1, 106, 1, N, N, N, N),
3567 MUX(1, 107, 1, N, N, N, N),
3568 MUX(1, 102, 1, N, N, N, N),
3569 MUX(1, 97, 1, N, N, N, N),
3570 MUX(1, 98, 1, N, N, N, N),
3571 MUX(1, 99, 1, N, N, N, N),
3572 MUX(1, 100, 1, N, N, N, N),
3573 MUX(1, 101, 1, N, N, N, N),
3574 };
3575
3576 static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
3577 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
3578 .pad_mux_list = rg_eth_mac_grp_pad_mux,
3579 };
3580
3581 static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
3582 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
3583 };
3584
3585 static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
3586 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
3587 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
3588 };
3589
3590 static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
3591 MUX(1, 109, 1, N, N, N, N),
3592 MUX(1, 110, 1, N, N, N, N),
3593 };
3594
3595 static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
3596 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
3597 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
3598 };
3599
3600 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
3601 MUX(1, 111, 5, N, N, N, N),
3602 };
3603
3604 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
3605 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
3606 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
3607 };
3608
3609 static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
3610 MUX(1, 53, 4, N, N, N, N),
3611 };
3612
3613 static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
3614 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
3615 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
3616 };
3617
3618 static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
3619 MUX(1, 46, 2, N, N, N, N),
3620 MUX(1, 47, 2, N, N, N, N),
3621 MUX(1, 44, 2, N, N, N, N),
3622 MUX(1, 43, 2, N, N, N, N),
3623 MUX(1, 42, 2, N, N, N, N),
3624 MUX(1, 41, 2, N, N, N, N),
3625 MUX(1, 40, 2, N, N, N, N),
3626 MUX(1, 39, 2, N, N, N, N),
3627 MUX(1, 38, 2, N, N, N, N),
3628 MUX(1, 37, 2, N, N, N, N),
3629 };
3630
3631 static struct atlas7_grp_mux sd0_grp_mux = {
3632 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
3633 .pad_mux_list = sd0_grp_pad_mux,
3634 };
3635
3636 static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
3637 MUX(1, 46, 2, N, N, N, N),
3638 MUX(1, 47, 2, N, N, N, N),
3639 MUX(1, 44, 2, N, N, N, N),
3640 MUX(1, 43, 2, N, N, N, N),
3641 MUX(1, 42, 2, N, N, N, N),
3642 MUX(1, 41, 2, N, N, N, N),
3643 };
3644
3645 static struct atlas7_grp_mux sd0_4bit_grp_mux = {
3646 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
3647 .pad_mux_list = sd0_4bit_grp_pad_mux,
3648 };
3649
3650 static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
3651 MUX(1, 48, 3, N, N, N, N),
3652 MUX(1, 49, 3, N, N, N, N),
3653 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3654 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3655 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3656 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3657 MUX(1, 40, 3, N, N, N, N),
3658 MUX(1, 39, 3, N, N, N, N),
3659 MUX(1, 38, 3, N, N, N, N),
3660 MUX(1, 37, 3, N, N, N, N),
3661 };
3662
3663 static struct atlas7_grp_mux sd1_grp_mux = {
3664 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
3665 .pad_mux_list = sd1_grp_pad_mux,
3666 };
3667
3668 static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
3669 MUX(1, 48, 3, N, N, N, N),
3670 MUX(1, 49, 3, N, N, N, N),
3671 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
3672 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
3673 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
3674 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
3675 };
3676
3677 static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
3678 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
3679 .pad_mux_list = sd1_4bit_grp0_pad_mux,
3680 };
3681
3682 static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
3683 MUX(1, 48, 3, N, N, N, N),
3684 MUX(1, 49, 3, N, N, N, N),
3685 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
3686 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
3687 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
3688 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
3689 };
3690
3691 static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
3692 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
3693 .pad_mux_list = sd1_4bit_grp1_pad_mux,
3694 };
3695
3696 static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
3697 MUX(1, 31, 1, N, N, N, N),
3698 MUX(1, 32, 1, N, N, N, N),
3699 MUX(1, 33, 1, N, N, N, N),
3700 MUX(1, 34, 1, N, N, N, N),
3701 MUX(1, 35, 1, N, N, N, N),
3702 MUX(1, 36, 1, N, N, N, N),
3703 };
3704
3705 static struct atlas7_grp_mux sd2_basic_grp_mux = {
3706 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
3707 .pad_mux_list = sd2_basic_grp_pad_mux,
3708 };
3709
3710 static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
3711 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
3712 };
3713
3714 static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
3715 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
3716 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3717 };
3718
3719 static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3720 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3721 };
3722
3723 static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3724 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3725 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3726 };
3727
3728 static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3729 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3730 };
3731
3732 static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3733 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3734 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3735 };
3736
3737 static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3738 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3739 };
3740
3741 static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3742 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3743 .pad_mux_list = sd2_wpb_grp1_pad_mux,
3744 };
3745
3746 static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
3747 MUX(1, 85, 1, N, N, N, N),
3748 MUX(1, 86, 1, N, N, N, N),
3749 MUX(1, 87, 1, N, N, N, N),
3750 MUX(1, 88, 1, N, N, N, N),
3751 MUX(1, 89, 1, N, N, N, N),
3752 MUX(1, 90, 1, N, N, N, N),
3753 };
3754
3755 static struct atlas7_grp_mux sd3_grp_mux = {
3756 .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux),
3757 .pad_mux_list = sd3_grp_pad_mux,
3758 };
3759
3760 static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
3761 MUX(1, 91, 1, N, N, N, N),
3762 MUX(1, 92, 1, N, N, N, N),
3763 MUX(1, 93, 1, N, N, N, N),
3764 MUX(1, 94, 1, N, N, N, N),
3765 MUX(1, 95, 1, N, N, N, N),
3766 MUX(1, 96, 1, N, N, N, N),
3767 };
3768
3769 static struct atlas7_grp_mux sd5_grp_mux = {
3770 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
3771 .pad_mux_list = sd5_grp_pad_mux,
3772 };
3773
3774 static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
3775 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
3776 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
3777 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
3778 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
3779 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
3780 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
3781 };
3782
3783 static struct atlas7_grp_mux sd6_grp0_mux = {
3784 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
3785 .pad_mux_list = sd6_grp0_pad_mux,
3786 };
3787
3788 static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
3789 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
3790 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
3791 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
3792 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
3793 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
3794 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
3795 };
3796
3797 static struct atlas7_grp_mux sd6_grp1_mux = {
3798 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
3799 .pad_mux_list = sd6_grp1_pad_mux,
3800 };
3801
3802 static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
3803 MUX(0, 4, 2, N, N, N, N),
3804 };
3805
3806 static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
3807 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
3808 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
3809 };
3810
3811 static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
3812 MUX(0, 12, 1, N, N, N, N),
3813 MUX(0, 13, 1, N, N, N, N),
3814 MUX(0, 14, 1, N, N, N, N),
3815 MUX(0, 15, 1, N, N, N, N),
3816 MUX(0, 16, 1, N, N, N, N),
3817 MUX(0, 17, 1, N, N, N, N),
3818 };
3819
3820 static struct atlas7_grp_mux sp0_qspi_grp_mux = {
3821 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
3822 .pad_mux_list = sp0_qspi_grp_pad_mux,
3823 };
3824
3825 static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
3826 MUX(1, 19, 1, N, N, N, N),
3827 MUX(1, 20, 1, N, N, N, N),
3828 MUX(1, 21, 1, N, N, N, N),
3829 MUX(1, 18, 1, N, N, N, N),
3830 };
3831
3832 static struct atlas7_grp_mux sp1_spi_grp_mux = {
3833 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
3834 .pad_mux_list = sp1_spi_grp_pad_mux,
3835 };
3836
3837 static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
3838 MUX(1, 53, 5, N, N, N, N),
3839 MUX(1, 56, 5, N, N, N, N),
3840 MUX(1, 57, 5, N, N, N, N),
3841 MUX(1, 58, 5, N, N, N, N),
3842 MUX(1, 59, 5, N, N, N, N),
3843 MUX(1, 60, 5, N, N, N, N),
3844 MUX(1, 61, 5, N, N, N, N),
3845 MUX(1, 62, 5, N, N, N, N),
3846 MUX(1, 63, 5, N, N, N, N),
3847 MUX(1, 64, 5, N, N, N, N),
3848 MUX(1, 65, 5, N, N, N, N),
3849 MUX(1, 66, 5, N, N, N, N),
3850 MUX(1, 67, 5, N, N, N, N),
3851 MUX(1, 68, 5, N, N, N, N),
3852 MUX(1, 69, 5, N, N, N, N),
3853 MUX(1, 70, 5, N, N, N, N),
3854 MUX(1, 71, 5, N, N, N, N),
3855 MUX(1, 72, 5, N, N, N, N),
3856 };
3857
3858 static struct atlas7_grp_mux tpiu_trace_grp_mux = {
3859 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
3860 .pad_mux_list = tpiu_trace_grp_pad_mux,
3861 };
3862
3863 static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
3864 MUX(1, 121, 4, N, N, N, N),
3865 MUX(1, 120, 4, N, N, N, N),
3866 MUX(1, 134, 1, N, N, N, N),
3867 MUX(1, 133, 1, N, N, N, N),
3868 };
3869
3870 static struct atlas7_grp_mux uart0_grp_mux = {
3871 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
3872 .pad_mux_list = uart0_grp_pad_mux,
3873 };
3874
3875 static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
3876 MUX(1, 134, 1, N, N, N, N),
3877 MUX(1, 133, 1, N, N, N, N),
3878 };
3879
3880 static struct atlas7_grp_mux uart0_nopause_grp_mux = {
3881 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
3882 .pad_mux_list = uart0_nopause_grp_pad_mux,
3883 };
3884
3885 static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
3886 MUX(1, 136, 1, N, N, N, N),
3887 MUX(1, 135, 1, N, N, N, N),
3888 };
3889
3890 static struct atlas7_grp_mux uart1_grp_mux = {
3891 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
3892 .pad_mux_list = uart1_grp_pad_mux,
3893 };
3894
3895 static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
3896 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3897 };
3898
3899 static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3900 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3901 .pad_mux_list = uart2_cts_grp0_pad_mux,
3902 };
3903
3904 static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3905 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3906 };
3907
3908 static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3909 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3910 .pad_mux_list = uart2_cts_grp1_pad_mux,
3911 };
3912
3913 static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3914 MUX(1, 131, 3, N, N, N, N),
3915 };
3916
3917 static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3918 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3919 .pad_mux_list = uart2_rts_grp0_pad_mux,
3920 };
3921
3922 static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3923 MUX(1, 161, 2, N, N, N, N),
3924 };
3925
3926 static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3927 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3928 .pad_mux_list = uart2_rts_grp1_pad_mux,
3929 };
3930
3931 static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3932 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3933 };
3934
3935 static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3936 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3937 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3938 };
3939
3940 static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3941 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3942 };
3943
3944 static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3945 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3946 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3947 };
3948
3949 static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3950 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3951 };
3952
3953 static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3954 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3955 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3956 };
3957
3958 static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
3959 MUX(0, 10, 2, N, N, N, N),
3960 };
3961
3962 static struct atlas7_grp_mux uart2_txd_grp0_mux = {
3963 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
3964 .pad_mux_list = uart2_txd_grp0_pad_mux,
3965 };
3966
3967 static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3968 MUX(1, 159, 2, N, N, N, N),
3969 };
3970
3971 static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3972 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3973 .pad_mux_list = uart2_txd_grp1_pad_mux,
3974 };
3975
3976 static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3977 MUX(1, 129, 3, N, N, N, N),
3978 };
3979
3980 static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3981 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3982 .pad_mux_list = uart2_txd_grp2_pad_mux,
3983 };
3984
3985 static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
3986 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
3987 };
3988
3989 static struct atlas7_grp_mux uart3_cts_grp0_mux = {
3990 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
3991 .pad_mux_list = uart3_cts_grp0_pad_mux,
3992 };
3993
3994 static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3995 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3996 };
3997
3998 static struct atlas7_grp_mux uart3_cts_grp1_mux = {
3999 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
4000 .pad_mux_list = uart3_cts_grp1_pad_mux,
4001 };
4002
4003 static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
4004 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4005 };
4006
4007 static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4008 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4009 .pad_mux_list = uart3_cts_grp2_pad_mux,
4010 };
4011
4012 static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4013 MUX(1, 126, 2, N, N, N, N),
4014 };
4015
4016 static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4017 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4018 .pad_mux_list = uart3_rts_grp0_pad_mux,
4019 };
4020
4021 static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4022 MUX(1, 109, 4, N, N, N, N),
4023 };
4024
4025 static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4026 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4027 .pad_mux_list = uart3_rts_grp1_pad_mux,
4028 };
4029
4030 static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
4031 MUX(1, 139, 2, N, N, N, N),
4032 };
4033
4034 static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4035 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4036 .pad_mux_list = uart3_rts_grp2_pad_mux,
4037 };
4038
4039 static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
4040 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
4041 };
4042
4043 static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
4044 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
4045 .pad_mux_list = uart3_rxd_grp0_pad_mux,
4046 };
4047
4048 static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
4049 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
4050 };
4051
4052 static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
4053 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
4054 .pad_mux_list = uart3_rxd_grp1_pad_mux,
4055 };
4056
4057 static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
4058 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4059 };
4060
4061 static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4062 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4063 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4064 };
4065
4066 static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
4067 MUX(1, 137, 1, N, N, N, N),
4068 };
4069
4070 static struct atlas7_grp_mux uart3_txd_grp0_mux = {
4071 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
4072 .pad_mux_list = uart3_txd_grp0_pad_mux,
4073 };
4074
4075 static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
4076 MUX(1, 83, 2, N, N, N, N),
4077 };
4078
4079 static struct atlas7_grp_mux uart3_txd_grp1_mux = {
4080 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
4081 .pad_mux_list = uart3_txd_grp1_pad_mux,
4082 };
4083
4084 static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
4085 MUX(1, 161, 3, N, N, N, N),
4086 };
4087
4088 static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4089 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4090 .pad_mux_list = uart3_txd_grp2_pad_mux,
4091 };
4092
4093 static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
4094 MUX(1, 140, 1, N, N, N, N),
4095 MUX(1, 139, 1, N, N, N, N),
4096 };
4097
4098 static struct atlas7_grp_mux uart4_basic_grp_mux = {
4099 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
4100 .pad_mux_list = uart4_basic_grp_pad_mux,
4101 };
4102
4103 static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4104 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4105 };
4106
4107 static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4108 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4109 .pad_mux_list = uart4_cts_grp0_pad_mux,
4110 };
4111
4112 static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
4113 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
4114 };
4115
4116 static struct atlas7_grp_mux uart4_cts_grp1_mux = {
4117 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
4118 .pad_mux_list = uart4_cts_grp1_pad_mux,
4119 };
4120
4121 static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
4122 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
4123 };
4124
4125 static struct atlas7_grp_mux uart4_cts_grp2_mux = {
4126 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
4127 .pad_mux_list = uart4_cts_grp2_pad_mux,
4128 };
4129
4130 static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
4131 MUX(1, 123, 4, N, N, N, N),
4132 };
4133
4134 static struct atlas7_grp_mux uart4_rts_grp0_mux = {
4135 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
4136 .pad_mux_list = uart4_rts_grp0_pad_mux,
4137 };
4138
4139 static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4140 MUX(1, 99, 4, N, N, N, N),
4141 };
4142
4143 static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4144 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4145 .pad_mux_list = uart4_rts_grp1_pad_mux,
4146 };
4147
4148 static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4149 MUX(1, 116, 2, N, N, N, N),
4150 };
4151
4152 static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4153 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4154 .pad_mux_list = uart4_rts_grp2_pad_mux,
4155 };
4156
4157 static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
4158 MUX(1, 51, 2, N, N, N, N),
4159 };
4160
4161 static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
4162 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
4163 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4164 };
4165
4166 static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4167 MUX(1, 162, 7, N, N, N, N),
4168 };
4169
4170 static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4171 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4172 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4173 };
4174
4175 static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
4176 MUX(1, 134, 2, N, N, N, N),
4177 };
4178
4179 static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
4180 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
4181 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4182 };
4183
4184 static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4185 MUX(1, 163, 2, N, N, N, N),
4186 };
4187
4188 static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4189 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4190 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
4191 };
4192
4193 static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
4194 MUX(1, 57, 6, N, N, N, N),
4195 MUX(1, 58, 6, N, N, N, N),
4196 MUX(1, 59, 6, N, N, N, N),
4197 MUX(1, 60, 6, N, N, N, N),
4198 MUX(1, 61, 6, N, N, N, N),
4199 MUX(1, 62, 6, N, N, N, N),
4200 MUX(1, 63, 6, N, N, N, N),
4201 MUX(1, 64, 6, N, N, N, N),
4202 MUX(1, 65, 6, N, N, N, N),
4203 MUX(1, 66, 6, N, N, N, N),
4204 MUX(1, 67, 6, N, N, N, N),
4205 MUX(1, 68, 6, N, N, N, N),
4206 MUX(1, 69, 6, N, N, N, N),
4207 MUX(1, 70, 6, N, N, N, N),
4208 MUX(1, 71, 6, N, N, N, N),
4209 MUX(1, 72, 6, N, N, N, N),
4210 MUX(1, 53, 6, N, N, N, N),
4211 MUX(1, 54, 6, N, N, N, N),
4212 MUX(1, 55, 6, N, N, N, N),
4213 MUX(1, 56, 6, N, N, N, N),
4214 MUX(1, 85, 6, N, N, N, N),
4215 MUX(1, 86, 6, N, N, N, N),
4216 MUX(1, 87, 6, N, N, N, N),
4217 MUX(1, 88, 6, N, N, N, N),
4218 MUX(1, 89, 6, N, N, N, N),
4219 MUX(1, 90, 6, N, N, N, N),
4220 MUX(1, 91, 6, N, N, N, N),
4221 MUX(1, 92, 6, N, N, N, N),
4222 MUX(1, 93, 6, N, N, N, N),
4223 MUX(1, 94, 6, N, N, N, N),
4224 MUX(1, 95, 6, N, N, N, N),
4225 MUX(1, 96, 6, N, N, N, N),
4226 };
4227
4228 static struct atlas7_grp_mux visbus_dout_grp_mux = {
4229 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
4230 .pad_mux_list = visbus_dout_grp_pad_mux,
4231 };
4232
4233 static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
4234 MUX(1, 74, 1, N, N, N, N),
4235 MUX(1, 75, 1, N, N, N, N),
4236 MUX(1, 76, 1, N, N, N, N),
4237 MUX(1, 77, 1, N, N, N, N),
4238 MUX(1, 78, 1, N, N, N, N),
4239 MUX(1, 79, 1, N, N, N, N),
4240 MUX(1, 80, 1, N, N, N, N),
4241 MUX(1, 81, 1, N, N, N, N),
4242 MUX(1, 82, 1, N, N, N, N),
4243 MUX(1, 83, 1, N, N, N, N),
4244 MUX(1, 84, 1, N, N, N, N),
4245 MUX(1, 103, 2, N, N, N, N),
4246 MUX(1, 104, 2, N, N, N, N),
4247 MUX(1, 105, 2, N, N, N, N),
4248 MUX(1, 106, 2, N, N, N, N),
4249 MUX(1, 107, 2, N, N, N, N),
4250 MUX(1, 102, 2, N, N, N, N),
4251 MUX(1, 97, 2, N, N, N, N),
4252 MUX(1, 98, 2, N, N, N, N),
4253 };
4254
4255 static struct atlas7_grp_mux vi_vip1_grp_mux = {
4256 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
4257 .pad_mux_list = vi_vip1_grp_pad_mux,
4258 };
4259
4260 static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
4261 MUX(1, 74, 1, N, N, N, N),
4262 MUX(1, 75, 1, N, N, N, N),
4263 MUX(1, 76, 1, N, N, N, N),
4264 MUX(1, 77, 1, N, N, N, N),
4265 MUX(1, 78, 1, N, N, N, N),
4266 MUX(1, 79, 1, N, N, N, N),
4267 MUX(1, 80, 1, N, N, N, N),
4268 MUX(1, 81, 1, N, N, N, N),
4269 MUX(1, 82, 1, N, N, N, N),
4270 MUX(1, 83, 1, N, N, N, N),
4271 MUX(1, 84, 1, N, N, N, N),
4272 MUX(1, 108, 2, N, N, N, N),
4273 MUX(1, 103, 2, N, N, N, N),
4274 MUX(1, 104, 2, N, N, N, N),
4275 MUX(1, 105, 2, N, N, N, N),
4276 MUX(1, 106, 2, N, N, N, N),
4277 MUX(1, 107, 2, N, N, N, N),
4278 MUX(1, 102, 2, N, N, N, N),
4279 MUX(1, 97, 2, N, N, N, N),
4280 MUX(1, 98, 2, N, N, N, N),
4281 MUX(1, 99, 2, N, N, N, N),
4282 MUX(1, 100, 2, N, N, N, N),
4283 };
4284
4285 static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
4286 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
4287 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
4288 };
4289
4290 static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
4291 MUX(1, 74, 1, N, N, N, N),
4292 MUX(1, 75, 1, N, N, N, N),
4293 MUX(1, 76, 1, N, N, N, N),
4294 MUX(1, 77, 1, N, N, N, N),
4295 MUX(1, 78, 1, N, N, N, N),
4296 MUX(1, 79, 1, N, N, N, N),
4297 MUX(1, 80, 1, N, N, N, N),
4298 MUX(1, 81, 1, N, N, N, N),
4299 };
4300
4301 static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
4302 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
4303 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
4304 };
4305
4306 static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
4307 MUX(1, 82, 1, N, N, N, N),
4308 MUX(1, 83, 1, N, N, N, N),
4309 MUX(1, 84, 1, N, N, N, N),
4310 MUX(1, 108, 2, N, N, N, N),
4311 MUX(1, 103, 2, N, N, N, N),
4312 MUX(1, 104, 2, N, N, N, N),
4313 MUX(1, 105, 2, N, N, N, N),
4314 MUX(1, 106, 2, N, N, N, N),
4315 };
4316
4317 static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
4318 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
4319 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
4320 };
4321
4322 static struct atlas7_pmx_func atlas7_pmx_functions[] = {
4323 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
4324 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
4325 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
4326 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
4327 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
4328 FUNCTION("jtag_uart_nand_gpio",
4329 jtag_uart_nand_gpio_grp,
4330 &jtag_uart_nand_gpio_grp_mux),
4331 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
4332 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4333 FUNCTION("audio_digmic_m0",
4334 audio_digmic_grp0,
4335 &audio_digmic_grp0_mux),
4336 FUNCTION("audio_digmic_m1",
4337 audio_digmic_grp1,
4338 &audio_digmic_grp1_mux),
4339 FUNCTION("audio_digmic_m2",
4340 audio_digmic_grp2,
4341 &audio_digmic_grp2_mux),
4342 FUNCTION("audio_func_dbg",
4343 audio_func_dbg_grp,
4344 &audio_func_dbg_grp_mux),
4345 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
4346 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
4347 FUNCTION("audio_i2s_extclk",
4348 audio_i2s_extclk_grp,
4349 &audio_i2s_extclk_grp_mux),
4350 FUNCTION("audio_spdif_out_m0",
4351 audio_spdif_out_grp0,
4352 &audio_spdif_out_grp0_mux),
4353 FUNCTION("audio_spdif_out_m1",
4354 audio_spdif_out_grp1,
4355 &audio_spdif_out_grp1_mux),
4356 FUNCTION("audio_spdif_out_m2",
4357 audio_spdif_out_grp2,
4358 &audio_spdif_out_grp2_mux),
4359 FUNCTION("audio_uart0_basic",
4360 audio_uart0_basic_grp,
4361 &audio_uart0_basic_grp_mux),
4362 FUNCTION("audio_uart0_urfs_m0",
4363 audio_uart0_urfs_grp0,
4364 &audio_uart0_urfs_grp0_mux),
4365 FUNCTION("audio_uart0_urfs_m1",
4366 audio_uart0_urfs_grp1,
4367 &audio_uart0_urfs_grp1_mux),
4368 FUNCTION("audio_uart0_urfs_m2",
4369 audio_uart0_urfs_grp2,
4370 &audio_uart0_urfs_grp2_mux),
4371 FUNCTION("audio_uart0_urfs_m3",
4372 audio_uart0_urfs_grp3,
4373 &audio_uart0_urfs_grp3_mux),
4374 FUNCTION("audio_uart1_basic",
4375 audio_uart1_basic_grp,
4376 &audio_uart1_basic_grp_mux),
4377 FUNCTION("audio_uart1_urfs_m0",
4378 audio_uart1_urfs_grp0,
4379 &audio_uart1_urfs_grp0_mux),
4380 FUNCTION("audio_uart1_urfs_m1",
4381 audio_uart1_urfs_grp1,
4382 &audio_uart1_urfs_grp1_mux),
4383 FUNCTION("audio_uart1_urfs_m2",
4384 audio_uart1_urfs_grp2,
4385 &audio_uart1_urfs_grp2_mux),
4386 FUNCTION("audio_uart2_urfs_m0",
4387 audio_uart2_urfs_grp0,
4388 &audio_uart2_urfs_grp0_mux),
4389 FUNCTION("audio_uart2_urfs_m1",
4390 audio_uart2_urfs_grp1,
4391 &audio_uart2_urfs_grp1_mux),
4392 FUNCTION("audio_uart2_urfs_m2",
4393 audio_uart2_urfs_grp2,
4394 &audio_uart2_urfs_grp2_mux),
4395 FUNCTION("audio_uart2_urxd_m0",
4396 audio_uart2_urxd_grp0,
4397 &audio_uart2_urxd_grp0_mux),
4398 FUNCTION("audio_uart2_urxd_m1",
4399 audio_uart2_urxd_grp1,
4400 &audio_uart2_urxd_grp1_mux),
4401 FUNCTION("audio_uart2_urxd_m2",
4402 audio_uart2_urxd_grp2,
4403 &audio_uart2_urxd_grp2_mux),
4404 FUNCTION("audio_uart2_usclk_m0",
4405 audio_uart2_usclk_grp0,
4406 &audio_uart2_usclk_grp0_mux),
4407 FUNCTION("audio_uart2_usclk_m1",
4408 audio_uart2_usclk_grp1,
4409 &audio_uart2_usclk_grp1_mux),
4410 FUNCTION("audio_uart2_usclk_m2",
4411 audio_uart2_usclk_grp2,
4412 &audio_uart2_usclk_grp2_mux),
4413 FUNCTION("audio_uart2_utfs_m0",
4414 audio_uart2_utfs_grp0,
4415 &audio_uart2_utfs_grp0_mux),
4416 FUNCTION("audio_uart2_utfs_m1",
4417 audio_uart2_utfs_grp1,
4418 &audio_uart2_utfs_grp1_mux),
4419 FUNCTION("audio_uart2_utfs_m2",
4420 audio_uart2_utfs_grp2,
4421 &audio_uart2_utfs_grp2_mux),
4422 FUNCTION("audio_uart2_utxd_m0",
4423 audio_uart2_utxd_grp0,
4424 &audio_uart2_utxd_grp0_mux),
4425 FUNCTION("audio_uart2_utxd_m1",
4426 audio_uart2_utxd_grp1,
4427 &audio_uart2_utxd_grp1_mux),
4428 FUNCTION("audio_uart2_utxd_m2",
4429 audio_uart2_utxd_grp2,
4430 &audio_uart2_utxd_grp2_mux),
4431 FUNCTION("c_can_trnsvr_en_m0",
4432 c_can_trnsvr_en_grp0,
4433 &c_can_trnsvr_en_grp0_mux),
4434 FUNCTION("c_can_trnsvr_en_m1",
4435 c_can_trnsvr_en_grp1,
4436 &c_can_trnsvr_en_grp1_mux),
4437 FUNCTION("c_can_trnsvr_intr",
4438 c_can_trnsvr_intr_grp,
4439 &c_can_trnsvr_intr_grp_mux),
4440 FUNCTION("c_can_trnsvr_stb_n",
4441 c_can_trnsvr_stb_n_grp,
4442 &c_can_trnsvr_stb_n_grp_mux),
4443 FUNCTION("c0_can_rxd_trnsv0",
4444 c0_can_rxd_trnsv0_grp,
4445 &c0_can_rxd_trnsv0_grp_mux),
4446 FUNCTION("c0_can_rxd_trnsv1",
4447 c0_can_rxd_trnsv1_grp,
4448 &c0_can_rxd_trnsv1_grp_mux),
4449 FUNCTION("c0_can_txd_trnsv0",
4450 c0_can_txd_trnsv0_grp,
4451 &c0_can_txd_trnsv0_grp_mux),
4452 FUNCTION("c0_can_txd_trnsv1",
4453 c0_can_txd_trnsv1_grp,
4454 &c0_can_txd_trnsv1_grp_mux),
4455 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4456 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4457 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4458 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4459 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4460 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4461 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4462 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
4463 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
4464 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
4465 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
4466 FUNCTION("ca_curator_lpc",
4467 ca_curator_lpc_grp,
4468 &ca_curator_lpc_grp_mux),
4469 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
4470 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
4471 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
4472 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
4473 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
4474 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
4475 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
4476 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
4477 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
4478 FUNCTION("gn_gnss_uart_nopause",
4479 gn_gnss_uart_nopause_grp,
4480 &gn_gnss_uart_nopause_grp_mux),
4481 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
4482 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
4483 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
4484 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
4485 FUNCTION("cvbs_dbg_test_m0",
4486 cvbs_dbg_test_grp0,
4487 &cvbs_dbg_test_grp0_mux),
4488 FUNCTION("cvbs_dbg_test_m1",
4489 cvbs_dbg_test_grp1,
4490 &cvbs_dbg_test_grp1_mux),
4491 FUNCTION("cvbs_dbg_test_m2",
4492 cvbs_dbg_test_grp2,
4493 &cvbs_dbg_test_grp2_mux),
4494 FUNCTION("cvbs_dbg_test_m3",
4495 cvbs_dbg_test_grp3,
4496 &cvbs_dbg_test_grp3_mux),
4497 FUNCTION("cvbs_dbg_test_m4",
4498 cvbs_dbg_test_grp4,
4499 &cvbs_dbg_test_grp4_mux),
4500 FUNCTION("cvbs_dbg_test_m5",
4501 cvbs_dbg_test_grp5,
4502 &cvbs_dbg_test_grp5_mux),
4503 FUNCTION("cvbs_dbg_test_m6",
4504 cvbs_dbg_test_grp6,
4505 &cvbs_dbg_test_grp6_mux),
4506 FUNCTION("cvbs_dbg_test_m7",
4507 cvbs_dbg_test_grp7,
4508 &cvbs_dbg_test_grp7_mux),
4509 FUNCTION("cvbs_dbg_test_m8",
4510 cvbs_dbg_test_grp8,
4511 &cvbs_dbg_test_grp8_mux),
4512 FUNCTION("cvbs_dbg_test_m9",
4513 cvbs_dbg_test_grp9,
4514 &cvbs_dbg_test_grp9_mux),
4515 FUNCTION("cvbs_dbg_test_m10",
4516 cvbs_dbg_test_grp10,
4517 &cvbs_dbg_test_grp10_mux),
4518 FUNCTION("cvbs_dbg_test_m11",
4519 cvbs_dbg_test_grp11,
4520 &cvbs_dbg_test_grp11_mux),
4521 FUNCTION("cvbs_dbg_test_m12",
4522 cvbs_dbg_test_grp12,
4523 &cvbs_dbg_test_grp12_mux),
4524 FUNCTION("cvbs_dbg_test_m13",
4525 cvbs_dbg_test_grp13,
4526 &cvbs_dbg_test_grp13_mux),
4527 FUNCTION("cvbs_dbg_test_m14",
4528 cvbs_dbg_test_grp14,
4529 &cvbs_dbg_test_grp14_mux),
4530 FUNCTION("cvbs_dbg_test_m15",
4531 cvbs_dbg_test_grp15,
4532 &cvbs_dbg_test_grp15_mux),
4533 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
4534 FUNCTION("gn_gnss_sw_status",
4535 gn_gnss_sw_status_grp,
4536 &gn_gnss_sw_status_grp_mux),
4537 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
4538 FUNCTION("gn_gnss_irq1_m0",
4539 gn_gnss_irq1_grp0,
4540 &gn_gnss_irq1_grp0_mux),
4541 FUNCTION("gn_gnss_irq2_m0",
4542 gn_gnss_irq2_grp0,
4543 &gn_gnss_irq2_grp0_mux),
4544 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
4545 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
4546 FUNCTION("gn_io_gnsssys_sw_cfg",
4547 gn_io_gnsssys_sw_cfg_grp,
4548 &gn_io_gnsssys_sw_cfg_grp_mux),
4549 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
4550 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
4551 FUNCTION("gn_trg_shutdown_m0",
4552 gn_trg_shutdown_grp0,
4553 &gn_trg_shutdown_grp0_mux),
4554 FUNCTION("gn_trg_shutdown_m1",
4555 gn_trg_shutdown_grp1,
4556 &gn_trg_shutdown_grp1_mux),
4557 FUNCTION("gn_trg_shutdown_m2",
4558 gn_trg_shutdown_grp2,
4559 &gn_trg_shutdown_grp2_mux),
4560 FUNCTION("gn_trg_shutdown_m3",
4561 gn_trg_shutdown_grp3,
4562 &gn_trg_shutdown_grp3_mux),
4563 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
4564 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
4565 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4566 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4567 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4568 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4569 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4570 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4571 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4572 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4573 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4574 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4575 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4576 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4577 FUNCTION("jtag_jt_dbg_nsrst",
4578 jtag_jt_dbg_nsrst_grp,
4579 &jtag_jt_dbg_nsrst_grp_mux),
4580 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4581 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4582 FUNCTION("jtag_swdiotms_m0",
4583 jtag_swdiotms_grp0,
4584 &jtag_swdiotms_grp0_mux),
4585 FUNCTION("jtag_swdiotms_m1",
4586 jtag_swdiotms_grp1,
4587 &jtag_swdiotms_grp1_mux),
4588 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4589 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4590 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4591 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4592 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4593 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
4594 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
4595 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
4596 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
4597 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
4598 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
4599 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
4600 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
4601 FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux),
4602 FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux),
4603 FUNCTION("ps", ps_grp, &ps_grp_mux),
4604 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
4605 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
4606 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
4607 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
4608 FUNCTION("pwc_lowbatt_b_m0",
4609 pwc_lowbatt_b_grp0,
4610 &pwc_lowbatt_b_grp0_mux),
4611 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
4612 FUNCTION("pwc_on_key_b_m0",
4613 pwc_on_key_b_grp0,
4614 &pwc_on_key_b_grp0_mux),
4615 FUNCTION("pwc_wakeup_src0",
4616 pwc_wakeup_src0_grp,
4617 &pwc_wakeup_src0_grp_mux),
4618 FUNCTION("pwc_wakeup_src1",
4619 pwc_wakeup_src1_grp,
4620 &pwc_wakeup_src1_grp_mux),
4621 FUNCTION("pwc_wakeup_src2",
4622 pwc_wakeup_src2_grp,
4623 &pwc_wakeup_src2_grp_mux),
4624 FUNCTION("pwc_wakeup_src3",
4625 pwc_wakeup_src3_grp,
4626 &pwc_wakeup_src3_grp_mux),
4627 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
4628 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
4629 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4630 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
4631 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
4632 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4633 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
4634 FUNCTION("pw_i2s01_clk_m0",
4635 pw_i2s01_clk_grp0,
4636 &pw_i2s01_clk_grp0_mux),
4637 FUNCTION("pw_i2s01_clk_m1",
4638 pw_i2s01_clk_grp1,
4639 &pw_i2s01_clk_grp1_mux),
4640 FUNCTION("pw_i2s01_clk_m2",
4641 pw_i2s01_clk_grp2,
4642 &pw_i2s01_clk_grp2_mux),
4643 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4644 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4645 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4646 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4647 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
4648 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
4649 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4650 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
4651 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
4652 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
4653 FUNCTION("pw_pwm_cpu_vol_m0",
4654 pw_pwm_cpu_vol_grp0,
4655 &pw_pwm_cpu_vol_grp0_mux),
4656 FUNCTION("pw_pwm_cpu_vol_m1",
4657 pw_pwm_cpu_vol_grp1,
4658 &pw_pwm_cpu_vol_grp1_mux),
4659 FUNCTION("pw_pwm_cpu_vol_m2",
4660 pw_pwm_cpu_vol_grp2,
4661 &pw_pwm_cpu_vol_grp2_mux),
4662 FUNCTION("pw_backlight_m0",
4663 pw_backlight_grp0,
4664 &pw_backlight_grp0_mux),
4665 FUNCTION("pw_backlight_m1",
4666 pw_backlight_grp1,
4667 &pw_backlight_grp1_mux),
4668 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
4669 FUNCTION("rg_gmac_phy_intr_n",
4670 rg_gmac_phy_intr_n_grp,
4671 &rg_gmac_phy_intr_n_grp_mux),
4672 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
4673 FUNCTION("rg_rgmii_phy_ref_clk_m0",
4674 rg_rgmii_phy_ref_clk_grp0,
4675 &rg_rgmii_phy_ref_clk_grp0_mux),
4676 FUNCTION("rg_rgmii_phy_ref_clk_m1",
4677 rg_rgmii_phy_ref_clk_grp1,
4678 &rg_rgmii_phy_ref_clk_grp1_mux),
4679 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
4680 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
4681 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
4682 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
4683 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
4684 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
4685 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4686 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4687 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4688 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
4689 FUNCTION("sd3", sd3_grp, &sd3_grp_mux),
4690 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
4691 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
4692 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
4693 FUNCTION("sp0_ext_ldo_on",
4694 sp0_ext_ldo_on_grp,
4695 &sp0_ext_ldo_on_grp_mux),
4696 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
4697 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
4698 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
4699 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
4700 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
4701 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
4702 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
4703 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
4704 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
4705 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
4706 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
4707 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
4708 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
4709 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
4710 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
4711 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
4712 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
4713 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
4714 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
4715 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
4716 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
4717 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
4718 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4719 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4720 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4721 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4722 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4723 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4724 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4725 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4726 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4727 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4728 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4729 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4730 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4731 FUNCTION("usb0_drvvbus_m0",
4732 usb0_drvvbus_grp0,
4733 &usb0_drvvbus_grp0_mux),
4734 FUNCTION("usb0_drvvbus_m1",
4735 usb0_drvvbus_grp1,
4736 &usb0_drvvbus_grp1_mux),
4737 FUNCTION("usb1_drvvbus_m0",
4738 usb1_drvvbus_grp0,
4739 &usb1_drvvbus_grp0_mux),
4740 FUNCTION("usb1_drvvbus_m1",
4741 usb1_drvvbus_grp1,
4742 &usb1_drvvbus_grp1_mux),
4743 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
4744 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
4745 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
4746 FUNCTION("vi_vip1_low8bit",
4747 vi_vip1_low8bit_grp,
4748 &vi_vip1_low8bit_grp_mux),
4749 FUNCTION("vi_vip1_high8bit",
4750 vi_vip1_high8bit_grp,
4751 &vi_vip1_high8bit_grp_mux),
4752 };
4753
4754 struct atlas7_pinctrl_data atlas7_ioc_data = {
4755 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
4756 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
4757 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
4758 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
4759 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
4760 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
4761 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
4762 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
4763 };
4764
4765 /* Simple map data structure */
4766 struct map_data {
4767 u8 idx;
4768 u8 data;
4769 };
4770
4771 /**
4772 * struct atlas7_pull_info - Atlas7 Pad pull info
4773 * @type:The type of this Pad.
4774 * @mask:The mas value of this pin's pull bits.
4775 * @v2s: The map of pull register value to pull status.
4776 * @s2v: The map of pull status to pull register value.
4777 */
4778 struct atlas7_pull_info {
4779 u8 pad_type;
4780 u8 mask;
4781 const struct map_data *v2s;
4782 const struct map_data *s2v;
4783 };
4784
4785 /* Pull Register value map to status */
4786 static const struct map_data p4we_pull_v2s[] = {
4787 { P4WE_PULL_UP, PULL_UP },
4788 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
4789 { P4WE_HIGH_Z, HIGH_Z },
4790 { P4WE_PULL_DOWN, PULL_DOWN },
4791 };
4792
4793 static const struct map_data p16st_pull_v2s[] = {
4794 { P16ST_PULL_UP, PULL_UP },
4795 { PD, PULL_UNKNOWN },
4796 { P16ST_HIGH_Z, HIGH_Z },
4797 { P16ST_PULL_DOWN, PULL_DOWN },
4798 };
4799
4800 static const struct map_data pm31_pull_v2s[] = {
4801 { PM31_PULL_DISABLED, PULL_DOWN },
4802 { PM31_PULL_ENABLED, PULL_UP },
4803 };
4804
4805 static const struct map_data pangd_pull_v2s[] = {
4806 { PANGD_PULL_UP, PULL_UP },
4807 { PD, PULL_UNKNOWN },
4808 { PANGD_HIGH_Z, HIGH_Z },
4809 { PANGD_PULL_DOWN, PULL_DOWN },
4810 };
4811
4812 /* Pull status map to register value */
4813 static const struct map_data p4we_pull_s2v[] = {
4814 { PULL_UP, P4WE_PULL_UP },
4815 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
4816 { HIGH_Z, P4WE_HIGH_Z },
4817 { PULL_DOWN, P4WE_PULL_DOWN },
4818 { PULL_DISABLE, -1 },
4819 { PULL_ENABLE, -1 },
4820 };
4821
4822 static const struct map_data p16st_pull_s2v[] = {
4823 { PULL_UP, P16ST_PULL_UP },
4824 { HIGH_HYSTERESIS, -1 },
4825 { HIGH_Z, P16ST_HIGH_Z },
4826 { PULL_DOWN, P16ST_PULL_DOWN },
4827 { PULL_DISABLE, -1 },
4828 { PULL_ENABLE, -1 },
4829 };
4830
4831 static const struct map_data pm31_pull_s2v[] = {
4832 { PULL_UP, PM31_PULL_ENABLED },
4833 { HIGH_HYSTERESIS, -1 },
4834 { HIGH_Z, -1 },
4835 { PULL_DOWN, PM31_PULL_DISABLED },
4836 { PULL_DISABLE, -1 },
4837 { PULL_ENABLE, -1 },
4838 };
4839
4840 static const struct map_data pangd_pull_s2v[] = {
4841 { PULL_UP, PANGD_PULL_UP },
4842 { HIGH_HYSTERESIS, -1 },
4843 { HIGH_Z, PANGD_HIGH_Z },
4844 { PULL_DOWN, PANGD_PULL_DOWN },
4845 { PULL_DISABLE, -1 },
4846 { PULL_ENABLE, -1 },
4847 };
4848
4849 static const struct atlas7_pull_info atlas7_pull_map[] = {
4850 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4851 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
4852 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
4853 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4854 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4855 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4856 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
4857 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
4858 };
4859
4860 /**
4861 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4862 * @ma: The Drive Strength in current value .
4863 * @ds_16st: The correspond raw value of 16st pad.
4864 * @ds_4we: The correspond raw value of 4we pad.
4865 * @ds_0204m31: The correspond raw value of 0204m31 pad.
4866 * @ds_0610m31: The correspond raw value of 0610m31 pad.
4867 */
4868 struct atlas7_ds_ma_info {
4869 u32 ma;
4870 u32 ds_16st;
4871 u32 ds_4we;
4872 u32 ds_0204m31;
4873 u32 ds_0610m31;
4874 };
4875
4876 static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
4877 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
4878 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
4879 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
4880 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
4881 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
4882 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
4883 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
4884 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
4885 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
4886 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
4887 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
4888 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
4889 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
4890 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
4891 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
4892 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
4893 };
4894
4895 /**
4896 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4897 * @type: The type of this Pad.
4898 * @mask: The mask value of this pin's pull bits.
4899 * @imval: The immediate value of drives trength register.
4900 */
4901 struct atlas7_ds_info {
4902 u8 type;
4903 u8 mask;
4904 u8 imval;
4905 u8 reserved;
4906 };
4907
4908 static const struct atlas7_ds_info atlas7_ds_map[] = {
4909 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4910 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
4911 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
4912 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4913 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4914 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4915 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
4916 { PAD_T_AD, DS_NULL, DS_NULL },
4917 };
4918
4919 static inline u32 atlas7_pin_to_bank(u32 pin)
4920 {
4921 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
4922 }
4923
4924 static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
4925 {
4926 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4927
4928 return pmx->pctl_data->funcs_cnt;
4929 }
4930
4931 static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
4932 u32 selector)
4933 {
4934 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4935
4936 return pmx->pctl_data->funcs[selector].name;
4937 }
4938
4939 static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
4940 u32 selector, const char * const **groups,
4941 u32 * const num_groups)
4942 {
4943 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
4944
4945 *groups = pmx->pctl_data->funcs[selector].groups;
4946 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
4947
4948 return 0;
4949 }
4950
4951 static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
4952 const struct atlas7_pad_mux *mux)
4953 {
4954 /* Set Input Disable to avoid input glitches
4955 *
4956 * All Input-Disable Control registers are located on IOCRTC.
4957 * So the regs bank is always 0.
4958 *
4959 */
4960 if (mux->dinput_reg && mux->dinput_val_reg) {
4961 writel(DI_MASK << mux->dinput_bit,
4962 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4963 writel(DI_DISABLE << mux->dinput_bit,
4964 pmx->regs[BANK_DS] + mux->dinput_reg);
4965
4966
4967 writel(DIV_MASK << mux->dinput_val_bit,
4968 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4969 writel(DIV_DISABLE << mux->dinput_val_bit,
4970 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4971 }
4972 }
4973
4974 static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
4975 const struct atlas7_pad_mux *mux)
4976 {
4977 /* Clear Input Disable to avoid input glitches */
4978 if (mux->dinput_reg && mux->dinput_val_reg) {
4979 writel(DI_MASK << mux->dinput_bit,
4980 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
4981 writel(DI_ENABLE << mux->dinput_bit,
4982 pmx->regs[BANK_DS] + mux->dinput_reg);
4983
4984 writel(DIV_MASK << mux->dinput_val_bit,
4985 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
4986 writel(DIV_ENABLE << mux->dinput_val_bit,
4987 pmx->regs[BANK_DS] + mux->dinput_val_reg);
4988 }
4989 }
4990
4991 static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
4992 struct atlas7_pad_config *conf,
4993 u32 bank, u32 ad_sel)
4994 {
4995 unsigned long regv;
4996
4997 /* Write to clear register to clear A/D selector */
4998 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
4999 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
5000
5001 /* Set target pad A/D selector */
5002 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5003 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
5004 writel(regv | (ad_sel << conf->ad_ctrl_bit),
5005 pmx->regs[bank] + conf->ad_ctrl_reg);
5006
5007 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5008 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5009 bank, conf->ad_ctrl_reg, regv);
5010 return 0;
5011 }
5012
5013 static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
5014 struct atlas7_pad_config *conf, u32 bank)
5015 {
5016 /* Only PAD_T_AD pins can change between Analogue&Digital */
5017 if (conf->type != PAD_T_AD)
5018 return -EINVAL;
5019
5020 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
5021 }
5022
5023 static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
5024 struct atlas7_pad_config *conf, u32 bank)
5025 {
5026 /* Other type pads are always digital */
5027 if (conf->type != PAD_T_AD)
5028 return 0;
5029
5030 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
5031 }
5032
5033 static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
5034 u32 pin, u32 func)
5035 {
5036 struct atlas7_pad_config *conf;
5037 u32 bank;
5038 int ret;
5039 unsigned long regv;
5040
5041 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
5042 pin, func);
5043
5044 /* Get this Pad's descriptor from PINCTRL */
5045 conf = &pmx->pctl_data->confs[pin];
5046 bank = atlas7_pin_to_bank(pin);
5047
5048 /* Just enable the analog function of this pad */
5049 if (FUNC_ANALOGUE == func) {
5050 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
5051 if (ret)
5052 dev_err(pmx->dev,
5053 "Convert pad#%d to analog failed, ret=%d\n",
5054 pin, ret);
5055 return ret;
5056 }
5057
5058 /* Set Pads from analog to digital */
5059 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
5060 if (ret) {
5061 dev_err(pmx->dev,
5062 "Convert pad#%d to digital failed, ret=%d\n",
5063 pin, ret);
5064 return ret;
5065 }
5066
5067 /* Write to clear register to clear current function */
5068 writel(FUNC_CLEAR_MASK << conf->mux_bit,
5069 pmx->regs[bank] + CLR_REG(conf->mux_reg));
5070
5071 /* Set target pad mux function */
5072 regv = readl(pmx->regs[bank] + conf->mux_reg);
5073 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
5074 writel(regv | (func << conf->mux_bit),
5075 pmx->regs[bank] + conf->mux_reg);
5076
5077 regv = readl(pmx->regs[bank] + conf->mux_reg);
5078 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
5079 bank, conf->mux_reg, regv);
5080
5081 return 0;
5082 }
5083
5084 static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
5085 u32 func_selector, u32 group_selector)
5086 {
5087 int idx, ret;
5088 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5089 struct atlas7_pmx_func *pmx_func;
5090 struct atlas7_pin_group *pin_grp;
5091 const struct atlas7_grp_mux *grp_mux;
5092 const struct atlas7_pad_mux *mux;
5093
5094 pmx_func = &pmx->pctl_data->funcs[func_selector];
5095 pin_grp = &pmx->pctl_data->grps[group_selector];
5096
5097 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
5098 pmx_func->name, pin_grp->name);
5099
5100 grp_mux = pmx_func->grpmux;
5101
5102 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
5103 mux = &grp_mux->pad_mux_list[idx];
5104 __atlas7_pmx_pin_input_disable_set(pmx, mux);
5105 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
5106 if (ret) {
5107 dev_err(pmx->dev,
5108 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
5109 pmx_func->name, pin_grp->name,
5110 mux->pin, mux->func, ret);
5111 BUG_ON(1);
5112 }
5113 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
5114 }
5115 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
5116 pmx_func->name, pin_grp->name);
5117
5118 return 0;
5119 }
5120
5121 static u32 convert_current_to_drive_strength(u32 type, u32 ma)
5122 {
5123 int idx;
5124
5125 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
5126 if (atlas7_ma2ds_map[idx].ma != ma)
5127 continue;
5128
5129 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
5130 return atlas7_ma2ds_map[idx].ds_4we;
5131 else if (type == PAD_T_16ST)
5132 return atlas7_ma2ds_map[idx].ds_16st;
5133 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
5134 return atlas7_ma2ds_map[idx].ds_0204m31;
5135 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
5136 return atlas7_ma2ds_map[idx].ds_0610m31;
5137 }
5138
5139 return DS_NULL;
5140 }
5141
5142 static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
5143 u32 pin, u32 sel)
5144 {
5145 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5146 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5147 const struct atlas7_pull_info *pull_info;
5148 u32 bank;
5149 unsigned long regv;
5150 void __iomem *pull_sel_reg;
5151
5152 bank = atlas7_pin_to_bank(pin);
5153 pull_info = &atlas7_pull_map[conf->type];
5154 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
5155
5156 /* Retrieve correspond register value from table by sel */
5157 regv = pull_info->s2v[sel].data & pull_info->mask;
5158
5159 /* Clear & Set new value to pull register */
5160 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
5161 writel(regv << conf->pupd_bit, pull_sel_reg);
5162
5163 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
5164 pin, sel);
5165 return 0;
5166 }
5167
5168 static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5169 u32 pin, u32 sel)
5170 {
5171 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5172 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5173 const struct atlas7_ds_info *ds_info;
5174 u32 bank;
5175 void __iomem *ds_sel_reg;
5176
5177 ds_info = &atlas7_ds_map[conf->type];
5178 if (sel & (~(ds_info->mask)))
5179 goto unsupport;
5180
5181 bank = atlas7_pin_to_bank(pin);
5182 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
5183
5184 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
5185 writel(sel << conf->drvstr_bit, ds_sel_reg);
5186
5187 return 0;
5188
5189 unsupport:
5190 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
5191 pin, conf->type, sel);
5192 return -ENOTSUPP;
5193 }
5194
5195 static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
5196 u32 pin, u32 ma)
5197 {
5198 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5199 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
5200 u32 type = conf->type;
5201 u32 sel;
5202 int ret;
5203
5204 sel = convert_current_to_drive_strength(conf->type, ma);
5205 if (DS_NULL == sel) {
5206 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
5207 pin, type, ma);
5208 return -ENOTSUPP;
5209 }
5210
5211 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
5212 pin, sel);
5213 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
5214 pin, sel, ma, ret?"FAILED":"OK");
5215 return ret;
5216 }
5217
5218 static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
5219 struct pinctrl_gpio_range *range, u32 pin)
5220 {
5221 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5222 u32 idx;
5223
5224 dev_dbg(pmx->dev,
5225 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
5226 for (idx = 0; idx < range->npins; idx++) {
5227 if (pin == range->pins[idx])
5228 break;
5229 }
5230
5231 if (idx >= range->npins) {
5232 dev_err(pmx->dev,
5233 "The pin#%d could not be requested as GPIO!!\n",
5234 pin);
5235 return -EPERM;
5236 }
5237
5238 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
5239
5240 return 0;
5241 }
5242
5243 static struct pinmux_ops atlas7_pinmux_ops = {
5244 .get_functions_count = atlas7_pmx_get_funcs_count,
5245 .get_function_name = atlas7_pmx_get_func_name,
5246 .get_function_groups = atlas7_pmx_get_func_groups,
5247 .set_mux = atlas7_pmx_set_mux,
5248 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
5249 };
5250
5251 static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
5252 {
5253 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5254
5255 return pmx->pctl_data->grps_cnt;
5256 }
5257
5258 static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
5259 u32 group)
5260 {
5261 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5262
5263 return pmx->pctl_data->grps[group].name;
5264 }
5265
5266 static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
5267 u32 group, const u32 **pins, u32 *num_pins)
5268 {
5269 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
5270
5271 *num_pins = pmx->pctl_data->grps[group].num_pins;
5272 *pins = pmx->pctl_data->grps[group].pins;
5273
5274 return 0;
5275 }
5276
5277 static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
5278 struct device_node *np_config,
5279 struct pinctrl_map **map,
5280 u32 *num_maps)
5281 {
5282 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
5283 num_maps, PIN_MAP_TYPE_INVALID);
5284 }
5285
5286 static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
5287 struct pinctrl_map *map, u32 num_maps)
5288 {
5289 kfree(map);
5290 }
5291
5292 static const struct pinctrl_ops atlas7_pinctrl_ops = {
5293 .get_groups_count = atlas7_pinctrl_get_groups_count,
5294 .get_group_name = atlas7_pinctrl_get_group_name,
5295 .get_group_pins = atlas7_pinctrl_get_group_pins,
5296 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
5297 .dt_free_map = atlas7_pinctrl_dt_free_map,
5298 };
5299
5300 static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
5301 unsigned pin, unsigned long *configs,
5302 unsigned num_configs)
5303 {
5304 u16 param, arg;
5305 int idx, err;
5306
5307 for (idx = 0; idx < num_configs; idx++) {
5308 param = pinconf_to_config_param(configs[idx]);
5309 arg = pinconf_to_config_argument(configs[idx]);
5310
5311 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
5312 pin, atlas7_ioc_pads[pin].name, param, arg);
5313 switch (param) {
5314 case PIN_CONFIG_BIAS_PULL_UP:
5315 err = altas7_pinctrl_set_pull_sel(pctldev,
5316 pin, PULL_UP);
5317 if (err)
5318 return err;
5319 break;
5320
5321 case PIN_CONFIG_BIAS_PULL_DOWN:
5322 err = altas7_pinctrl_set_pull_sel(pctldev,
5323 pin, PULL_DOWN);
5324 if (err)
5325 return err;
5326 break;
5327
5328 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
5329 err = altas7_pinctrl_set_pull_sel(pctldev,
5330 pin, HIGH_HYSTERESIS);
5331 if (err)
5332 return err;
5333 break;
5334 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
5335 err = altas7_pinctrl_set_pull_sel(pctldev,
5336 pin, HIGH_Z);
5337 if (err)
5338 return err;
5339 break;
5340
5341 case PIN_CONFIG_DRIVE_STRENGTH:
5342 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
5343 pin, arg);
5344 if (err)
5345 return err;
5346 break;
5347 default:
5348 return -ENOTSUPP;
5349 }
5350 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
5351 pin, atlas7_ioc_pads[pin].name, param, arg);
5352 }
5353
5354 return 0;
5355 }
5356
5357 static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
5358 unsigned group, unsigned long *configs,
5359 unsigned num_configs)
5360 {
5361 const unsigned *pins;
5362 unsigned npins;
5363 int i, ret;
5364
5365 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
5366 if (ret)
5367 return ret;
5368 for (i = 0; i < npins; i++) {
5369 if (atlas7_pin_config_set(pctldev, pins[i],
5370 configs, num_configs))
5371 return -ENOTSUPP;
5372 }
5373 return 0;
5374 }
5375
5376 static const struct pinconf_ops atlas7_pinconf_ops = {
5377 .pin_config_set = atlas7_pin_config_set,
5378 .pin_config_group_set = atlas7_pin_config_group_set,
5379 .is_generic = true,
5380 };
5381
5382 static int atlas7_pinmux_probe(struct platform_device *pdev)
5383 {
5384 int ret, idx;
5385 struct atlas7_pmx *pmx;
5386 struct device_node *np = pdev->dev.of_node;
5387 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
5388
5389 /* Create state holders etc for this driver */
5390 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
5391 if (!pmx)
5392 return -ENOMEM;
5393
5394 pmx->dev = &pdev->dev;
5395
5396 pmx->pctl_data = &atlas7_ioc_data;
5397 pmx->pctl_desc.name = "pinctrl-atlas7";
5398 pmx->pctl_desc.pins = pmx->pctl_data->pads;
5399 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
5400 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
5401 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
5402 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
5403
5404 for (idx = 0; idx < banks; idx++) {
5405 pmx->regs[idx] = of_iomap(np, idx);
5406 if (!pmx->regs[idx]) {
5407 dev_err(&pdev->dev,
5408 "can't map ioc bank#%d registers\n", idx);
5409 ret = -ENOMEM;
5410 goto unmap_io;
5411 }
5412 }
5413
5414 /* Now register the pin controller and all pins it handles */
5415 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
5416 if (IS_ERR(pmx->pctl)) {
5417 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
5418 ret = PTR_ERR(pmx->pctl);
5419 goto unmap_io;
5420 }
5421
5422 platform_set_drvdata(pdev, pmx);
5423
5424 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
5425
5426 return 0;
5427
5428 unmap_io:
5429 for (idx = 0; idx < banks; idx++) {
5430 if (!pmx->regs[idx])
5431 break;
5432 iounmap(pmx->regs[idx]);
5433 }
5434
5435 return ret;
5436 }
5437
5438 #ifdef CONFIG_PM_SLEEP
5439 static int atlas7_pinmux_suspend_noirq(struct device *dev)
5440 {
5441 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5442 struct atlas7_pad_status *status;
5443 struct atlas7_pad_config *conf;
5444 const struct atlas7_ds_info *ds_info;
5445 const struct atlas7_pull_info *pull_info;
5446 int idx;
5447 u32 bank;
5448 unsigned long regv;
5449
5450 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5451 /* Get this Pad's descriptor from PINCTRL */
5452 conf = &pmx->pctl_data->confs[idx];
5453 bank = atlas7_pin_to_bank(idx);
5454 status = &pmx->sleep_data[idx];
5455
5456 /* Save Function selector */
5457 regv = readl(pmx->regs[bank] + conf->mux_reg);
5458 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
5459
5460 /* Check if Pad is in Analogue selector */
5461 if (conf->ad_ctrl_reg == -1)
5462 goto save_ds_sel;
5463
5464 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
5465 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
5466 status->func = FUNC_ANALOGUE;
5467
5468 save_ds_sel:
5469 if (conf->drvstr_reg == -1)
5470 goto save_pull_sel;
5471
5472 /* Save Drive Strength selector */
5473 ds_info = &atlas7_ds_map[conf->type];
5474 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
5475 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
5476
5477 save_pull_sel:
5478 /* Save Pull selector */
5479 pull_info = &atlas7_pull_map[conf->type];
5480 regv = readl(pmx->regs[bank] + conf->pupd_reg);
5481 regv = (regv >> conf->pupd_bit) & pull_info->mask;
5482 status->pull = pull_info->v2s[regv].data;
5483 }
5484
5485 /*
5486 * Save disable input selector, this selector is not for Pin,
5487 * but for Mux function.
5488 */
5489 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5490 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
5491 IN_DISABLE_0_REG_SET + 0x8 * idx);
5492 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
5493 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5494 }
5495
5496 return 0;
5497 }
5498
5499 static int atlas7_pinmux_resume_noirq(struct device *dev)
5500 {
5501 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
5502 struct atlas7_pad_status *status;
5503 struct atlas7_pad_config *conf;
5504 int idx;
5505 u32 bank;
5506
5507 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
5508 /* Get this Pad's descriptor from PINCTRL */
5509 conf = &pmx->pctl_data->confs[idx];
5510 bank = atlas7_pin_to_bank(idx);
5511 status = &pmx->sleep_data[idx];
5512
5513 /* Restore Function selector */
5514 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
5515
5516 if (FUNC_ANALOGUE == status->func)
5517 goto restore_pull_sel;
5518
5519 /* Restore Drive Strength selector */
5520 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
5521 (u32)status->dstr & 0xff);
5522
5523 restore_pull_sel:
5524 /* Restore Pull selector */
5525 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
5526 (u32)status->pull & 0xff);
5527 }
5528
5529 /*
5530 * Restore disable input selector, this selector is not for Pin,
5531 * but for Mux function
5532 */
5533 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
5534 writel(~0, pmx->regs[BANK_DS] +
5535 IN_DISABLE_0_REG_CLR + 0x8 * idx);
5536 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
5537 IN_DISABLE_0_REG_SET + 0x8 * idx);
5538 writel(~0, pmx->regs[BANK_DS] +
5539 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
5540 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
5541 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
5542 }
5543
5544 return 0;
5545 }
5546
5547 static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
5548 .suspend_noirq = atlas7_pinmux_suspend_noirq,
5549 .resume_noirq = atlas7_pinmux_resume_noirq,
5550 .freeze_noirq = atlas7_pinmux_suspend_noirq,
5551 .restore_noirq = atlas7_pinmux_resume_noirq,
5552 };
5553 #endif
5554
5555 static const struct of_device_id atlas7_pinmux_ids[] = {
5556 { .compatible = "sirf,atlas7-ioc",},
5557 {},
5558 };
5559
5560 static struct platform_driver atlas7_pinmux_driver = {
5561 .driver = {
5562 .name = "atlas7-ioc",
5563 .of_match_table = atlas7_pinmux_ids,
5564 #ifdef CONFIG_PM_SLEEP
5565 .pm = &atlas7_pinmux_pm_ops,
5566 #endif
5567 },
5568 .probe = atlas7_pinmux_probe,
5569 };
5570
5571 static int __init atlas7_pinmux_init(void)
5572 {
5573 return platform_driver_register(&atlas7_pinmux_driver);
5574 }
5575 arch_initcall(atlas7_pinmux_init);
5576
5577
5578 /**
5579 * The Following is GPIO Code
5580 */
5581 static inline struct
5582 atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
5583 {
5584 return &a7gc->banks[GPIO_TO_BANK(gpio)];
5585 }
5586
5587 static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
5588 {
5589 struct atlas7_gpio_bank *bank;
5590 u32 ofs;
5591
5592 bank = atlas7_gpio_to_bank(a7gc, gpio);
5593 ofs = gpio - bank->gpio_offset;
5594 if (ofs >= bank->ngpio)
5595 return -ENODEV;
5596
5597 return bank->gpio_pins[ofs];
5598 }
5599
5600 static void atlas7_gpio_irq_ack(struct irq_data *d)
5601 {
5602 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5603 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
5604 struct atlas7_gpio_bank *bank;
5605 void __iomem *ctrl_reg;
5606 u32 val, pin_in_bank;
5607 unsigned long flags;
5608
5609 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5610 pin_in_bank = d->hwirq - bank->gpio_offset;
5611 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5612
5613 spin_lock_irqsave(&a7gc->lock, flags);
5614
5615 val = readl(ctrl_reg);
5616 /* clear interrupt status */
5617 writel(val, ctrl_reg);
5618
5619 spin_unlock_irqrestore(&a7gc->lock, flags);
5620 }
5621
5622 static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
5623 {
5624 struct atlas7_gpio_bank *bank;
5625 void __iomem *ctrl_reg;
5626 u32 val, pin_in_bank;
5627
5628 bank = atlas7_gpio_to_bank(a7gc, idx);
5629 pin_in_bank = idx - bank->gpio_offset;
5630 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5631
5632 val = readl(ctrl_reg);
5633 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
5634 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
5635 writel(val, ctrl_reg);
5636 }
5637
5638 static void atlas7_gpio_irq_mask(struct irq_data *d)
5639 {
5640 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5641 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
5642 unsigned long flags;
5643
5644 spin_lock_irqsave(&a7gc->lock, flags);
5645
5646 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
5647
5648 spin_unlock_irqrestore(&a7gc->lock, flags);
5649 }
5650
5651 static void atlas7_gpio_irq_unmask(struct irq_data *d)
5652 {
5653 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5654 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
5655 struct atlas7_gpio_bank *bank;
5656 void __iomem *ctrl_reg;
5657 u32 val, pin_in_bank;
5658 unsigned long flags;
5659
5660 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5661 pin_in_bank = d->hwirq - bank->gpio_offset;
5662 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5663
5664 spin_lock_irqsave(&a7gc->lock, flags);
5665
5666 val = readl(ctrl_reg);
5667 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
5668 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
5669 writel(val, ctrl_reg);
5670
5671 spin_unlock_irqrestore(&a7gc->lock, flags);
5672 }
5673
5674 static int atlas7_gpio_irq_type(struct irq_data *d,
5675 unsigned int type)
5676 {
5677 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5678 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
5679 struct atlas7_gpio_bank *bank;
5680 void __iomem *ctrl_reg;
5681 u32 val, pin_in_bank;
5682 unsigned long flags;
5683
5684 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
5685 pin_in_bank = d->hwirq - bank->gpio_offset;
5686 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5687
5688 spin_lock_irqsave(&a7gc->lock, flags);
5689
5690 val = readl(ctrl_reg);
5691 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
5692 ATLAS7_GPIO_CTL_INTR_EN_MASK);
5693
5694 switch (type) {
5695 case IRQ_TYPE_NONE:
5696 break;
5697
5698 case IRQ_TYPE_EDGE_RISING:
5699 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5700 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5701 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5702 break;
5703
5704 case IRQ_TYPE_EDGE_FALLING:
5705 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5706 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5707 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5708 break;
5709
5710 case IRQ_TYPE_EDGE_BOTH:
5711 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5712 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5713 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
5714 break;
5715
5716 case IRQ_TYPE_LEVEL_LOW:
5717 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
5718 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5719 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
5720 break;
5721
5722 case IRQ_TYPE_LEVEL_HIGH:
5723 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
5724 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
5725 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
5726 break;
5727 }
5728
5729 writel(val, ctrl_reg);
5730
5731 spin_unlock_irqrestore(&a7gc->lock, flags);
5732
5733 return 0;
5734 }
5735
5736 static struct irq_chip atlas7_gpio_irq_chip = {
5737 .name = "atlas7-gpio-irq",
5738 .irq_ack = atlas7_gpio_irq_ack,
5739 .irq_mask = atlas7_gpio_irq_mask,
5740 .irq_unmask = atlas7_gpio_irq_unmask,
5741 .irq_set_type = atlas7_gpio_irq_type,
5742 };
5743
5744 static void atlas7_gpio_handle_irq(struct irq_desc *desc)
5745 {
5746 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5747 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
5748 struct atlas7_gpio_bank *bank = NULL;
5749 u32 status, ctrl;
5750 int pin_in_bank = 0, idx;
5751 struct irq_chip *chip = irq_desc_get_chip(desc);
5752 unsigned int irq = irq_desc_get_irq(desc);
5753
5754 for (idx = 0; idx < a7gc->nbank; idx++) {
5755 bank = &a7gc->banks[idx];
5756 if (bank->irq == irq)
5757 break;
5758 }
5759 BUG_ON(idx == a7gc->nbank);
5760
5761 chained_irq_enter(chip, desc);
5762
5763 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
5764 if (!status) {
5765 pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n",
5766 __func__, gc->label, status);
5767 handle_bad_irq(desc);
5768 return;
5769 }
5770
5771 while (status) {
5772 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5773
5774 /*
5775 * Here we must check whether the corresponding GPIO's
5776 * interrupt has been enabled, otherwise just skip it
5777 */
5778 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
5779 pr_debug("%s: chip[%s] gpio:%d happens\n",
5780 __func__, gc->label,
5781 bank->gpio_offset + pin_in_bank);
5782 generic_handle_irq(
5783 irq_find_mapping(gc->irqdomain,
5784 bank->gpio_offset + pin_in_bank));
5785 }
5786
5787 if (++pin_in_bank >= bank->ngpio)
5788 break;
5789
5790 status = status >> 1;
5791 }
5792
5793 chained_irq_exit(chip, desc);
5794 }
5795
5796 static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
5797 unsigned int gpio)
5798 {
5799 struct atlas7_gpio_bank *bank;
5800 void __iomem *ctrl_reg;
5801 u32 val, pin_in_bank;
5802
5803 bank = atlas7_gpio_to_bank(a7gc, gpio);
5804 pin_in_bank = gpio - bank->gpio_offset;
5805 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5806
5807 val = readl(ctrl_reg);
5808 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
5809 writel(val, ctrl_reg);
5810 }
5811
5812 static int atlas7_gpio_request(struct gpio_chip *chip,
5813 unsigned int gpio)
5814 {
5815 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5816 int ret;
5817 unsigned long flags;
5818
5819 ret = __atlas7_gpio_to_pin(a7gc, gpio);
5820 if (ret < 0)
5821 return ret;
5822
5823 if (pinctrl_request_gpio(chip->base + gpio))
5824 return -ENODEV;
5825
5826 spin_lock_irqsave(&a7gc->lock, flags);
5827
5828 /*
5829 * default status:
5830 * set direction as input and mask irq
5831 */
5832 __atlas7_gpio_set_input(a7gc, gpio);
5833 __atlas7_gpio_irq_mask(a7gc, gpio);
5834
5835 spin_unlock_irqrestore(&a7gc->lock, flags);
5836
5837 return 0;
5838 }
5839
5840 static void atlas7_gpio_free(struct gpio_chip *chip,
5841 unsigned int gpio)
5842 {
5843 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5844 unsigned long flags;
5845
5846 spin_lock_irqsave(&a7gc->lock, flags);
5847
5848 __atlas7_gpio_irq_mask(a7gc, gpio);
5849 __atlas7_gpio_set_input(a7gc, gpio);
5850
5851 spin_unlock_irqrestore(&a7gc->lock, flags);
5852
5853 pinctrl_free_gpio(chip->base + gpio);
5854 }
5855
5856 static int atlas7_gpio_direction_input(struct gpio_chip *chip,
5857 unsigned int gpio)
5858 {
5859 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5860 unsigned long flags;
5861
5862 spin_lock_irqsave(&a7gc->lock, flags);
5863
5864 __atlas7_gpio_set_input(a7gc, gpio);
5865
5866 spin_unlock_irqrestore(&a7gc->lock, flags);
5867
5868 return 0;
5869 }
5870
5871 static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
5872 unsigned int gpio, int value)
5873 {
5874 struct atlas7_gpio_bank *bank;
5875 void __iomem *ctrl_reg;
5876 u32 out_ctrl, pin_in_bank;
5877
5878 bank = atlas7_gpio_to_bank(a7gc, gpio);
5879 pin_in_bank = gpio - bank->gpio_offset;
5880 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5881
5882 out_ctrl = readl(ctrl_reg);
5883 if (value)
5884 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5885 else
5886 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5887
5888 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
5889 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
5890 writel(out_ctrl, ctrl_reg);
5891 }
5892
5893 static int atlas7_gpio_direction_output(struct gpio_chip *chip,
5894 unsigned int gpio, int value)
5895 {
5896 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5897 unsigned long flags;
5898
5899 spin_lock_irqsave(&a7gc->lock, flags);
5900
5901 __atlas7_gpio_set_output(a7gc, gpio, value);
5902
5903 spin_unlock_irqrestore(&a7gc->lock, flags);
5904
5905 return 0;
5906 }
5907
5908 static int atlas7_gpio_get_value(struct gpio_chip *chip,
5909 unsigned int gpio)
5910 {
5911 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5912 struct atlas7_gpio_bank *bank;
5913 u32 val, pin_in_bank;
5914 unsigned long flags;
5915
5916 bank = atlas7_gpio_to_bank(a7gc, gpio);
5917 pin_in_bank = gpio - bank->gpio_offset;
5918
5919 spin_lock_irqsave(&a7gc->lock, flags);
5920
5921 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
5922
5923 spin_unlock_irqrestore(&a7gc->lock, flags);
5924
5925 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
5926 }
5927
5928 static void atlas7_gpio_set_value(struct gpio_chip *chip,
5929 unsigned int gpio, int value)
5930 {
5931 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
5932 struct atlas7_gpio_bank *bank;
5933 void __iomem *ctrl_reg;
5934 u32 ctrl, pin_in_bank;
5935 unsigned long flags;
5936
5937 bank = atlas7_gpio_to_bank(a7gc, gpio);
5938 pin_in_bank = gpio - bank->gpio_offset;
5939 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
5940
5941 spin_lock_irqsave(&a7gc->lock, flags);
5942
5943 ctrl = readl(ctrl_reg);
5944 if (value)
5945 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
5946 else
5947 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
5948 writel(ctrl, ctrl_reg);
5949
5950 spin_unlock_irqrestore(&a7gc->lock, flags);
5951 }
5952
5953 static const struct of_device_id atlas7_gpio_ids[] = {
5954 { .compatible = "sirf,atlas7-gpio", },
5955 {},
5956 };
5957
5958 static int atlas7_gpio_probe(struct platform_device *pdev)
5959 {
5960 struct device_node *np = pdev->dev.of_node;
5961 struct atlas7_gpio_chip *a7gc;
5962 struct gpio_chip *chip;
5963 u32 nbank;
5964 int ret, idx;
5965
5966 ret = of_property_read_u32(np, "gpio-banks", &nbank);
5967 if (ret) {
5968 dev_err(&pdev->dev,
5969 "Could not find GPIO bank info,ret=%d!\n",
5970 ret);
5971 return ret;
5972 }
5973
5974 /* retrieve gpio descriptor data */
5975 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
5976 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
5977 if (!a7gc)
5978 return -ENOMEM;
5979
5980 /* Get Gpio clk */
5981 a7gc->clk = of_clk_get(np, 0);
5982 if (!IS_ERR(a7gc->clk)) {
5983 ret = clk_prepare_enable(a7gc->clk);
5984 if (ret) {
5985 dev_err(&pdev->dev,
5986 "Could not enable clock!\n");
5987 return ret;
5988 }
5989 }
5990
5991 /* Get Gpio Registers */
5992 a7gc->reg = of_iomap(np, 0);
5993 if (!a7gc->reg) {
5994 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
5995 return -ENOMEM;
5996 }
5997
5998 a7gc->nbank = nbank;
5999 spin_lock_init(&a7gc->lock);
6000
6001 /* Setup GPIO Chip */
6002 chip = &a7gc->chip;
6003 chip->request = atlas7_gpio_request;
6004 chip->free = atlas7_gpio_free;
6005 chip->direction_input = atlas7_gpio_direction_input;
6006 chip->get = atlas7_gpio_get_value;
6007 chip->direction_output = atlas7_gpio_direction_output;
6008 chip->set = atlas7_gpio_set_value;
6009 chip->base = -1;
6010 /* Each chip can support 32 pins at one bank */
6011 chip->ngpio = NGPIO_OF_BANK * nbank;
6012 chip->label = kstrdup(np->name, GFP_KERNEL);
6013 chip->of_node = np;
6014 chip->of_gpio_n_cells = 2;
6015 chip->dev = &pdev->dev;
6016
6017 /* Add gpio chip to system */
6018 ret = gpiochip_add(chip);
6019 if (ret) {
6020 dev_err(&pdev->dev,
6021 "%s: error in probe function with status %d\n",
6022 np->name, ret);
6023 goto failed;
6024 }
6025
6026 /* Add gpio chip to irq subsystem */
6027 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6028 0, handle_level_irq, IRQ_TYPE_NONE);
6029 if (ret) {
6030 dev_err(&pdev->dev,
6031 "could not connect irqchip to gpiochip\n");
6032 goto failed;
6033 }
6034
6035 for (idx = 0; idx < nbank; idx++) {
6036 struct gpio_pin_range *pin_range;
6037 struct atlas7_gpio_bank *bank;
6038
6039 bank = &a7gc->banks[idx];
6040 /* Set ctrl registers' base of this bank */
6041 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
6042
6043 /* Get interrupt number from DTS */
6044 ret = of_irq_get(np, idx);
6045 if (ret == -EPROBE_DEFER) {
6046 dev_err(&pdev->dev,
6047 "Unable to find IRQ number. ret=%d\n", ret);
6048 goto failed;
6049 }
6050 bank->irq = ret;
6051
6052 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6053 bank->irq, atlas7_gpio_handle_irq);
6054
6055 /* Records gpio_pin_range to a7gc */
6056 list_for_each_entry(pin_range, &chip->pin_ranges, node) {
6057 struct pinctrl_gpio_range *range;
6058
6059 range = &pin_range->range;
6060 if (range->id == NGPIO_OF_BANK * idx) {
6061 bank->gpio_offset = range->id;
6062 bank->ngpio = range->npins;
6063 bank->gpio_pins = range->pins;
6064 bank->pctldev = pin_range->pctldev;
6065 break;
6066 }
6067 }
6068
6069 BUG_ON(!bank->pctldev);
6070 }
6071
6072 platform_set_drvdata(pdev, a7gc);
6073 dev_info(&pdev->dev, "add to system.\n");
6074 return 0;
6075 failed:
6076 return ret;
6077 }
6078
6079 #ifdef CONFIG_PM_SLEEP
6080 static int atlas7_gpio_suspend_noirq(struct device *dev)
6081 {
6082 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6083 struct atlas7_gpio_bank *bank;
6084 void __iomem *ctrl_reg;
6085 u32 idx, pin;
6086
6087 for (idx = 0; idx < a7gc->nbank; idx++) {
6088 bank = &a7gc->banks[idx];
6089 for (pin = 0; pin < bank->ngpio; pin++) {
6090 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6091 bank->sleep_data[pin] = readl(ctrl_reg);
6092 }
6093 }
6094
6095 return 0;
6096 }
6097
6098 static int atlas7_gpio_resume_noirq(struct device *dev)
6099 {
6100 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
6101 struct atlas7_gpio_bank *bank;
6102 void __iomem *ctrl_reg;
6103 u32 idx, pin;
6104
6105 for (idx = 0; idx < a7gc->nbank; idx++) {
6106 bank = &a7gc->banks[idx];
6107 for (pin = 0; pin < bank->ngpio; pin++) {
6108 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
6109 writel(bank->sleep_data[pin], ctrl_reg);
6110 }
6111 }
6112
6113 return 0;
6114 }
6115
6116 static const struct dev_pm_ops atlas7_gpio_pm_ops = {
6117 .suspend_noirq = atlas7_gpio_suspend_noirq,
6118 .resume_noirq = atlas7_gpio_resume_noirq,
6119 .freeze_noirq = atlas7_gpio_suspend_noirq,
6120 .restore_noirq = atlas7_gpio_resume_noirq,
6121 };
6122 #endif
6123
6124 static struct platform_driver atlas7_gpio_driver = {
6125 .driver = {
6126 .name = "atlas7-gpio",
6127 .of_match_table = atlas7_gpio_ids,
6128 #ifdef CONFIG_PM_SLEEP
6129 .pm = &atlas7_gpio_pm_ops,
6130 #endif
6131 },
6132 .probe = atlas7_gpio_probe,
6133 };
6134
6135 static int __init atlas7_gpio_init(void)
6136 {
6137 return platform_driver_register(&atlas7_gpio_driver);
6138 }
6139 subsys_initcall(atlas7_gpio_init);
6140
6141 MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver");
6142 MODULE_LICENSE("GPL");
Linux with added FPC-III support