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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_os.c
blobbfa9a64c316b6ca2eec9a1b2277608f68101d92d
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 #define MAX_Q_DEPTH 32
114 static int ql2xmaxqdepth = MAX_Q_DEPTH;
115 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116 MODULE_PARM_DESC(ql2xmaxqdepth,
117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
119
120 int ql2xenabledif = 2;
121 module_param(ql2xenabledif, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
128
129 int ql2xenablehba_err_chk = 2;
130 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xenablehba_err_chk,
132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
133 " Default is 2.\n"
134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
137
138 int ql2xiidmaenable=1;
139 module_param(ql2xiidmaenable, int, S_IRUGO);
140 MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
144 int ql2xmaxqueues = 1;
145 module_param(ql2xmaxqueues, int, S_IRUGO);
146 MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
150
151 int ql2xmultique_tag;
152 module_param(ql2xmultique_tag, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
157
158 int ql2xfwloadbin;
159 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
160 MODULE_PARM_DESC(ql2xfwloadbin,
161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
167 int ql2xetsenable;
168 module_param(ql2xetsenable, int, S_IRUGO);
169 MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
173 int ql2xdbwr = 1;
174 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
175 MODULE_PARM_DESC(ql2xdbwr,
176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
179
180 int ql2xtargetreset = 1;
181 module_param(ql2xtargetreset, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
186 int ql2xgffidenable;
187 module_param(ql2xgffidenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
191
192 int ql2xasynctmfenable;
193 module_param(ql2xasynctmfenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
197
198 int ql2xdontresethba;
199 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdontresethba,
201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
204
205 uint64_t ql2xmaxlun = MAX_LUNS;
206 module_param(ql2xmaxlun, ullong, S_IRUGO);
207 MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
211 int ql2xmdcapmask = 0x1F;
212 module_param(ql2xmdcapmask, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
216
217 int ql2xmdenable = 1;
218 module_param(ql2xmdenable, int, S_IRUGO);
219 MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
223
224 /*
225 * SCSI host template entry points
226 */
227 static int qla2xxx_slave_configure(struct scsi_device * device);
228 static int qla2xxx_slave_alloc(struct scsi_device *);
229 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230 static void qla2xxx_scan_start(struct Scsi_Host *);
231 static void qla2xxx_slave_destroy(struct scsi_device *);
232 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
233 static int qla2xxx_eh_abort(struct scsi_cmnd *);
234 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
235 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
236 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
238
239 static void qla2x00_clear_drv_active(struct qla_hw_data *);
240 static void qla2x00_free_device(scsi_qla_host_t *);
241 static void qla83xx_disable_laser(scsi_qla_host_t *vha);
242
243 struct scsi_host_template qla2xxx_driver_template = {
244 .module = THIS_MODULE,
245 .name = QLA2XXX_DRIVER_NAME,
246 .queuecommand = qla2xxx_queuecommand,
247
248 .eh_abort_handler = qla2xxx_eh_abort,
249 .eh_device_reset_handler = qla2xxx_eh_device_reset,
250 .eh_target_reset_handler = qla2xxx_eh_target_reset,
251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
252 .eh_host_reset_handler = qla2xxx_eh_host_reset,
253
254 .slave_configure = qla2xxx_slave_configure,
255
256 .slave_alloc = qla2xxx_slave_alloc,
257 .slave_destroy = qla2xxx_slave_destroy,
258 .scan_finished = qla2xxx_scan_finished,
259 .scan_start = qla2xxx_scan_start,
260 .change_queue_depth = scsi_change_queue_depth,
261 .this_id = -1,
262 .cmd_per_lun = 3,
263 .use_clustering = ENABLE_CLUSTERING,
264 .sg_tablesize = SG_ALL,
265
266 .max_sectors = 0xFFFF,
267 .shost_attrs = qla2x00_host_attrs,
268
269 .supported_mode = MODE_INITIATOR,
270 .track_queue_depth = 1,
271 };
272
273 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
274 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
275
276 /* TODO Convert to inlines
277 *
278 * Timer routines
279 */
280
281 __inline__ void
282 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
283 {
284 init_timer(&vha->timer);
285 vha->timer.expires = jiffies + interval * HZ;
286 vha->timer.data = (unsigned long)vha;
287 vha->timer.function = (void (*)(unsigned long))func;
288 add_timer(&vha->timer);
289 vha->timer_active = 1;
290 }
291
292 static inline void
293 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
294 {
295 /* Currently used for 82XX only. */
296 if (vha->device_flags & DFLG_DEV_FAILED) {
297 ql_dbg(ql_dbg_timer, vha, 0x600d,
298 "Device in a failed state, returning.\n");
299 return;
300 }
301
302 mod_timer(&vha->timer, jiffies + interval * HZ);
303 }
304
305 static __inline__ void
306 qla2x00_stop_timer(scsi_qla_host_t *vha)
307 {
308 del_timer_sync(&vha->timer);
309 vha->timer_active = 0;
310 }
311
312 static int qla2x00_do_dpc(void *data);
313
314 static void qla2x00_rst_aen(scsi_qla_host_t *);
315
316 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
317 struct req_que **, struct rsp_que **);
318 static void qla2x00_free_fw_dump(struct qla_hw_data *);
319 static void qla2x00_mem_free(struct qla_hw_data *);
320
321 /* -------------------------------------------------------------------------- */
322 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
323 struct rsp_que *rsp)
324 {
325 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
326 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
327 GFP_KERNEL);
328 if (!ha->req_q_map) {
329 ql_log(ql_log_fatal, vha, 0x003b,
330 "Unable to allocate memory for request queue ptrs.\n");
331 goto fail_req_map;
332 }
333
334 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
335 GFP_KERNEL);
336 if (!ha->rsp_q_map) {
337 ql_log(ql_log_fatal, vha, 0x003c,
338 "Unable to allocate memory for response queue ptrs.\n");
339 goto fail_rsp_map;
340 }
341 /*
342 * Make sure we record at least the request and response queue zero in
343 * case we need to free them if part of the probe fails.
344 */
345 ha->rsp_q_map[0] = rsp;
346 ha->req_q_map[0] = req;
347 set_bit(0, ha->rsp_qid_map);
348 set_bit(0, ha->req_qid_map);
349 return 1;
350
351 fail_rsp_map:
352 kfree(ha->req_q_map);
353 ha->req_q_map = NULL;
354 fail_req_map:
355 return -ENOMEM;
356 }
357
358 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
359 {
360 if (IS_QLAFX00(ha)) {
361 if (req && req->ring_fx00)
362 dma_free_coherent(&ha->pdev->dev,
363 (req->length_fx00 + 1) * sizeof(request_t),
364 req->ring_fx00, req->dma_fx00);
365 } else if (req && req->ring)
366 dma_free_coherent(&ha->pdev->dev,
367 (req->length + 1) * sizeof(request_t),
368 req->ring, req->dma);
369
370 if (req)
371 kfree(req->outstanding_cmds);
372
373 kfree(req);
374 req = NULL;
375 }
376
377 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
378 {
379 if (IS_QLAFX00(ha)) {
380 if (rsp && rsp->ring)
381 dma_free_coherent(&ha->pdev->dev,
382 (rsp->length_fx00 + 1) * sizeof(request_t),
383 rsp->ring_fx00, rsp->dma_fx00);
384 } else if (rsp && rsp->ring) {
385 dma_free_coherent(&ha->pdev->dev,
386 (rsp->length + 1) * sizeof(response_t),
387 rsp->ring, rsp->dma);
388 }
389 kfree(rsp);
390 rsp = NULL;
391 }
392
393 static void qla2x00_free_queues(struct qla_hw_data *ha)
394 {
395 struct req_que *req;
396 struct rsp_que *rsp;
397 int cnt;
398
399 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
400 req = ha->req_q_map[cnt];
401 qla2x00_free_req_que(ha, req);
402 }
403 kfree(ha->req_q_map);
404 ha->req_q_map = NULL;
405
406 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
407 rsp = ha->rsp_q_map[cnt];
408 qla2x00_free_rsp_que(ha, rsp);
409 }
410 kfree(ha->rsp_q_map);
411 ha->rsp_q_map = NULL;
412 }
413
414 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
415 {
416 uint16_t options = 0;
417 int ques, req, ret;
418 struct qla_hw_data *ha = vha->hw;
419
420 if (!(ha->fw_attributes & BIT_6)) {
421 ql_log(ql_log_warn, vha, 0x00d8,
422 "Firmware is not multi-queue capable.\n");
423 goto fail;
424 }
425 if (ql2xmultique_tag) {
426 /* create a request queue for IO */
427 options |= BIT_7;
428 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
429 QLA_DEFAULT_QUE_QOS);
430 if (!req) {
431 ql_log(ql_log_warn, vha, 0x00e0,
432 "Failed to create request queue.\n");
433 goto fail;
434 }
435 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
436 vha->req = ha->req_q_map[req];
437 options |= BIT_1;
438 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
439 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
440 if (!ret) {
441 ql_log(ql_log_warn, vha, 0x00e8,
442 "Failed to create response queue.\n");
443 goto fail2;
444 }
445 }
446 ha->flags.cpu_affinity_enabled = 1;
447 ql_dbg(ql_dbg_multiq, vha, 0xc007,
448 "CPU affinity mode enabled, "
449 "no. of response queues:%d no. of request queues:%d.\n",
450 ha->max_rsp_queues, ha->max_req_queues);
451 ql_dbg(ql_dbg_init, vha, 0x00e9,
452 "CPU affinity mode enabled, "
453 "no. of response queues:%d no. of request queues:%d.\n",
454 ha->max_rsp_queues, ha->max_req_queues);
455 }
456 return 0;
457 fail2:
458 qla25xx_delete_queues(vha);
459 destroy_workqueue(ha->wq);
460 ha->wq = NULL;
461 vha->req = ha->req_q_map[0];
462 fail:
463 ha->mqenable = 0;
464 kfree(ha->req_q_map);
465 kfree(ha->rsp_q_map);
466 ha->max_req_queues = ha->max_rsp_queues = 1;
467 return 1;
468 }
469
470 static char *
471 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
472 {
473 struct qla_hw_data *ha = vha->hw;
474 static char *pci_bus_modes[] = {
475 "33", "66", "100", "133",
476 };
477 uint16_t pci_bus;
478
479 strcpy(str, "PCI");
480 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
481 if (pci_bus) {
482 strcat(str, "-X (");
483 strcat(str, pci_bus_modes[pci_bus]);
484 } else {
485 pci_bus = (ha->pci_attr & BIT_8) >> 8;
486 strcat(str, " (");
487 strcat(str, pci_bus_modes[pci_bus]);
488 }
489 strcat(str, " MHz)");
490
491 return (str);
492 }
493
494 static char *
495 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
496 {
497 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
498 struct qla_hw_data *ha = vha->hw;
499 uint32_t pci_bus;
500
501 if (pci_is_pcie(ha->pdev)) {
502 char lwstr[6];
503 uint32_t lstat, lspeed, lwidth;
504
505 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
506 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
507 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
508
509 strcpy(str, "PCIe (");
510 switch (lspeed) {
511 case 1:
512 strcat(str, "2.5GT/s ");
513 break;
514 case 2:
515 strcat(str, "5.0GT/s ");
516 break;
517 case 3:
518 strcat(str, "8.0GT/s ");
519 break;
520 default:
521 strcat(str, "<unknown> ");
522 break;
523 }
524 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
525 strcat(str, lwstr);
526
527 return str;
528 }
529
530 strcpy(str, "PCI");
531 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
532 if (pci_bus == 0 || pci_bus == 8) {
533 strcat(str, " (");
534 strcat(str, pci_bus_modes[pci_bus >> 3]);
535 } else {
536 strcat(str, "-X ");
537 if (pci_bus & BIT_2)
538 strcat(str, "Mode 2");
539 else
540 strcat(str, "Mode 1");
541 strcat(str, " (");
542 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
543 }
544 strcat(str, " MHz)");
545
546 return str;
547 }
548
549 static char *
550 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
551 {
552 char un_str[10];
553 struct qla_hw_data *ha = vha->hw;
554
555 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
556 ha->fw_minor_version, ha->fw_subminor_version);
557
558 if (ha->fw_attributes & BIT_9) {
559 strcat(str, "FLX");
560 return (str);
561 }
562
563 switch (ha->fw_attributes & 0xFF) {
564 case 0x7:
565 strcat(str, "EF");
566 break;
567 case 0x17:
568 strcat(str, "TP");
569 break;
570 case 0x37:
571 strcat(str, "IP");
572 break;
573 case 0x77:
574 strcat(str, "VI");
575 break;
576 default:
577 sprintf(un_str, "(%x)", ha->fw_attributes);
578 strcat(str, un_str);
579 break;
580 }
581 if (ha->fw_attributes & 0x100)
582 strcat(str, "X");
583
584 return (str);
585 }
586
587 static char *
588 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
589 {
590 struct qla_hw_data *ha = vha->hw;
591
592 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
593 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
594 return str;
595 }
596
597 void
598 qla2x00_sp_free_dma(void *vha, void *ptr)
599 {
600 srb_t *sp = (srb_t *)ptr;
601 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
602 struct qla_hw_data *ha = sp->fcport->vha->hw;
603 void *ctx = GET_CMD_CTX_SP(sp);
604
605 if (sp->flags & SRB_DMA_VALID) {
606 scsi_dma_unmap(cmd);
607 sp->flags &= ~SRB_DMA_VALID;
608 }
609
610 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
611 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
612 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
613 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
614 }
615
616 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
617 /* List assured to be having elements */
618 qla2x00_clean_dsd_pool(ha, sp, NULL);
619 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
620 }
621
622 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
623 dma_pool_free(ha->dl_dma_pool, ctx,
624 ((struct crc_context *)ctx)->crc_ctx_dma);
625 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
629 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
630
631 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
632 ctx1->fcp_cmnd_dma);
633 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
634 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
635 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
636 mempool_free(ctx1, ha->ctx_mempool);
637 ctx1 = NULL;
638 }
639
640 CMD_SP(cmd) = NULL;
641 qla2x00_rel_sp(sp->fcport->vha, sp);
642 }
643
644 static void
645 qla2x00_sp_compl(void *data, void *ptr, int res)
646 {
647 struct qla_hw_data *ha = (struct qla_hw_data *)data;
648 srb_t *sp = (srb_t *)ptr;
649 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
650
651 cmd->result = res;
652
653 if (atomic_read(&sp->ref_count) == 0) {
654 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
655 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
656 sp, GET_CMD_SP(sp));
657 if (ql2xextended_error_logging & ql_dbg_io)
658 WARN_ON(atomic_read(&sp->ref_count) == 0);
659 return;
660 }
661 if (!atomic_dec_and_test(&sp->ref_count))
662 return;
663
664 qla2x00_sp_free_dma(ha, sp);
665 cmd->scsi_done(cmd);
666 }
667
668 /* If we are SP1 here, we need to still take and release the host_lock as SP1
669 * does not have the changes necessary to avoid taking host->host_lock.
670 */
671 static int
672 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
673 {
674 scsi_qla_host_t *vha = shost_priv(host);
675 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
676 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
677 struct qla_hw_data *ha = vha->hw;
678 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
679 srb_t *sp;
680 int rval;
681
682 if (ha->flags.eeh_busy) {
683 if (ha->flags.pci_channel_io_perm_failure) {
684 ql_dbg(ql_dbg_aer, vha, 0x9010,
685 "PCI Channel IO permanent failure, exiting "
686 "cmd=%p.\n", cmd);
687 cmd->result = DID_NO_CONNECT << 16;
688 } else {
689 ql_dbg(ql_dbg_aer, vha, 0x9011,
690 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
691 cmd->result = DID_REQUEUE << 16;
692 }
693 goto qc24_fail_command;
694 }
695
696 rval = fc_remote_port_chkready(rport);
697 if (rval) {
698 cmd->result = rval;
699 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
700 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
701 cmd, rval);
702 goto qc24_fail_command;
703 }
704
705 if (!vha->flags.difdix_supported &&
706 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
707 ql_dbg(ql_dbg_io, vha, 0x3004,
708 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
709 cmd);
710 cmd->result = DID_NO_CONNECT << 16;
711 goto qc24_fail_command;
712 }
713
714 if (!fcport) {
715 cmd->result = DID_NO_CONNECT << 16;
716 goto qc24_fail_command;
717 }
718
719 if (atomic_read(&fcport->state) != FCS_ONLINE) {
720 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
721 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
722 ql_dbg(ql_dbg_io, vha, 0x3005,
723 "Returning DNC, fcport_state=%d loop_state=%d.\n",
724 atomic_read(&fcport->state),
725 atomic_read(&base_vha->loop_state));
726 cmd->result = DID_NO_CONNECT << 16;
727 goto qc24_fail_command;
728 }
729 goto qc24_target_busy;
730 }
731
732 /*
733 * Return target busy if we've received a non-zero retry_delay_timer
734 * in a FCP_RSP.
735 */
736 if (fcport->retry_delay_timestamp == 0) {
737 /* retry delay not set */
738 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
739 fcport->retry_delay_timestamp = 0;
740 else
741 goto qc24_target_busy;
742
743 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
744 if (!sp)
745 goto qc24_host_busy;
746
747 sp->u.scmd.cmd = cmd;
748 sp->type = SRB_SCSI_CMD;
749 atomic_set(&sp->ref_count, 1);
750 CMD_SP(cmd) = (void *)sp;
751 sp->free = qla2x00_sp_free_dma;
752 sp->done = qla2x00_sp_compl;
753
754 rval = ha->isp_ops->start_scsi(sp);
755 if (rval != QLA_SUCCESS) {
756 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
757 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
758 goto qc24_host_busy_free_sp;
759 }
760
761 return 0;
762
763 qc24_host_busy_free_sp:
764 qla2x00_sp_free_dma(ha, sp);
765
766 qc24_host_busy:
767 return SCSI_MLQUEUE_HOST_BUSY;
768
769 qc24_target_busy:
770 return SCSI_MLQUEUE_TARGET_BUSY;
771
772 qc24_fail_command:
773 cmd->scsi_done(cmd);
774
775 return 0;
776 }
777
778 /*
779 * qla2x00_eh_wait_on_command
780 * Waits for the command to be returned by the Firmware for some
781 * max time.
782 *
783 * Input:
784 * cmd = Scsi Command to wait on.
785 *
786 * Return:
787 * Not Found : 0
788 * Found : 1
789 */
790 static int
791 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
792 {
793 #define ABORT_POLLING_PERIOD 1000
794 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
795 unsigned long wait_iter = ABORT_WAIT_ITER;
796 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
797 struct qla_hw_data *ha = vha->hw;
798 int ret = QLA_SUCCESS;
799
800 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
801 ql_dbg(ql_dbg_taskm, vha, 0x8005,
802 "Return:eh_wait.\n");
803 return ret;
804 }
805
806 while (CMD_SP(cmd) && wait_iter--) {
807 msleep(ABORT_POLLING_PERIOD);
808 }
809 if (CMD_SP(cmd))
810 ret = QLA_FUNCTION_FAILED;
811
812 return ret;
813 }
814
815 /*
816 * qla2x00_wait_for_hba_online
817 * Wait till the HBA is online after going through
818 * <= MAX_RETRIES_OF_ISP_ABORT or
819 * finally HBA is disabled ie marked offline
820 *
821 * Input:
822 * ha - pointer to host adapter structure
823 *
824 * Note:
825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
827 *
828 * Return:
829 * Success (Adapter is online) : 0
830 * Failed (Adapter is offline/disabled) : 1
831 */
832 int
833 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
834 {
835 int return_status;
836 unsigned long wait_online;
837 struct qla_hw_data *ha = vha->hw;
838 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
839
840 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
841 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
842 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
843 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
844 ha->dpc_active) && time_before(jiffies, wait_online)) {
845
846 msleep(1000);
847 }
848 if (base_vha->flags.online)
849 return_status = QLA_SUCCESS;
850 else
851 return_status = QLA_FUNCTION_FAILED;
852
853 return (return_status);
854 }
855
856 /*
857 * qla2x00_wait_for_hba_ready
858 * Wait till the HBA is ready before doing driver unload
859 *
860 * Input:
861 * ha - pointer to host adapter structure
862 *
863 * Note:
864 * Does context switching-Release SPIN_LOCK
865 * (if any) before calling this routine.
866 *
867 */
868 static void
869 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
870 {
871 struct qla_hw_data *ha = vha->hw;
872
873 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
874 ha->flags.mbox_busy) ||
875 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
876 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
877 msleep(1000);
878 }
879
880 int
881 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
882 {
883 int return_status;
884 unsigned long wait_reset;
885 struct qla_hw_data *ha = vha->hw;
886 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
887
888 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
889 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
890 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
891 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
892 ha->dpc_active) && time_before(jiffies, wait_reset)) {
893
894 msleep(1000);
895
896 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
897 ha->flags.chip_reset_done)
898 break;
899 }
900 if (ha->flags.chip_reset_done)
901 return_status = QLA_SUCCESS;
902 else
903 return_status = QLA_FUNCTION_FAILED;
904
905 return return_status;
906 }
907
908 static void
909 sp_get(struct srb *sp)
910 {
911 atomic_inc(&sp->ref_count);
912 }
913
914 /**************************************************************************
915 * qla2xxx_eh_abort
916 *
917 * Description:
918 * The abort function will abort the specified command.
919 *
920 * Input:
921 * cmd = Linux SCSI command packet to be aborted.
922 *
923 * Returns:
924 * Either SUCCESS or FAILED.
925 *
926 * Note:
927 * Only return FAILED if command not returned by firmware.
928 **************************************************************************/
929 static int
930 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
931 {
932 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
933 srb_t *sp;
934 int ret;
935 unsigned int id;
936 uint64_t lun;
937 unsigned long flags;
938 int rval, wait = 0;
939 struct qla_hw_data *ha = vha->hw;
940
941 if (!CMD_SP(cmd))
942 return SUCCESS;
943
944 ret = fc_block_scsi_eh(cmd);
945 if (ret != 0)
946 return ret;
947 ret = SUCCESS;
948
949 id = cmd->device->id;
950 lun = cmd->device->lun;
951
952 spin_lock_irqsave(&ha->hardware_lock, flags);
953 sp = (srb_t *) CMD_SP(cmd);
954 if (!sp) {
955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
956 return SUCCESS;
957 }
958
959 ql_dbg(ql_dbg_taskm, vha, 0x8002,
960 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
961 vha->host_no, id, lun, sp, cmd, sp->handle);
962
963 /* Get a reference to the sp and drop the lock.*/
964 sp_get(sp);
965
966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
967 rval = ha->isp_ops->abort_command(sp);
968 if (rval) {
969 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
970 ret = SUCCESS;
971 else
972 ret = FAILED;
973
974 ql_dbg(ql_dbg_taskm, vha, 0x8003,
975 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
976 } else {
977 ql_dbg(ql_dbg_taskm, vha, 0x8004,
978 "Abort command mbx success cmd=%p.\n", cmd);
979 wait = 1;
980 }
981
982 spin_lock_irqsave(&ha->hardware_lock, flags);
983 sp->done(ha, sp, 0);
984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
985
986 /* Did the command return during mailbox execution? */
987 if (ret == FAILED && !CMD_SP(cmd))
988 ret = SUCCESS;
989
990 /* Wait for the command to be returned. */
991 if (wait) {
992 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
993 ql_log(ql_log_warn, vha, 0x8006,
994 "Abort handler timed out cmd=%p.\n", cmd);
995 ret = FAILED;
996 }
997 }
998
999 ql_log(ql_log_info, vha, 0x801c,
1000 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1001 vha->host_no, id, lun, wait, ret);
1002
1003 return ret;
1004 }
1005
1006 int
1007 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1008 uint64_t l, enum nexus_wait_type type)
1009 {
1010 int cnt, match, status;
1011 unsigned long flags;
1012 struct qla_hw_data *ha = vha->hw;
1013 struct req_que *req;
1014 srb_t *sp;
1015 struct scsi_cmnd *cmd;
1016
1017 status = QLA_SUCCESS;
1018
1019 spin_lock_irqsave(&ha->hardware_lock, flags);
1020 req = vha->req;
1021 for (cnt = 1; status == QLA_SUCCESS &&
1022 cnt < req->num_outstanding_cmds; cnt++) {
1023 sp = req->outstanding_cmds[cnt];
1024 if (!sp)
1025 continue;
1026 if (sp->type != SRB_SCSI_CMD)
1027 continue;
1028 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1029 continue;
1030 match = 0;
1031 cmd = GET_CMD_SP(sp);
1032 switch (type) {
1033 case WAIT_HOST:
1034 match = 1;
1035 break;
1036 case WAIT_TARGET:
1037 match = cmd->device->id == t;
1038 break;
1039 case WAIT_LUN:
1040 match = (cmd->device->id == t &&
1041 cmd->device->lun == l);
1042 break;
1043 }
1044 if (!match)
1045 continue;
1046
1047 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1048 status = qla2x00_eh_wait_on_command(cmd);
1049 spin_lock_irqsave(&ha->hardware_lock, flags);
1050 }
1051 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1052
1053 return status;
1054 }
1055
1056 static char *reset_errors[] = {
1057 "HBA not online",
1058 "HBA not ready",
1059 "Task management failed",
1060 "Waiting for command completions",
1061 };
1062
1063 static int
1064 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1065 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1066 {
1067 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1068 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1069 int err;
1070
1071 if (!fcport) {
1072 return FAILED;
1073 }
1074
1075 err = fc_block_scsi_eh(cmd);
1076 if (err != 0)
1077 return err;
1078
1079 ql_log(ql_log_info, vha, 0x8009,
1080 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1081 cmd->device->id, cmd->device->lun, cmd);
1082
1083 err = 0;
1084 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1085 ql_log(ql_log_warn, vha, 0x800a,
1086 "Wait for hba online failed for cmd=%p.\n", cmd);
1087 goto eh_reset_failed;
1088 }
1089 err = 2;
1090 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1091 != QLA_SUCCESS) {
1092 ql_log(ql_log_warn, vha, 0x800c,
1093 "do_reset failed for cmd=%p.\n", cmd);
1094 goto eh_reset_failed;
1095 }
1096 err = 3;
1097 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1098 cmd->device->lun, type) != QLA_SUCCESS) {
1099 ql_log(ql_log_warn, vha, 0x800d,
1100 "wait for pending cmds failed for cmd=%p.\n", cmd);
1101 goto eh_reset_failed;
1102 }
1103
1104 ql_log(ql_log_info, vha, 0x800e,
1105 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1106 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1107
1108 return SUCCESS;
1109
1110 eh_reset_failed:
1111 ql_log(ql_log_info, vha, 0x800f,
1112 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1113 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1114 cmd);
1115 return FAILED;
1116 }
1117
1118 static int
1119 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1120 {
1121 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1122 struct qla_hw_data *ha = vha->hw;
1123
1124 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1125 ha->isp_ops->lun_reset);
1126 }
1127
1128 static int
1129 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1130 {
1131 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1132 struct qla_hw_data *ha = vha->hw;
1133
1134 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1135 ha->isp_ops->target_reset);
1136 }
1137
1138 /**************************************************************************
1139 * qla2xxx_eh_bus_reset
1140 *
1141 * Description:
1142 * The bus reset function will reset the bus and abort any executing
1143 * commands.
1144 *
1145 * Input:
1146 * cmd = Linux SCSI command packet of the command that cause the
1147 * bus reset.
1148 *
1149 * Returns:
1150 * SUCCESS/FAILURE (defined as macro in scsi.h).
1151 *
1152 **************************************************************************/
1153 static int
1154 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1155 {
1156 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1157 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1158 int ret = FAILED;
1159 unsigned int id;
1160 uint64_t lun;
1161
1162 id = cmd->device->id;
1163 lun = cmd->device->lun;
1164
1165 if (!fcport) {
1166 return ret;
1167 }
1168
1169 ret = fc_block_scsi_eh(cmd);
1170 if (ret != 0)
1171 return ret;
1172 ret = FAILED;
1173
1174 ql_log(ql_log_info, vha, 0x8012,
1175 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1176
1177 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1178 ql_log(ql_log_fatal, vha, 0x8013,
1179 "Wait for hba online failed board disabled.\n");
1180 goto eh_bus_reset_done;
1181 }
1182
1183 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1184 ret = SUCCESS;
1185
1186 if (ret == FAILED)
1187 goto eh_bus_reset_done;
1188
1189 /* Flush outstanding commands. */
1190 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1191 QLA_SUCCESS) {
1192 ql_log(ql_log_warn, vha, 0x8014,
1193 "Wait for pending commands failed.\n");
1194 ret = FAILED;
1195 }
1196
1197 eh_bus_reset_done:
1198 ql_log(ql_log_warn, vha, 0x802b,
1199 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1200 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1201
1202 return ret;
1203 }
1204
1205 /**************************************************************************
1206 * qla2xxx_eh_host_reset
1207 *
1208 * Description:
1209 * The reset function will reset the Adapter.
1210 *
1211 * Input:
1212 * cmd = Linux SCSI command packet of the command that cause the
1213 * adapter reset.
1214 *
1215 * Returns:
1216 * Either SUCCESS or FAILED.
1217 *
1218 * Note:
1219 **************************************************************************/
1220 static int
1221 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1222 {
1223 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1224 struct qla_hw_data *ha = vha->hw;
1225 int ret = FAILED;
1226 unsigned int id;
1227 uint64_t lun;
1228 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1229
1230 id = cmd->device->id;
1231 lun = cmd->device->lun;
1232
1233 ql_log(ql_log_info, vha, 0x8018,
1234 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1235
1236 /*
1237 * No point in issuing another reset if one is active. Also do not
1238 * attempt a reset if we are updating flash.
1239 */
1240 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1241 goto eh_host_reset_lock;
1242
1243 if (vha != base_vha) {
1244 if (qla2x00_vp_abort_isp(vha))
1245 goto eh_host_reset_lock;
1246 } else {
1247 if (IS_P3P_TYPE(vha->hw)) {
1248 if (!qla82xx_fcoe_ctx_reset(vha)) {
1249 /* Ctx reset success */
1250 ret = SUCCESS;
1251 goto eh_host_reset_lock;
1252 }
1253 /* fall thru if ctx reset failed */
1254 }
1255 if (ha->wq)
1256 flush_workqueue(ha->wq);
1257
1258 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1259 if (ha->isp_ops->abort_isp(base_vha)) {
1260 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1261 /* failed. schedule dpc to try */
1262 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1263
1264 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1265 ql_log(ql_log_warn, vha, 0x802a,
1266 "wait for hba online failed.\n");
1267 goto eh_host_reset_lock;
1268 }
1269 }
1270 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1271 }
1272
1273 /* Waiting for command to be returned to OS.*/
1274 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1275 QLA_SUCCESS)
1276 ret = SUCCESS;
1277
1278 eh_host_reset_lock:
1279 ql_log(ql_log_info, vha, 0x8017,
1280 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1281 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1282
1283 return ret;
1284 }
1285
1286 /*
1287 * qla2x00_loop_reset
1288 * Issue loop reset.
1289 *
1290 * Input:
1291 * ha = adapter block pointer.
1292 *
1293 * Returns:
1294 * 0 = success
1295 */
1296 int
1297 qla2x00_loop_reset(scsi_qla_host_t *vha)
1298 {
1299 int ret;
1300 struct fc_port *fcport;
1301 struct qla_hw_data *ha = vha->hw;
1302
1303 if (IS_QLAFX00(ha)) {
1304 return qlafx00_loop_reset(vha);
1305 }
1306
1307 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1308 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1309 if (fcport->port_type != FCT_TARGET)
1310 continue;
1311
1312 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1313 if (ret != QLA_SUCCESS) {
1314 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1315 "Bus Reset failed: Reset=%d "
1316 "d_id=%x.\n", ret, fcport->d_id.b24);
1317 }
1318 }
1319 }
1320
1321
1322 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1323 atomic_set(&vha->loop_state, LOOP_DOWN);
1324 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1325 qla2x00_mark_all_devices_lost(vha, 0);
1326 ret = qla2x00_full_login_lip(vha);
1327 if (ret != QLA_SUCCESS) {
1328 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1329 "full_login_lip=%d.\n", ret);
1330 }
1331 }
1332
1333 if (ha->flags.enable_lip_reset) {
1334 ret = qla2x00_lip_reset(vha);
1335 if (ret != QLA_SUCCESS)
1336 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1337 "lip_reset failed (%d).\n", ret);
1338 }
1339
1340 /* Issue marker command only when we are going to start the I/O */
1341 vha->marker_needed = 1;
1342
1343 return QLA_SUCCESS;
1344 }
1345
1346 void
1347 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1348 {
1349 int que, cnt;
1350 unsigned long flags;
1351 srb_t *sp;
1352 struct qla_hw_data *ha = vha->hw;
1353 struct req_que *req;
1354
1355 qlt_host_reset_handler(ha);
1356
1357 spin_lock_irqsave(&ha->hardware_lock, flags);
1358 for (que = 0; que < ha->max_req_queues; que++) {
1359 req = ha->req_q_map[que];
1360 if (!req)
1361 continue;
1362 if (!req->outstanding_cmds)
1363 continue;
1364 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1365 sp = req->outstanding_cmds[cnt];
1366 if (sp) {
1367 req->outstanding_cmds[cnt] = NULL;
1368 sp->done(vha, sp, res);
1369 }
1370 }
1371 }
1372 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1373 }
1374
1375 static int
1376 qla2xxx_slave_alloc(struct scsi_device *sdev)
1377 {
1378 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1379
1380 if (!rport || fc_remote_port_chkready(rport))
1381 return -ENXIO;
1382
1383 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1384
1385 return 0;
1386 }
1387
1388 static int
1389 qla2xxx_slave_configure(struct scsi_device *sdev)
1390 {
1391 scsi_qla_host_t *vha = shost_priv(sdev->host);
1392 struct req_que *req = vha->req;
1393
1394 if (IS_T10_PI_CAPABLE(vha->hw))
1395 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1396
1397 scsi_change_queue_depth(sdev, req->max_q_depth);
1398 return 0;
1399 }
1400
1401 static void
1402 qla2xxx_slave_destroy(struct scsi_device *sdev)
1403 {
1404 sdev->hostdata = NULL;
1405 }
1406
1407 /**
1408 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1409 * @ha: HA context
1410 *
1411 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1412 * supported addressing method.
1413 */
1414 static void
1415 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1416 {
1417 /* Assume a 32bit DMA mask. */
1418 ha->flags.enable_64bit_addressing = 0;
1419
1420 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1421 /* Any upper-dword bits set? */
1422 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1423 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1424 /* Ok, a 64bit DMA mask is applicable. */
1425 ha->flags.enable_64bit_addressing = 1;
1426 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1427 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1428 return;
1429 }
1430 }
1431
1432 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1433 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1434 }
1435
1436 static void
1437 qla2x00_enable_intrs(struct qla_hw_data *ha)
1438 {
1439 unsigned long flags = 0;
1440 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1441
1442 spin_lock_irqsave(&ha->hardware_lock, flags);
1443 ha->interrupts_on = 1;
1444 /* enable risc and host interrupts */
1445 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1446 RD_REG_WORD(&reg->ictrl);
1447 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1448
1449 }
1450
1451 static void
1452 qla2x00_disable_intrs(struct qla_hw_data *ha)
1453 {
1454 unsigned long flags = 0;
1455 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1456
1457 spin_lock_irqsave(&ha->hardware_lock, flags);
1458 ha->interrupts_on = 0;
1459 /* disable risc and host interrupts */
1460 WRT_REG_WORD(&reg->ictrl, 0);
1461 RD_REG_WORD(&reg->ictrl);
1462 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1463 }
1464
1465 static void
1466 qla24xx_enable_intrs(struct qla_hw_data *ha)
1467 {
1468 unsigned long flags = 0;
1469 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1470
1471 spin_lock_irqsave(&ha->hardware_lock, flags);
1472 ha->interrupts_on = 1;
1473 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1474 RD_REG_DWORD(&reg->ictrl);
1475 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1476 }
1477
1478 static void
1479 qla24xx_disable_intrs(struct qla_hw_data *ha)
1480 {
1481 unsigned long flags = 0;
1482 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1483
1484 if (IS_NOPOLLING_TYPE(ha))
1485 return;
1486 spin_lock_irqsave(&ha->hardware_lock, flags);
1487 ha->interrupts_on = 0;
1488 WRT_REG_DWORD(&reg->ictrl, 0);
1489 RD_REG_DWORD(&reg->ictrl);
1490 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1491 }
1492
1493 static int
1494 qla2x00_iospace_config(struct qla_hw_data *ha)
1495 {
1496 resource_size_t pio;
1497 uint16_t msix;
1498 int cpus;
1499
1500 if (pci_request_selected_regions(ha->pdev, ha->bars,
1501 QLA2XXX_DRIVER_NAME)) {
1502 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1503 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1504 pci_name(ha->pdev));
1505 goto iospace_error_exit;
1506 }
1507 if (!(ha->bars & 1))
1508 goto skip_pio;
1509
1510 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1511 pio = pci_resource_start(ha->pdev, 0);
1512 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1513 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1514 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1515 "Invalid pci I/O region size (%s).\n",
1516 pci_name(ha->pdev));
1517 pio = 0;
1518 }
1519 } else {
1520 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1521 "Region #0 no a PIO resource (%s).\n",
1522 pci_name(ha->pdev));
1523 pio = 0;
1524 }
1525 ha->pio_address = pio;
1526 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1527 "PIO address=%llu.\n",
1528 (unsigned long long)ha->pio_address);
1529
1530 skip_pio:
1531 /* Use MMIO operations for all accesses. */
1532 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1533 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1534 "Region #1 not an MMIO resource (%s), aborting.\n",
1535 pci_name(ha->pdev));
1536 goto iospace_error_exit;
1537 }
1538 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1539 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1540 "Invalid PCI mem region size (%s), aborting.\n",
1541 pci_name(ha->pdev));
1542 goto iospace_error_exit;
1543 }
1544
1545 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1546 if (!ha->iobase) {
1547 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1548 "Cannot remap MMIO (%s), aborting.\n",
1549 pci_name(ha->pdev));
1550 goto iospace_error_exit;
1551 }
1552
1553 /* Determine queue resources */
1554 ha->max_req_queues = ha->max_rsp_queues = 1;
1555 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1556 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1557 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1558 goto mqiobase_exit;
1559
1560 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1561 pci_resource_len(ha->pdev, 3));
1562 if (ha->mqiobase) {
1563 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1564 "MQIO Base=%p.\n", ha->mqiobase);
1565 /* Read MSIX vector size of the board */
1566 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1567 ha->msix_count = msix;
1568 /* Max queues are bounded by available msix vectors */
1569 /* queue 0 uses two msix vectors */
1570 if (ql2xmultique_tag) {
1571 cpus = num_online_cpus();
1572 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1573 (cpus + 1) : (ha->msix_count - 1);
1574 ha->max_req_queues = 2;
1575 } else if (ql2xmaxqueues > 1) {
1576 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1577 QLA_MQ_SIZE : ql2xmaxqueues;
1578 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1579 "QoS mode set, max no of request queues:%d.\n",
1580 ha->max_req_queues);
1581 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1582 "QoS mode set, max no of request queues:%d.\n",
1583 ha->max_req_queues);
1584 }
1585 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1586 "MSI-X vector count: %d.\n", msix);
1587 } else
1588 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1589 "BAR 3 not enabled.\n");
1590
1591 mqiobase_exit:
1592 ha->msix_count = ha->max_rsp_queues + 1;
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1594 "MSIX Count:%d.\n", ha->msix_count);
1595 return (0);
1596
1597 iospace_error_exit:
1598 return (-ENOMEM);
1599 }
1600
1601
1602 static int
1603 qla83xx_iospace_config(struct qla_hw_data *ha)
1604 {
1605 uint16_t msix;
1606 int cpus;
1607
1608 if (pci_request_selected_regions(ha->pdev, ha->bars,
1609 QLA2XXX_DRIVER_NAME)) {
1610 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1611 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1612 pci_name(ha->pdev));
1613
1614 goto iospace_error_exit;
1615 }
1616
1617 /* Use MMIO operations for all accesses. */
1618 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1619 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1620 "Invalid pci I/O region size (%s).\n",
1621 pci_name(ha->pdev));
1622 goto iospace_error_exit;
1623 }
1624 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1625 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1626 "Invalid PCI mem region size (%s), aborting\n",
1627 pci_name(ha->pdev));
1628 goto iospace_error_exit;
1629 }
1630
1631 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1632 if (!ha->iobase) {
1633 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1634 "Cannot remap MMIO (%s), aborting.\n",
1635 pci_name(ha->pdev));
1636 goto iospace_error_exit;
1637 }
1638
1639 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1640 /* 83XX 26XX always use MQ type access for queues
1641 * - mbar 2, a.k.a region 4 */
1642 ha->max_req_queues = ha->max_rsp_queues = 1;
1643 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1644 pci_resource_len(ha->pdev, 4));
1645
1646 if (!ha->mqiobase) {
1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1648 "BAR2/region4 not enabled\n");
1649 goto mqiobase_exit;
1650 }
1651
1652 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1653 pci_resource_len(ha->pdev, 2));
1654 if (ha->msixbase) {
1655 /* Read MSIX vector size of the board */
1656 pci_read_config_word(ha->pdev,
1657 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1658 ha->msix_count = msix;
1659 /* Max queues are bounded by available msix vectors */
1660 /* queue 0 uses two msix vectors */
1661 if (ql2xmultique_tag) {
1662 cpus = num_online_cpus();
1663 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1664 (cpus + 1) : (ha->msix_count - 1);
1665 ha->max_req_queues = 2;
1666 } else if (ql2xmaxqueues > 1) {
1667 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1668 QLA_MQ_SIZE : ql2xmaxqueues;
1669 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1670 "QoS mode set, max no of request queues:%d.\n",
1671 ha->max_req_queues);
1672 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1673 "QoS mode set, max no of request queues:%d.\n",
1674 ha->max_req_queues);
1675 }
1676 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1677 "MSI-X vector count: %d.\n", msix);
1678 } else
1679 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1680 "BAR 1 not enabled.\n");
1681
1682 mqiobase_exit:
1683 ha->msix_count = ha->max_rsp_queues + 1;
1684
1685 qlt_83xx_iospace_config(ha);
1686
1687 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1688 "MSIX Count:%d.\n", ha->msix_count);
1689 return 0;
1690
1691 iospace_error_exit:
1692 return -ENOMEM;
1693 }
1694
1695 static struct isp_operations qla2100_isp_ops = {
1696 .pci_config = qla2100_pci_config,
1697 .reset_chip = qla2x00_reset_chip,
1698 .chip_diag = qla2x00_chip_diag,
1699 .config_rings = qla2x00_config_rings,
1700 .reset_adapter = qla2x00_reset_adapter,
1701 .nvram_config = qla2x00_nvram_config,
1702 .update_fw_options = qla2x00_update_fw_options,
1703 .load_risc = qla2x00_load_risc,
1704 .pci_info_str = qla2x00_pci_info_str,
1705 .fw_version_str = qla2x00_fw_version_str,
1706 .intr_handler = qla2100_intr_handler,
1707 .enable_intrs = qla2x00_enable_intrs,
1708 .disable_intrs = qla2x00_disable_intrs,
1709 .abort_command = qla2x00_abort_command,
1710 .target_reset = qla2x00_abort_target,
1711 .lun_reset = qla2x00_lun_reset,
1712 .fabric_login = qla2x00_login_fabric,
1713 .fabric_logout = qla2x00_fabric_logout,
1714 .calc_req_entries = qla2x00_calc_iocbs_32,
1715 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1716 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1717 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1718 .read_nvram = qla2x00_read_nvram_data,
1719 .write_nvram = qla2x00_write_nvram_data,
1720 .fw_dump = qla2100_fw_dump,
1721 .beacon_on = NULL,
1722 .beacon_off = NULL,
1723 .beacon_blink = NULL,
1724 .read_optrom = qla2x00_read_optrom_data,
1725 .write_optrom = qla2x00_write_optrom_data,
1726 .get_flash_version = qla2x00_get_flash_version,
1727 .start_scsi = qla2x00_start_scsi,
1728 .abort_isp = qla2x00_abort_isp,
1729 .iospace_config = qla2x00_iospace_config,
1730 .initialize_adapter = qla2x00_initialize_adapter,
1731 };
1732
1733 static struct isp_operations qla2300_isp_ops = {
1734 .pci_config = qla2300_pci_config,
1735 .reset_chip = qla2x00_reset_chip,
1736 .chip_diag = qla2x00_chip_diag,
1737 .config_rings = qla2x00_config_rings,
1738 .reset_adapter = qla2x00_reset_adapter,
1739 .nvram_config = qla2x00_nvram_config,
1740 .update_fw_options = qla2x00_update_fw_options,
1741 .load_risc = qla2x00_load_risc,
1742 .pci_info_str = qla2x00_pci_info_str,
1743 .fw_version_str = qla2x00_fw_version_str,
1744 .intr_handler = qla2300_intr_handler,
1745 .enable_intrs = qla2x00_enable_intrs,
1746 .disable_intrs = qla2x00_disable_intrs,
1747 .abort_command = qla2x00_abort_command,
1748 .target_reset = qla2x00_abort_target,
1749 .lun_reset = qla2x00_lun_reset,
1750 .fabric_login = qla2x00_login_fabric,
1751 .fabric_logout = qla2x00_fabric_logout,
1752 .calc_req_entries = qla2x00_calc_iocbs_32,
1753 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1754 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1755 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1756 .read_nvram = qla2x00_read_nvram_data,
1757 .write_nvram = qla2x00_write_nvram_data,
1758 .fw_dump = qla2300_fw_dump,
1759 .beacon_on = qla2x00_beacon_on,
1760 .beacon_off = qla2x00_beacon_off,
1761 .beacon_blink = qla2x00_beacon_blink,
1762 .read_optrom = qla2x00_read_optrom_data,
1763 .write_optrom = qla2x00_write_optrom_data,
1764 .get_flash_version = qla2x00_get_flash_version,
1765 .start_scsi = qla2x00_start_scsi,
1766 .abort_isp = qla2x00_abort_isp,
1767 .iospace_config = qla2x00_iospace_config,
1768 .initialize_adapter = qla2x00_initialize_adapter,
1769 };
1770
1771 static struct isp_operations qla24xx_isp_ops = {
1772 .pci_config = qla24xx_pci_config,
1773 .reset_chip = qla24xx_reset_chip,
1774 .chip_diag = qla24xx_chip_diag,
1775 .config_rings = qla24xx_config_rings,
1776 .reset_adapter = qla24xx_reset_adapter,
1777 .nvram_config = qla24xx_nvram_config,
1778 .update_fw_options = qla24xx_update_fw_options,
1779 .load_risc = qla24xx_load_risc,
1780 .pci_info_str = qla24xx_pci_info_str,
1781 .fw_version_str = qla24xx_fw_version_str,
1782 .intr_handler = qla24xx_intr_handler,
1783 .enable_intrs = qla24xx_enable_intrs,
1784 .disable_intrs = qla24xx_disable_intrs,
1785 .abort_command = qla24xx_abort_command,
1786 .target_reset = qla24xx_abort_target,
1787 .lun_reset = qla24xx_lun_reset,
1788 .fabric_login = qla24xx_login_fabric,
1789 .fabric_logout = qla24xx_fabric_logout,
1790 .calc_req_entries = NULL,
1791 .build_iocbs = NULL,
1792 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1793 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1794 .read_nvram = qla24xx_read_nvram_data,
1795 .write_nvram = qla24xx_write_nvram_data,
1796 .fw_dump = qla24xx_fw_dump,
1797 .beacon_on = qla24xx_beacon_on,
1798 .beacon_off = qla24xx_beacon_off,
1799 .beacon_blink = qla24xx_beacon_blink,
1800 .read_optrom = qla24xx_read_optrom_data,
1801 .write_optrom = qla24xx_write_optrom_data,
1802 .get_flash_version = qla24xx_get_flash_version,
1803 .start_scsi = qla24xx_start_scsi,
1804 .abort_isp = qla2x00_abort_isp,
1805 .iospace_config = qla2x00_iospace_config,
1806 .initialize_adapter = qla2x00_initialize_adapter,
1807 };
1808
1809 static struct isp_operations qla25xx_isp_ops = {
1810 .pci_config = qla25xx_pci_config,
1811 .reset_chip = qla24xx_reset_chip,
1812 .chip_diag = qla24xx_chip_diag,
1813 .config_rings = qla24xx_config_rings,
1814 .reset_adapter = qla24xx_reset_adapter,
1815 .nvram_config = qla24xx_nvram_config,
1816 .update_fw_options = qla24xx_update_fw_options,
1817 .load_risc = qla24xx_load_risc,
1818 .pci_info_str = qla24xx_pci_info_str,
1819 .fw_version_str = qla24xx_fw_version_str,
1820 .intr_handler = qla24xx_intr_handler,
1821 .enable_intrs = qla24xx_enable_intrs,
1822 .disable_intrs = qla24xx_disable_intrs,
1823 .abort_command = qla24xx_abort_command,
1824 .target_reset = qla24xx_abort_target,
1825 .lun_reset = qla24xx_lun_reset,
1826 .fabric_login = qla24xx_login_fabric,
1827 .fabric_logout = qla24xx_fabric_logout,
1828 .calc_req_entries = NULL,
1829 .build_iocbs = NULL,
1830 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1831 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1832 .read_nvram = qla25xx_read_nvram_data,
1833 .write_nvram = qla25xx_write_nvram_data,
1834 .fw_dump = qla25xx_fw_dump,
1835 .beacon_on = qla24xx_beacon_on,
1836 .beacon_off = qla24xx_beacon_off,
1837 .beacon_blink = qla24xx_beacon_blink,
1838 .read_optrom = qla25xx_read_optrom_data,
1839 .write_optrom = qla24xx_write_optrom_data,
1840 .get_flash_version = qla24xx_get_flash_version,
1841 .start_scsi = qla24xx_dif_start_scsi,
1842 .abort_isp = qla2x00_abort_isp,
1843 .iospace_config = qla2x00_iospace_config,
1844 .initialize_adapter = qla2x00_initialize_adapter,
1845 };
1846
1847 static struct isp_operations qla81xx_isp_ops = {
1848 .pci_config = qla25xx_pci_config,
1849 .reset_chip = qla24xx_reset_chip,
1850 .chip_diag = qla24xx_chip_diag,
1851 .config_rings = qla24xx_config_rings,
1852 .reset_adapter = qla24xx_reset_adapter,
1853 .nvram_config = qla81xx_nvram_config,
1854 .update_fw_options = qla81xx_update_fw_options,
1855 .load_risc = qla81xx_load_risc,
1856 .pci_info_str = qla24xx_pci_info_str,
1857 .fw_version_str = qla24xx_fw_version_str,
1858 .intr_handler = qla24xx_intr_handler,
1859 .enable_intrs = qla24xx_enable_intrs,
1860 .disable_intrs = qla24xx_disable_intrs,
1861 .abort_command = qla24xx_abort_command,
1862 .target_reset = qla24xx_abort_target,
1863 .lun_reset = qla24xx_lun_reset,
1864 .fabric_login = qla24xx_login_fabric,
1865 .fabric_logout = qla24xx_fabric_logout,
1866 .calc_req_entries = NULL,
1867 .build_iocbs = NULL,
1868 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1869 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1870 .read_nvram = NULL,
1871 .write_nvram = NULL,
1872 .fw_dump = qla81xx_fw_dump,
1873 .beacon_on = qla24xx_beacon_on,
1874 .beacon_off = qla24xx_beacon_off,
1875 .beacon_blink = qla83xx_beacon_blink,
1876 .read_optrom = qla25xx_read_optrom_data,
1877 .write_optrom = qla24xx_write_optrom_data,
1878 .get_flash_version = qla24xx_get_flash_version,
1879 .start_scsi = qla24xx_dif_start_scsi,
1880 .abort_isp = qla2x00_abort_isp,
1881 .iospace_config = qla2x00_iospace_config,
1882 .initialize_adapter = qla2x00_initialize_adapter,
1883 };
1884
1885 static struct isp_operations qla82xx_isp_ops = {
1886 .pci_config = qla82xx_pci_config,
1887 .reset_chip = qla82xx_reset_chip,
1888 .chip_diag = qla24xx_chip_diag,
1889 .config_rings = qla82xx_config_rings,
1890 .reset_adapter = qla24xx_reset_adapter,
1891 .nvram_config = qla81xx_nvram_config,
1892 .update_fw_options = qla24xx_update_fw_options,
1893 .load_risc = qla82xx_load_risc,
1894 .pci_info_str = qla24xx_pci_info_str,
1895 .fw_version_str = qla24xx_fw_version_str,
1896 .intr_handler = qla82xx_intr_handler,
1897 .enable_intrs = qla82xx_enable_intrs,
1898 .disable_intrs = qla82xx_disable_intrs,
1899 .abort_command = qla24xx_abort_command,
1900 .target_reset = qla24xx_abort_target,
1901 .lun_reset = qla24xx_lun_reset,
1902 .fabric_login = qla24xx_login_fabric,
1903 .fabric_logout = qla24xx_fabric_logout,
1904 .calc_req_entries = NULL,
1905 .build_iocbs = NULL,
1906 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1907 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1908 .read_nvram = qla24xx_read_nvram_data,
1909 .write_nvram = qla24xx_write_nvram_data,
1910 .fw_dump = qla82xx_fw_dump,
1911 .beacon_on = qla82xx_beacon_on,
1912 .beacon_off = qla82xx_beacon_off,
1913 .beacon_blink = NULL,
1914 .read_optrom = qla82xx_read_optrom_data,
1915 .write_optrom = qla82xx_write_optrom_data,
1916 .get_flash_version = qla82xx_get_flash_version,
1917 .start_scsi = qla82xx_start_scsi,
1918 .abort_isp = qla82xx_abort_isp,
1919 .iospace_config = qla82xx_iospace_config,
1920 .initialize_adapter = qla2x00_initialize_adapter,
1921 };
1922
1923 static struct isp_operations qla8044_isp_ops = {
1924 .pci_config = qla82xx_pci_config,
1925 .reset_chip = qla82xx_reset_chip,
1926 .chip_diag = qla24xx_chip_diag,
1927 .config_rings = qla82xx_config_rings,
1928 .reset_adapter = qla24xx_reset_adapter,
1929 .nvram_config = qla81xx_nvram_config,
1930 .update_fw_options = qla24xx_update_fw_options,
1931 .load_risc = qla82xx_load_risc,
1932 .pci_info_str = qla24xx_pci_info_str,
1933 .fw_version_str = qla24xx_fw_version_str,
1934 .intr_handler = qla8044_intr_handler,
1935 .enable_intrs = qla82xx_enable_intrs,
1936 .disable_intrs = qla82xx_disable_intrs,
1937 .abort_command = qla24xx_abort_command,
1938 .target_reset = qla24xx_abort_target,
1939 .lun_reset = qla24xx_lun_reset,
1940 .fabric_login = qla24xx_login_fabric,
1941 .fabric_logout = qla24xx_fabric_logout,
1942 .calc_req_entries = NULL,
1943 .build_iocbs = NULL,
1944 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1945 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1946 .read_nvram = NULL,
1947 .write_nvram = NULL,
1948 .fw_dump = qla8044_fw_dump,
1949 .beacon_on = qla82xx_beacon_on,
1950 .beacon_off = qla82xx_beacon_off,
1951 .beacon_blink = NULL,
1952 .read_optrom = qla8044_read_optrom_data,
1953 .write_optrom = qla8044_write_optrom_data,
1954 .get_flash_version = qla82xx_get_flash_version,
1955 .start_scsi = qla82xx_start_scsi,
1956 .abort_isp = qla8044_abort_isp,
1957 .iospace_config = qla82xx_iospace_config,
1958 .initialize_adapter = qla2x00_initialize_adapter,
1959 };
1960
1961 static struct isp_operations qla83xx_isp_ops = {
1962 .pci_config = qla25xx_pci_config,
1963 .reset_chip = qla24xx_reset_chip,
1964 .chip_diag = qla24xx_chip_diag,
1965 .config_rings = qla24xx_config_rings,
1966 .reset_adapter = qla24xx_reset_adapter,
1967 .nvram_config = qla81xx_nvram_config,
1968 .update_fw_options = qla81xx_update_fw_options,
1969 .load_risc = qla81xx_load_risc,
1970 .pci_info_str = qla24xx_pci_info_str,
1971 .fw_version_str = qla24xx_fw_version_str,
1972 .intr_handler = qla24xx_intr_handler,
1973 .enable_intrs = qla24xx_enable_intrs,
1974 .disable_intrs = qla24xx_disable_intrs,
1975 .abort_command = qla24xx_abort_command,
1976 .target_reset = qla24xx_abort_target,
1977 .lun_reset = qla24xx_lun_reset,
1978 .fabric_login = qla24xx_login_fabric,
1979 .fabric_logout = qla24xx_fabric_logout,
1980 .calc_req_entries = NULL,
1981 .build_iocbs = NULL,
1982 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1983 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1984 .read_nvram = NULL,
1985 .write_nvram = NULL,
1986 .fw_dump = qla83xx_fw_dump,
1987 .beacon_on = qla24xx_beacon_on,
1988 .beacon_off = qla24xx_beacon_off,
1989 .beacon_blink = qla83xx_beacon_blink,
1990 .read_optrom = qla25xx_read_optrom_data,
1991 .write_optrom = qla24xx_write_optrom_data,
1992 .get_flash_version = qla24xx_get_flash_version,
1993 .start_scsi = qla24xx_dif_start_scsi,
1994 .abort_isp = qla2x00_abort_isp,
1995 .iospace_config = qla83xx_iospace_config,
1996 .initialize_adapter = qla2x00_initialize_adapter,
1997 };
1998
1999 static struct isp_operations qlafx00_isp_ops = {
2000 .pci_config = qlafx00_pci_config,
2001 .reset_chip = qlafx00_soft_reset,
2002 .chip_diag = qlafx00_chip_diag,
2003 .config_rings = qlafx00_config_rings,
2004 .reset_adapter = qlafx00_soft_reset,
2005 .nvram_config = NULL,
2006 .update_fw_options = NULL,
2007 .load_risc = NULL,
2008 .pci_info_str = qlafx00_pci_info_str,
2009 .fw_version_str = qlafx00_fw_version_str,
2010 .intr_handler = qlafx00_intr_handler,
2011 .enable_intrs = qlafx00_enable_intrs,
2012 .disable_intrs = qlafx00_disable_intrs,
2013 .abort_command = qla24xx_async_abort_command,
2014 .target_reset = qlafx00_abort_target,
2015 .lun_reset = qlafx00_lun_reset,
2016 .fabric_login = NULL,
2017 .fabric_logout = NULL,
2018 .calc_req_entries = NULL,
2019 .build_iocbs = NULL,
2020 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2021 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2022 .read_nvram = qla24xx_read_nvram_data,
2023 .write_nvram = qla24xx_write_nvram_data,
2024 .fw_dump = NULL,
2025 .beacon_on = qla24xx_beacon_on,
2026 .beacon_off = qla24xx_beacon_off,
2027 .beacon_blink = NULL,
2028 .read_optrom = qla24xx_read_optrom_data,
2029 .write_optrom = qla24xx_write_optrom_data,
2030 .get_flash_version = qla24xx_get_flash_version,
2031 .start_scsi = qlafx00_start_scsi,
2032 .abort_isp = qlafx00_abort_isp,
2033 .iospace_config = qlafx00_iospace_config,
2034 .initialize_adapter = qlafx00_initialize_adapter,
2035 };
2036
2037 static struct isp_operations qla27xx_isp_ops = {
2038 .pci_config = qla25xx_pci_config,
2039 .reset_chip = qla24xx_reset_chip,
2040 .chip_diag = qla24xx_chip_diag,
2041 .config_rings = qla24xx_config_rings,
2042 .reset_adapter = qla24xx_reset_adapter,
2043 .nvram_config = qla81xx_nvram_config,
2044 .update_fw_options = qla81xx_update_fw_options,
2045 .load_risc = qla81xx_load_risc,
2046 .pci_info_str = qla24xx_pci_info_str,
2047 .fw_version_str = qla24xx_fw_version_str,
2048 .intr_handler = qla24xx_intr_handler,
2049 .enable_intrs = qla24xx_enable_intrs,
2050 .disable_intrs = qla24xx_disable_intrs,
2051 .abort_command = qla24xx_abort_command,
2052 .target_reset = qla24xx_abort_target,
2053 .lun_reset = qla24xx_lun_reset,
2054 .fabric_login = qla24xx_login_fabric,
2055 .fabric_logout = qla24xx_fabric_logout,
2056 .calc_req_entries = NULL,
2057 .build_iocbs = NULL,
2058 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2059 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2060 .read_nvram = NULL,
2061 .write_nvram = NULL,
2062 .fw_dump = qla27xx_fwdump,
2063 .beacon_on = qla24xx_beacon_on,
2064 .beacon_off = qla24xx_beacon_off,
2065 .beacon_blink = qla83xx_beacon_blink,
2066 .read_optrom = qla25xx_read_optrom_data,
2067 .write_optrom = qla24xx_write_optrom_data,
2068 .get_flash_version = qla24xx_get_flash_version,
2069 .start_scsi = qla24xx_dif_start_scsi,
2070 .abort_isp = qla2x00_abort_isp,
2071 .iospace_config = qla83xx_iospace_config,
2072 .initialize_adapter = qla2x00_initialize_adapter,
2073 };
2074
2075 static inline void
2076 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2077 {
2078 ha->device_type = DT_EXTENDED_IDS;
2079 switch (ha->pdev->device) {
2080 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2081 ha->device_type |= DT_ISP2100;
2082 ha->device_type &= ~DT_EXTENDED_IDS;
2083 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2084 break;
2085 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2086 ha->device_type |= DT_ISP2200;
2087 ha->device_type &= ~DT_EXTENDED_IDS;
2088 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2089 break;
2090 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2091 ha->device_type |= DT_ISP2300;
2092 ha->device_type |= DT_ZIO_SUPPORTED;
2093 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2094 break;
2095 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2096 ha->device_type |= DT_ISP2312;
2097 ha->device_type |= DT_ZIO_SUPPORTED;
2098 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2099 break;
2100 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2101 ha->device_type |= DT_ISP2322;
2102 ha->device_type |= DT_ZIO_SUPPORTED;
2103 if (ha->pdev->subsystem_vendor == 0x1028 &&
2104 ha->pdev->subsystem_device == 0x0170)
2105 ha->device_type |= DT_OEM_001;
2106 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2107 break;
2108 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2109 ha->device_type |= DT_ISP6312;
2110 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2111 break;
2112 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2113 ha->device_type |= DT_ISP6322;
2114 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2115 break;
2116 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2117 ha->device_type |= DT_ISP2422;
2118 ha->device_type |= DT_ZIO_SUPPORTED;
2119 ha->device_type |= DT_FWI2;
2120 ha->device_type |= DT_IIDMA;
2121 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2122 break;
2123 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2124 ha->device_type |= DT_ISP2432;
2125 ha->device_type |= DT_ZIO_SUPPORTED;
2126 ha->device_type |= DT_FWI2;
2127 ha->device_type |= DT_IIDMA;
2128 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2129 break;
2130 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2131 ha->device_type |= DT_ISP8432;
2132 ha->device_type |= DT_ZIO_SUPPORTED;
2133 ha->device_type |= DT_FWI2;
2134 ha->device_type |= DT_IIDMA;
2135 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2136 break;
2137 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2138 ha->device_type |= DT_ISP5422;
2139 ha->device_type |= DT_FWI2;
2140 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2141 break;
2142 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2143 ha->device_type |= DT_ISP5432;
2144 ha->device_type |= DT_FWI2;
2145 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2146 break;
2147 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2148 ha->device_type |= DT_ISP2532;
2149 ha->device_type |= DT_ZIO_SUPPORTED;
2150 ha->device_type |= DT_FWI2;
2151 ha->device_type |= DT_IIDMA;
2152 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2153 break;
2154 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2155 ha->device_type |= DT_ISP8001;
2156 ha->device_type |= DT_ZIO_SUPPORTED;
2157 ha->device_type |= DT_FWI2;
2158 ha->device_type |= DT_IIDMA;
2159 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2160 break;
2161 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2162 ha->device_type |= DT_ISP8021;
2163 ha->device_type |= DT_ZIO_SUPPORTED;
2164 ha->device_type |= DT_FWI2;
2165 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2166 /* Initialize 82XX ISP flags */
2167 qla82xx_init_flags(ha);
2168 break;
2169 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2170 ha->device_type |= DT_ISP8044;
2171 ha->device_type |= DT_ZIO_SUPPORTED;
2172 ha->device_type |= DT_FWI2;
2173 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2174 /* Initialize 82XX ISP flags */
2175 qla82xx_init_flags(ha);
2176 break;
2177 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2178 ha->device_type |= DT_ISP2031;
2179 ha->device_type |= DT_ZIO_SUPPORTED;
2180 ha->device_type |= DT_FWI2;
2181 ha->device_type |= DT_IIDMA;
2182 ha->device_type |= DT_T10_PI;
2183 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2184 break;
2185 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2186 ha->device_type |= DT_ISP8031;
2187 ha->device_type |= DT_ZIO_SUPPORTED;
2188 ha->device_type |= DT_FWI2;
2189 ha->device_type |= DT_IIDMA;
2190 ha->device_type |= DT_T10_PI;
2191 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2192 break;
2193 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2194 ha->device_type |= DT_ISPFX00;
2195 break;
2196 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2197 ha->device_type |= DT_ISP2071;
2198 ha->device_type |= DT_ZIO_SUPPORTED;
2199 ha->device_type |= DT_FWI2;
2200 ha->device_type |= DT_IIDMA;
2201 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2202 break;
2203 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2204 ha->device_type |= DT_ISP2271;
2205 ha->device_type |= DT_ZIO_SUPPORTED;
2206 ha->device_type |= DT_FWI2;
2207 ha->device_type |= DT_IIDMA;
2208 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2209 break;
2210 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2211 ha->device_type |= DT_ISP2261;
2212 ha->device_type |= DT_ZIO_SUPPORTED;
2213 ha->device_type |= DT_FWI2;
2214 ha->device_type |= DT_IIDMA;
2215 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2216 break;
2217 }
2218
2219 if (IS_QLA82XX(ha))
2220 ha->port_no = ha->portnum & 1;
2221 else {
2222 /* Get adapter physical port no from interrupt pin register. */
2223 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2224 if (IS_QLA27XX(ha))
2225 ha->port_no--;
2226 else
2227 ha->port_no = !(ha->port_no & 1);
2228 }
2229
2230 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2231 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2232 ha->device_type, ha->port_no, ha->fw_srisc_address);
2233 }
2234
2235 static void
2236 qla2xxx_scan_start(struct Scsi_Host *shost)
2237 {
2238 scsi_qla_host_t *vha = shost_priv(shost);
2239
2240 if (vha->hw->flags.running_gold_fw)
2241 return;
2242
2243 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2244 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2245 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2246 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2247 }
2248
2249 static int
2250 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2251 {
2252 scsi_qla_host_t *vha = shost_priv(shost);
2253
2254 if (!vha->host)
2255 return 1;
2256 if (time > vha->hw->loop_reset_delay * HZ)
2257 return 1;
2258
2259 return atomic_read(&vha->loop_state) == LOOP_READY;
2260 }
2261
2262 /*
2263 * PCI driver interface
2264 */
2265 static int
2266 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2267 {
2268 int ret = -ENODEV;
2269 struct Scsi_Host *host;
2270 scsi_qla_host_t *base_vha = NULL;
2271 struct qla_hw_data *ha;
2272 char pci_info[30];
2273 char fw_str[30], wq_name[30];
2274 struct scsi_host_template *sht;
2275 int bars, mem_only = 0;
2276 uint16_t req_length = 0, rsp_length = 0;
2277 struct req_que *req = NULL;
2278 struct rsp_que *rsp = NULL;
2279 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2280 sht = &qla2xxx_driver_template;
2281 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2282 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2283 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2284 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2285 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2286 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2287 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2296 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2297 mem_only = 1;
2298 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2299 "Mem only adapter.\n");
2300 }
2301 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2302 "Bars=%d.\n", bars);
2303
2304 if (mem_only) {
2305 if (pci_enable_device_mem(pdev))
2306 goto probe_out;
2307 } else {
2308 if (pci_enable_device(pdev))
2309 goto probe_out;
2310 }
2311
2312 /* This may fail but that's ok */
2313 pci_enable_pcie_error_reporting(pdev);
2314
2315 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2316 if (!ha) {
2317 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2318 "Unable to allocate memory for ha.\n");
2319 goto probe_out;
2320 }
2321 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2322 "Memory allocated for ha=%p.\n", ha);
2323 ha->pdev = pdev;
2324 ha->tgt.enable_class_2 = ql2xenableclass2;
2325 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2326 spin_lock_init(&ha->tgt.q_full_lock);
2327
2328 /* Clear our data area */
2329 ha->bars = bars;
2330 ha->mem_only = mem_only;
2331 spin_lock_init(&ha->hardware_lock);
2332 spin_lock_init(&ha->vport_slock);
2333 mutex_init(&ha->selflogin_lock);
2334 mutex_init(&ha->optrom_mutex);
2335
2336 /* Set ISP-type information. */
2337 qla2x00_set_isp_flags(ha);
2338
2339 /* Set EEH reset type to fundamental if required by hba */
2340 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2341 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2342 pdev->needs_freset = 1;
2343
2344 ha->prev_topology = 0;
2345 ha->init_cb_size = sizeof(init_cb_t);
2346 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2347 ha->optrom_size = OPTROM_SIZE_2300;
2348
2349 /* Assign ISP specific operations. */
2350 if (IS_QLA2100(ha)) {
2351 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2352 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2353 req_length = REQUEST_ENTRY_CNT_2100;
2354 rsp_length = RESPONSE_ENTRY_CNT_2100;
2355 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2356 ha->gid_list_info_size = 4;
2357 ha->flash_conf_off = ~0;
2358 ha->flash_data_off = ~0;
2359 ha->nvram_conf_off = ~0;
2360 ha->nvram_data_off = ~0;
2361 ha->isp_ops = &qla2100_isp_ops;
2362 } else if (IS_QLA2200(ha)) {
2363 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2364 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2365 req_length = REQUEST_ENTRY_CNT_2200;
2366 rsp_length = RESPONSE_ENTRY_CNT_2100;
2367 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2368 ha->gid_list_info_size = 4;
2369 ha->flash_conf_off = ~0;
2370 ha->flash_data_off = ~0;
2371 ha->nvram_conf_off = ~0;
2372 ha->nvram_data_off = ~0;
2373 ha->isp_ops = &qla2100_isp_ops;
2374 } else if (IS_QLA23XX(ha)) {
2375 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2376 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2377 req_length = REQUEST_ENTRY_CNT_2200;
2378 rsp_length = RESPONSE_ENTRY_CNT_2300;
2379 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2380 ha->gid_list_info_size = 6;
2381 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2382 ha->optrom_size = OPTROM_SIZE_2322;
2383 ha->flash_conf_off = ~0;
2384 ha->flash_data_off = ~0;
2385 ha->nvram_conf_off = ~0;
2386 ha->nvram_data_off = ~0;
2387 ha->isp_ops = &qla2300_isp_ops;
2388 } else if (IS_QLA24XX_TYPE(ha)) {
2389 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2390 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2391 req_length = REQUEST_ENTRY_CNT_24XX;
2392 rsp_length = RESPONSE_ENTRY_CNT_2300;
2393 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2394 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2395 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2396 ha->gid_list_info_size = 8;
2397 ha->optrom_size = OPTROM_SIZE_24XX;
2398 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2399 ha->isp_ops = &qla24xx_isp_ops;
2400 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2401 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2402 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2403 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2404 } else if (IS_QLA25XX(ha)) {
2405 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2406 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2407 req_length = REQUEST_ENTRY_CNT_24XX;
2408 rsp_length = RESPONSE_ENTRY_CNT_2300;
2409 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2410 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2411 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2412 ha->gid_list_info_size = 8;
2413 ha->optrom_size = OPTROM_SIZE_25XX;
2414 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2415 ha->isp_ops = &qla25xx_isp_ops;
2416 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2417 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2418 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2419 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2420 } else if (IS_QLA81XX(ha)) {
2421 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2422 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2423 req_length = REQUEST_ENTRY_CNT_24XX;
2424 rsp_length = RESPONSE_ENTRY_CNT_2300;
2425 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2426 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2427 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2428 ha->gid_list_info_size = 8;
2429 ha->optrom_size = OPTROM_SIZE_81XX;
2430 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2431 ha->isp_ops = &qla81xx_isp_ops;
2432 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2433 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2434 ha->nvram_conf_off = ~0;
2435 ha->nvram_data_off = ~0;
2436 } else if (IS_QLA82XX(ha)) {
2437 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2438 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2439 req_length = REQUEST_ENTRY_CNT_82XX;
2440 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2441 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2442 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2443 ha->gid_list_info_size = 8;
2444 ha->optrom_size = OPTROM_SIZE_82XX;
2445 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2446 ha->isp_ops = &qla82xx_isp_ops;
2447 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2448 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2449 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2450 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2451 } else if (IS_QLA8044(ha)) {
2452 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2453 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2454 req_length = REQUEST_ENTRY_CNT_82XX;
2455 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2456 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2457 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2458 ha->gid_list_info_size = 8;
2459 ha->optrom_size = OPTROM_SIZE_83XX;
2460 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2461 ha->isp_ops = &qla8044_isp_ops;
2462 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2463 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2464 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2465 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2466 } else if (IS_QLA83XX(ha)) {
2467 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2468 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2469 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2470 req_length = REQUEST_ENTRY_CNT_83XX;
2471 rsp_length = RESPONSE_ENTRY_CNT_2300;
2472 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2473 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2474 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2475 ha->gid_list_info_size = 8;
2476 ha->optrom_size = OPTROM_SIZE_83XX;
2477 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2478 ha->isp_ops = &qla83xx_isp_ops;
2479 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2480 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2481 ha->nvram_conf_off = ~0;
2482 ha->nvram_data_off = ~0;
2483 } else if (IS_QLAFX00(ha)) {
2484 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2485 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2486 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2487 req_length = REQUEST_ENTRY_CNT_FX00;
2488 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2489 ha->isp_ops = &qlafx00_isp_ops;
2490 ha->port_down_retry_count = 30; /* default value */
2491 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2492 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2493 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2494 ha->mr.fw_hbt_en = 1;
2495 ha->mr.host_info_resend = false;
2496 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2497 } else if (IS_QLA27XX(ha)) {
2498 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2499 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2500 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2501 req_length = REQUEST_ENTRY_CNT_24XX;
2502 rsp_length = RESPONSE_ENTRY_CNT_2300;
2503 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2504 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2505 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2506 ha->gid_list_info_size = 8;
2507 ha->optrom_size = OPTROM_SIZE_83XX;
2508 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2509 ha->isp_ops = &qla27xx_isp_ops;
2510 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2511 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2512 ha->nvram_conf_off = ~0;
2513 ha->nvram_data_off = ~0;
2514 }
2515
2516 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2517 "mbx_count=%d, req_length=%d, "
2518 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2519 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2520 "max_fibre_devices=%d.\n",
2521 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2522 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2523 ha->nvram_npiv_size, ha->max_fibre_devices);
2524 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2525 "isp_ops=%p, flash_conf_off=%d, "
2526 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2527 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2528 ha->nvram_conf_off, ha->nvram_data_off);
2529
2530 /* Configure PCI I/O space */
2531 ret = ha->isp_ops->iospace_config(ha);
2532 if (ret)
2533 goto iospace_config_failed;
2534
2535 ql_log_pci(ql_log_info, pdev, 0x001d,
2536 "Found an ISP%04X irq %d iobase 0x%p.\n",
2537 pdev->device, pdev->irq, ha->iobase);
2538 mutex_init(&ha->vport_lock);
2539 init_completion(&ha->mbx_cmd_comp);
2540 complete(&ha->mbx_cmd_comp);
2541 init_completion(&ha->mbx_intr_comp);
2542 init_completion(&ha->dcbx_comp);
2543 init_completion(&ha->lb_portup_comp);
2544
2545 set_bit(0, (unsigned long *) ha->vp_idx_map);
2546
2547 qla2x00_config_dma_addressing(ha);
2548 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2549 "64 Bit addressing is %s.\n",
2550 ha->flags.enable_64bit_addressing ? "enable" :
2551 "disable");
2552 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2553 if (ret) {
2554 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2555 "Failed to allocate memory for adapter, aborting.\n");
2556
2557 goto probe_hw_failed;
2558 }
2559
2560 req->max_q_depth = MAX_Q_DEPTH;
2561 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2562 req->max_q_depth = ql2xmaxqdepth;
2563
2564
2565 base_vha = qla2x00_create_host(sht, ha);
2566 if (!base_vha) {
2567 ret = -ENOMEM;
2568 qla2x00_mem_free(ha);
2569 qla2x00_free_req_que(ha, req);
2570 qla2x00_free_rsp_que(ha, rsp);
2571 goto probe_hw_failed;
2572 }
2573
2574 pci_set_drvdata(pdev, base_vha);
2575 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2576
2577 host = base_vha->host;
2578 base_vha->req = req;
2579 if (IS_QLA2XXX_MIDTYPE(ha))
2580 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2581 else
2582 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2583 base_vha->vp_idx;
2584
2585 /* Setup fcport template structure. */
2586 ha->mr.fcport.vha = base_vha;
2587 ha->mr.fcport.port_type = FCT_UNKNOWN;
2588 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2589 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2590 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2591 ha->mr.fcport.scan_state = 1;
2592
2593 /* Set the SG table size based on ISP type */
2594 if (!IS_FWI2_CAPABLE(ha)) {
2595 if (IS_QLA2100(ha))
2596 host->sg_tablesize = 32;
2597 } else {
2598 if (!IS_QLA82XX(ha))
2599 host->sg_tablesize = QLA_SG_ALL;
2600 }
2601 host->max_id = ha->max_fibre_devices;
2602 host->cmd_per_lun = 3;
2603 host->unique_id = host->host_no;
2604 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2605 host->max_cmd_len = 32;
2606 else
2607 host->max_cmd_len = MAX_CMDSZ;
2608 host->max_channel = MAX_BUSES - 1;
2609 /* Older HBAs support only 16-bit LUNs */
2610 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2611 ql2xmaxlun > 0xffff)
2612 host->max_lun = 0xffff;
2613 else
2614 host->max_lun = ql2xmaxlun;
2615 host->transportt = qla2xxx_transport_template;
2616 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2617
2618 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2619 "max_id=%d this_id=%d "
2620 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2621 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
2622 host->this_id, host->cmd_per_lun, host->unique_id,
2623 host->max_cmd_len, host->max_channel, host->max_lun,
2624 host->transportt, sht->vendor_id);
2625
2626 que_init:
2627 /* Alloc arrays of request and response ring ptrs */
2628 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2629 ql_log(ql_log_fatal, base_vha, 0x003d,
2630 "Failed to allocate memory for queue pointers..."
2631 "aborting.\n");
2632 goto probe_init_failed;
2633 }
2634
2635 qlt_probe_one_stage1(base_vha, ha);
2636
2637 /* Set up the irqs */
2638 ret = qla2x00_request_irqs(ha, rsp);
2639 if (ret)
2640 goto probe_init_failed;
2641
2642 pci_save_state(pdev);
2643
2644 /* Assign back pointers */
2645 rsp->req = req;
2646 req->rsp = rsp;
2647
2648 if (IS_QLAFX00(ha)) {
2649 ha->rsp_q_map[0] = rsp;
2650 ha->req_q_map[0] = req;
2651 set_bit(0, ha->req_qid_map);
2652 set_bit(0, ha->rsp_qid_map);
2653 }
2654
2655 /* FWI2-capable only. */
2656 req->req_q_in = &ha->iobase->isp24.req_q_in;
2657 req->req_q_out = &ha->iobase->isp24.req_q_out;
2658 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2659 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2660 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
2661 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2662 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2663 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2664 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2665 }
2666
2667 if (IS_QLAFX00(ha)) {
2668 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2669 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2670 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2671 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2672 }
2673
2674 if (IS_P3P_TYPE(ha)) {
2675 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2676 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2677 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2678 }
2679
2680 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2681 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2682 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2683 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2684 "req->req_q_in=%p req->req_q_out=%p "
2685 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2686 req->req_q_in, req->req_q_out,
2687 rsp->rsp_q_in, rsp->rsp_q_out);
2688 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2689 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2690 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2691 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2692 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2693 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2694
2695 if (ha->isp_ops->initialize_adapter(base_vha)) {
2696 ql_log(ql_log_fatal, base_vha, 0x00d6,
2697 "Failed to initialize adapter - Adapter flags %x.\n",
2698 base_vha->device_flags);
2699
2700 if (IS_QLA82XX(ha)) {
2701 qla82xx_idc_lock(ha);
2702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2703 QLA8XXX_DEV_FAILED);
2704 qla82xx_idc_unlock(ha);
2705 ql_log(ql_log_fatal, base_vha, 0x00d7,
2706 "HW State: FAILED.\n");
2707 } else if (IS_QLA8044(ha)) {
2708 qla8044_idc_lock(ha);
2709 qla8044_wr_direct(base_vha,
2710 QLA8044_CRB_DEV_STATE_INDEX,
2711 QLA8XXX_DEV_FAILED);
2712 qla8044_idc_unlock(ha);
2713 ql_log(ql_log_fatal, base_vha, 0x0150,
2714 "HW State: FAILED.\n");
2715 }
2716
2717 ret = -ENODEV;
2718 goto probe_failed;
2719 }
2720
2721 if (IS_QLAFX00(ha))
2722 host->can_queue = QLAFX00_MAX_CANQUEUE;
2723 else
2724 host->can_queue = req->num_outstanding_cmds - 10;
2725
2726 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2727 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2728 host->can_queue, base_vha->req,
2729 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2730
2731 if (ha->mqenable) {
2732 if (qla25xx_setup_mode(base_vha)) {
2733 ql_log(ql_log_warn, base_vha, 0x00ec,
2734 "Failed to create queues, falling back to single queue mode.\n");
2735 goto que_init;
2736 }
2737 }
2738
2739 if (ha->flags.running_gold_fw)
2740 goto skip_dpc;
2741
2742 /*
2743 * Startup the kernel thread for this host adapter
2744 */
2745 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2746 "%s_dpc", base_vha->host_str);
2747 if (IS_ERR(ha->dpc_thread)) {
2748 ql_log(ql_log_fatal, base_vha, 0x00ed,
2749 "Failed to start DPC thread.\n");
2750 ret = PTR_ERR(ha->dpc_thread);
2751 goto probe_failed;
2752 }
2753 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2754 "DPC thread started successfully.\n");
2755
2756 /*
2757 * If we're not coming up in initiator mode, we might sit for
2758 * a while without waking up the dpc thread, which leads to a
2759 * stuck process warning. So just kick the dpc once here and
2760 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2761 */
2762 qla2xxx_wake_dpc(base_vha);
2763
2764 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2765
2766 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2767 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2768 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2769 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2770
2771 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2772 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2773 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2774 INIT_WORK(&ha->idc_state_handler,
2775 qla83xx_idc_state_handler_work);
2776 INIT_WORK(&ha->nic_core_unrecoverable,
2777 qla83xx_nic_core_unrecoverable_work);
2778 }
2779
2780 skip_dpc:
2781 list_add_tail(&base_vha->list, &ha->vp_list);
2782 base_vha->host->irq = ha->pdev->irq;
2783
2784 /* Initialized the timer */
2785 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2786 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2787 "Started qla2x00_timer with "
2788 "interval=%d.\n", WATCH_INTERVAL);
2789 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2790 "Detected hba at address=%p.\n",
2791 ha);
2792
2793 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2794 if (ha->fw_attributes & BIT_4) {
2795 int prot = 0, guard;
2796 base_vha->flags.difdix_supported = 1;
2797 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2798 "Registering for DIF/DIX type 1 and 3 protection.\n");
2799 if (ql2xenabledif == 1)
2800 prot = SHOST_DIX_TYPE0_PROTECTION;
2801 scsi_host_set_prot(host,
2802 prot | SHOST_DIF_TYPE1_PROTECTION
2803 | SHOST_DIF_TYPE2_PROTECTION
2804 | SHOST_DIF_TYPE3_PROTECTION
2805 | SHOST_DIX_TYPE1_PROTECTION
2806 | SHOST_DIX_TYPE2_PROTECTION
2807 | SHOST_DIX_TYPE3_PROTECTION);
2808
2809 guard = SHOST_DIX_GUARD_CRC;
2810
2811 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2812 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2813 guard |= SHOST_DIX_GUARD_IP;
2814
2815 scsi_host_set_guard(host, guard);
2816 } else
2817 base_vha->flags.difdix_supported = 0;
2818 }
2819
2820 ha->isp_ops->enable_intrs(ha);
2821
2822 if (IS_QLAFX00(ha)) {
2823 ret = qlafx00_fx_disc(base_vha,
2824 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2825 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2826 QLA_SG_ALL : 128;
2827 }
2828
2829 ret = scsi_add_host(host, &pdev->dev);
2830 if (ret)
2831 goto probe_failed;
2832
2833 base_vha->flags.init_done = 1;
2834 base_vha->flags.online = 1;
2835 ha->prev_minidump_failed = 0;
2836
2837 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2838 "Init done and hba is online.\n");
2839
2840 if (qla_ini_mode_enabled(base_vha))
2841 scsi_scan_host(host);
2842 else
2843 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2844 "skipping scsi_scan_host() for non-initiator port\n");
2845
2846 qla2x00_alloc_sysfs_attr(base_vha);
2847
2848 if (IS_QLAFX00(ha)) {
2849 ret = qlafx00_fx_disc(base_vha,
2850 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2851
2852 /* Register system information */
2853 ret = qlafx00_fx_disc(base_vha,
2854 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2855 }
2856
2857 qla2x00_init_host_attr(base_vha);
2858
2859 qla2x00_dfs_setup(base_vha);
2860
2861 ql_log(ql_log_info, base_vha, 0x00fb,
2862 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2863 ql_log(ql_log_info, base_vha, 0x00fc,
2864 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2865 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2866 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2867 base_vha->host_no,
2868 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
2869
2870 qlt_add_target(ha, base_vha);
2871
2872 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
2873 return 0;
2874
2875 probe_init_failed:
2876 qla2x00_free_req_que(ha, req);
2877 ha->req_q_map[0] = NULL;
2878 clear_bit(0, ha->req_qid_map);
2879 qla2x00_free_rsp_que(ha, rsp);
2880 ha->rsp_q_map[0] = NULL;
2881 clear_bit(0, ha->rsp_qid_map);
2882 ha->max_req_queues = ha->max_rsp_queues = 0;
2883
2884 probe_failed:
2885 if (base_vha->timer_active)
2886 qla2x00_stop_timer(base_vha);
2887 base_vha->flags.online = 0;
2888 if (ha->dpc_thread) {
2889 struct task_struct *t = ha->dpc_thread;
2890
2891 ha->dpc_thread = NULL;
2892 kthread_stop(t);
2893 }
2894
2895 qla2x00_free_device(base_vha);
2896
2897 scsi_host_put(base_vha->host);
2898
2899 probe_hw_failed:
2900 qla2x00_clear_drv_active(ha);
2901
2902 iospace_config_failed:
2903 if (IS_P3P_TYPE(ha)) {
2904 if (!ha->nx_pcibase)
2905 iounmap((device_reg_t *)ha->nx_pcibase);
2906 if (!ql2xdbwr)
2907 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
2908 } else {
2909 if (ha->iobase)
2910 iounmap(ha->iobase);
2911 if (ha->cregbase)
2912 iounmap(ha->cregbase);
2913 }
2914 pci_release_selected_regions(ha->pdev, ha->bars);
2915 kfree(ha);
2916 ha = NULL;
2917
2918 probe_out:
2919 pci_disable_device(pdev);
2920 return ret;
2921 }
2922
2923 static void
2924 qla2x00_shutdown(struct pci_dev *pdev)
2925 {
2926 scsi_qla_host_t *vha;
2927 struct qla_hw_data *ha;
2928
2929 if (!atomic_read(&pdev->enable_cnt))
2930 return;
2931
2932 vha = pci_get_drvdata(pdev);
2933 ha = vha->hw;
2934
2935 /* Notify ISPFX00 firmware */
2936 if (IS_QLAFX00(ha))
2937 qlafx00_driver_shutdown(vha, 20);
2938
2939 /* Turn-off FCE trace */
2940 if (ha->flags.fce_enabled) {
2941 qla2x00_disable_fce_trace(vha, NULL, NULL);
2942 ha->flags.fce_enabled = 0;
2943 }
2944
2945 /* Turn-off EFT trace */
2946 if (ha->eft)
2947 qla2x00_disable_eft_trace(vha);
2948
2949 /* Stop currently executing firmware. */
2950 qla2x00_try_to_stop_firmware(vha);
2951
2952 /* Turn adapter off line */
2953 vha->flags.online = 0;
2954
2955 /* turn-off interrupts on the card */
2956 if (ha->interrupts_on) {
2957 vha->flags.init_done = 0;
2958 ha->isp_ops->disable_intrs(ha);
2959 }
2960
2961 qla2x00_free_irqs(vha);
2962
2963 qla2x00_free_fw_dump(ha);
2964
2965 pci_disable_pcie_error_reporting(pdev);
2966 pci_disable_device(pdev);
2967 }
2968
2969 /* Deletes all the virtual ports for a given ha */
2970 static void
2971 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
2972 {
2973 scsi_qla_host_t *vha;
2974 unsigned long flags;
2975
2976 mutex_lock(&ha->vport_lock);
2977 while (ha->cur_vport_count) {
2978 spin_lock_irqsave(&ha->vport_slock, flags);
2979
2980 BUG_ON(base_vha->list.next == &ha->vp_list);
2981 /* This assumes first entry in ha->vp_list is always base vha */
2982 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2983 scsi_host_get(vha->host);
2984
2985 spin_unlock_irqrestore(&ha->vport_slock, flags);
2986 mutex_unlock(&ha->vport_lock);
2987
2988 fc_vport_terminate(vha->fc_vport);
2989 scsi_host_put(vha->host);
2990
2991 mutex_lock(&ha->vport_lock);
2992 }
2993 mutex_unlock(&ha->vport_lock);
2994 }
2995
2996 /* Stops all deferred work threads */
2997 static void
2998 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
2999 {
3000 /* Flush the work queue and remove it */
3001 if (ha->wq) {
3002 flush_workqueue(ha->wq);
3003 destroy_workqueue(ha->wq);
3004 ha->wq = NULL;
3005 }
3006
3007 /* Cancel all work and destroy DPC workqueues */
3008 if (ha->dpc_lp_wq) {
3009 cancel_work_sync(&ha->idc_aen);
3010 destroy_workqueue(ha->dpc_lp_wq);
3011 ha->dpc_lp_wq = NULL;
3012 }
3013
3014 if (ha->dpc_hp_wq) {
3015 cancel_work_sync(&ha->nic_core_reset);
3016 cancel_work_sync(&ha->idc_state_handler);
3017 cancel_work_sync(&ha->nic_core_unrecoverable);
3018 destroy_workqueue(ha->dpc_hp_wq);
3019 ha->dpc_hp_wq = NULL;
3020 }
3021
3022 /* Kill the kernel thread for this host */
3023 if (ha->dpc_thread) {
3024 struct task_struct *t = ha->dpc_thread;
3025
3026 /*
3027 * qla2xxx_wake_dpc checks for ->dpc_thread
3028 * so we need to zero it out.
3029 */
3030 ha->dpc_thread = NULL;
3031 kthread_stop(t);
3032 }
3033 }
3034
3035 static void
3036 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3037 {
3038 if (IS_QLA82XX(ha)) {
3039
3040 iounmap((device_reg_t *)ha->nx_pcibase);
3041 if (!ql2xdbwr)
3042 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3043 } else {
3044 if (ha->iobase)
3045 iounmap(ha->iobase);
3046
3047 if (ha->cregbase)
3048 iounmap(ha->cregbase);
3049
3050 if (ha->mqiobase)
3051 iounmap(ha->mqiobase);
3052
3053 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3054 iounmap(ha->msixbase);
3055 }
3056 }
3057
3058 static void
3059 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3060 {
3061 if (IS_QLA8044(ha)) {
3062 qla8044_idc_lock(ha);
3063 qla8044_clear_drv_active(ha);
3064 qla8044_idc_unlock(ha);
3065 } else if (IS_QLA82XX(ha)) {
3066 qla82xx_idc_lock(ha);
3067 qla82xx_clear_drv_active(ha);
3068 qla82xx_idc_unlock(ha);
3069 }
3070 }
3071
3072 static void
3073 qla2x00_remove_one(struct pci_dev *pdev)
3074 {
3075 scsi_qla_host_t *base_vha;
3076 struct qla_hw_data *ha;
3077
3078 base_vha = pci_get_drvdata(pdev);
3079 ha = base_vha->hw;
3080
3081 /* Indicate device removal to prevent future board_disable and wait
3082 * until any pending board_disable has completed. */
3083 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3084 cancel_work_sync(&ha->board_disable);
3085
3086 /*
3087 * If the PCI device is disabled then there was a PCI-disconnect and
3088 * qla2x00_disable_board_on_pci_error has taken care of most of the
3089 * resources.
3090 */
3091 if (!atomic_read(&pdev->enable_cnt)) {
3092 scsi_host_put(base_vha->host);
3093 kfree(ha);
3094 pci_set_drvdata(pdev, NULL);
3095 return;
3096 }
3097
3098 qla2x00_wait_for_hba_ready(base_vha);
3099
3100 set_bit(UNLOADING, &base_vha->dpc_flags);
3101
3102 if (IS_QLAFX00(ha))
3103 qlafx00_driver_shutdown(base_vha, 20);
3104
3105 qla2x00_delete_all_vps(ha, base_vha);
3106
3107 if (IS_QLA8031(ha)) {
3108 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3109 "Clearing fcoe driver presence.\n");
3110 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3111 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3112 "Error while clearing DRV-Presence.\n");
3113 }
3114
3115 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3116
3117 qla2x00_dfs_remove(base_vha);
3118
3119 qla84xx_put_chip(base_vha);
3120
3121 /* Laser should be disabled only for ISP2031 */
3122 if (IS_QLA2031(ha))
3123 qla83xx_disable_laser(base_vha);
3124
3125 /* Disable timer */
3126 if (base_vha->timer_active)
3127 qla2x00_stop_timer(base_vha);
3128
3129 base_vha->flags.online = 0;
3130
3131 qla2x00_destroy_deferred_work(ha);
3132
3133 qlt_remove_target(ha, base_vha);
3134
3135 qla2x00_free_sysfs_attr(base_vha, true);
3136
3137 fc_remove_host(base_vha->host);
3138
3139 scsi_remove_host(base_vha->host);
3140
3141 qla2x00_free_device(base_vha);
3142
3143 qla2x00_clear_drv_active(ha);
3144
3145 scsi_host_put(base_vha->host);
3146
3147 qla2x00_unmap_iobases(ha);
3148
3149 pci_release_selected_regions(ha->pdev, ha->bars);
3150 kfree(ha);
3151 ha = NULL;
3152
3153 pci_disable_pcie_error_reporting(pdev);
3154
3155 pci_disable_device(pdev);
3156 }
3157
3158 static void
3159 qla2x00_free_device(scsi_qla_host_t *vha)
3160 {
3161 struct qla_hw_data *ha = vha->hw;
3162
3163 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3164
3165 /* Disable timer */
3166 if (vha->timer_active)
3167 qla2x00_stop_timer(vha);
3168
3169 qla25xx_delete_queues(vha);
3170
3171 if (ha->flags.fce_enabled)
3172 qla2x00_disable_fce_trace(vha, NULL, NULL);
3173
3174 if (ha->eft)
3175 qla2x00_disable_eft_trace(vha);
3176
3177 /* Stop currently executing firmware. */
3178 qla2x00_try_to_stop_firmware(vha);
3179
3180 vha->flags.online = 0;
3181
3182 /* turn-off interrupts on the card */
3183 if (ha->interrupts_on) {
3184 vha->flags.init_done = 0;
3185 ha->isp_ops->disable_intrs(ha);
3186 }
3187
3188 qla2x00_free_irqs(vha);
3189
3190 qla2x00_free_fcports(vha);
3191
3192 qla2x00_mem_free(ha);
3193
3194 qla82xx_md_free(vha);
3195
3196 qla2x00_free_queues(ha);
3197 }
3198
3199 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3200 {
3201 fc_port_t *fcport, *tfcport;
3202
3203 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3204 list_del(&fcport->list);
3205 qla2x00_clear_loop_id(fcport);
3206 kfree(fcport);
3207 fcport = NULL;
3208 }
3209 }
3210
3211 static inline void
3212 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3213 int defer)
3214 {
3215 struct fc_rport *rport;
3216 scsi_qla_host_t *base_vha;
3217 unsigned long flags;
3218
3219 if (!fcport->rport)
3220 return;
3221
3222 rport = fcport->rport;
3223 if (defer) {
3224 base_vha = pci_get_drvdata(vha->hw->pdev);
3225 spin_lock_irqsave(vha->host->host_lock, flags);
3226 fcport->drport = rport;
3227 spin_unlock_irqrestore(vha->host->host_lock, flags);
3228 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3229 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3230 qla2xxx_wake_dpc(base_vha);
3231 } else {
3232 int now;
3233 if (rport)
3234 fc_remote_port_delete(rport);
3235 qlt_do_generation_tick(vha, &now);
3236 qlt_fc_port_deleted(vha, fcport, now);
3237 }
3238 }
3239
3240 /*
3241 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3242 *
3243 * Input: ha = adapter block pointer. fcport = port structure pointer.
3244 *
3245 * Return: None.
3246 *
3247 * Context:
3248 */
3249 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3250 int do_login, int defer)
3251 {
3252 if (IS_QLAFX00(vha->hw)) {
3253 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3254 qla2x00_schedule_rport_del(vha, fcport, defer);
3255 return;
3256 }
3257
3258 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3259 vha->vp_idx == fcport->vha->vp_idx) {
3260 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3261 qla2x00_schedule_rport_del(vha, fcport, defer);
3262 }
3263 /*
3264 * We may need to retry the login, so don't change the state of the
3265 * port but do the retries.
3266 */
3267 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3268 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3269
3270 if (!do_login)
3271 return;
3272
3273 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3274
3275 if (fcport->login_retry == 0) {
3276 fcport->login_retry = vha->hw->login_retry_count;
3277
3278 ql_dbg(ql_dbg_disc, vha, 0x2067,
3279 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3280 fcport->port_name, fcport->loop_id, fcport->login_retry);
3281 }
3282 }
3283
3284 /*
3285 * qla2x00_mark_all_devices_lost
3286 * Updates fcport state when device goes offline.
3287 *
3288 * Input:
3289 * ha = adapter block pointer.
3290 * fcport = port structure pointer.
3291 *
3292 * Return:
3293 * None.
3294 *
3295 * Context:
3296 */
3297 void
3298 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3299 {
3300 fc_port_t *fcport;
3301
3302 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3303 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3304 continue;
3305
3306 /*
3307 * No point in marking the device as lost, if the device is
3308 * already DEAD.
3309 */
3310 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3311 continue;
3312 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3313 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3314 if (defer)
3315 qla2x00_schedule_rport_del(vha, fcport, defer);
3316 else if (vha->vp_idx == fcport->vha->vp_idx)
3317 qla2x00_schedule_rport_del(vha, fcport, defer);
3318 }
3319 }
3320 }
3321
3322 /*
3323 * qla2x00_mem_alloc
3324 * Allocates adapter memory.
3325 *
3326 * Returns:
3327 * 0 = success.
3328 * !0 = failure.
3329 */
3330 static int
3331 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3332 struct req_que **req, struct rsp_que **rsp)
3333 {
3334 char name[16];
3335
3336 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3337 &ha->init_cb_dma, GFP_KERNEL);
3338 if (!ha->init_cb)
3339 goto fail;
3340
3341 if (qlt_mem_alloc(ha) < 0)
3342 goto fail_free_init_cb;
3343
3344 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3345 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3346 if (!ha->gid_list)
3347 goto fail_free_tgt_mem;
3348
3349 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3350 if (!ha->srb_mempool)
3351 goto fail_free_gid_list;
3352
3353 if (IS_P3P_TYPE(ha)) {
3354 /* Allocate cache for CT6 Ctx. */
3355 if (!ctx_cachep) {
3356 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3357 sizeof(struct ct6_dsd), 0,
3358 SLAB_HWCACHE_ALIGN, NULL);
3359 if (!ctx_cachep)
3360 goto fail_free_gid_list;
3361 }
3362 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3363 ctx_cachep);
3364 if (!ha->ctx_mempool)
3365 goto fail_free_srb_mempool;
3366 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3367 "ctx_cachep=%p ctx_mempool=%p.\n",
3368 ctx_cachep, ha->ctx_mempool);
3369 }
3370
3371 /* Get memory for cached NVRAM */
3372 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3373 if (!ha->nvram)
3374 goto fail_free_ctx_mempool;
3375
3376 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3377 ha->pdev->device);
3378 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3379 DMA_POOL_SIZE, 8, 0);
3380 if (!ha->s_dma_pool)
3381 goto fail_free_nvram;
3382
3383 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3384 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3385 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3386
3387 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3388 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3389 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3390 if (!ha->dl_dma_pool) {
3391 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3392 "Failed to allocate memory for dl_dma_pool.\n");
3393 goto fail_s_dma_pool;
3394 }
3395
3396 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3397 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3398 if (!ha->fcp_cmnd_dma_pool) {
3399 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3400 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3401 goto fail_dl_dma_pool;
3402 }
3403 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3404 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3405 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3406 }
3407
3408 /* Allocate memory for SNS commands */
3409 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3410 /* Get consistent memory allocated for SNS commands */
3411 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3412 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3413 if (!ha->sns_cmd)
3414 goto fail_dma_pool;
3415 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3416 "sns_cmd: %p.\n", ha->sns_cmd);
3417 } else {
3418 /* Get consistent memory allocated for MS IOCB */
3419 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3420 &ha->ms_iocb_dma);
3421 if (!ha->ms_iocb)
3422 goto fail_dma_pool;
3423 /* Get consistent memory allocated for CT SNS commands */
3424 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3425 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3426 if (!ha->ct_sns)
3427 goto fail_free_ms_iocb;
3428 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3429 "ms_iocb=%p ct_sns=%p.\n",
3430 ha->ms_iocb, ha->ct_sns);
3431 }
3432
3433 /* Allocate memory for request ring */
3434 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3435 if (!*req) {
3436 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3437 "Failed to allocate memory for req.\n");
3438 goto fail_req;
3439 }
3440 (*req)->length = req_len;
3441 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3442 ((*req)->length + 1) * sizeof(request_t),
3443 &(*req)->dma, GFP_KERNEL);
3444 if (!(*req)->ring) {
3445 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3446 "Failed to allocate memory for req_ring.\n");
3447 goto fail_req_ring;
3448 }
3449 /* Allocate memory for response ring */
3450 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3451 if (!*rsp) {
3452 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3453 "Failed to allocate memory for rsp.\n");
3454 goto fail_rsp;
3455 }
3456 (*rsp)->hw = ha;
3457 (*rsp)->length = rsp_len;
3458 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3459 ((*rsp)->length + 1) * sizeof(response_t),
3460 &(*rsp)->dma, GFP_KERNEL);
3461 if (!(*rsp)->ring) {
3462 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3463 "Failed to allocate memory for rsp_ring.\n");
3464 goto fail_rsp_ring;
3465 }
3466 (*req)->rsp = *rsp;
3467 (*rsp)->req = *req;
3468 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3469 "req=%p req->length=%d req->ring=%p rsp=%p "
3470 "rsp->length=%d rsp->ring=%p.\n",
3471 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3472 (*rsp)->ring);
3473 /* Allocate memory for NVRAM data for vports */
3474 if (ha->nvram_npiv_size) {
3475 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3476 ha->nvram_npiv_size, GFP_KERNEL);
3477 if (!ha->npiv_info) {
3478 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3479 "Failed to allocate memory for npiv_info.\n");
3480 goto fail_npiv_info;
3481 }
3482 } else
3483 ha->npiv_info = NULL;
3484
3485 /* Get consistent memory allocated for EX-INIT-CB. */
3486 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3487 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3488 &ha->ex_init_cb_dma);
3489 if (!ha->ex_init_cb)
3490 goto fail_ex_init_cb;
3491 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3492 "ex_init_cb=%p.\n", ha->ex_init_cb);
3493 }
3494
3495 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3496
3497 /* Get consistent memory allocated for Async Port-Database. */
3498 if (!IS_FWI2_CAPABLE(ha)) {
3499 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3500 &ha->async_pd_dma);
3501 if (!ha->async_pd)
3502 goto fail_async_pd;
3503 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3504 "async_pd=%p.\n", ha->async_pd);
3505 }
3506
3507 INIT_LIST_HEAD(&ha->vp_list);
3508
3509 /* Allocate memory for our loop_id bitmap */
3510 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3511 GFP_KERNEL);
3512 if (!ha->loop_id_map)
3513 goto fail_async_pd;
3514 else {
3515 qla2x00_set_reserved_loop_ids(ha);
3516 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3517 "loop_id_map=%p.\n", ha->loop_id_map);
3518 }
3519
3520 return 0;
3521
3522 fail_async_pd:
3523 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3524 fail_ex_init_cb:
3525 kfree(ha->npiv_info);
3526 fail_npiv_info:
3527 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3528 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3529 (*rsp)->ring = NULL;
3530 (*rsp)->dma = 0;
3531 fail_rsp_ring:
3532 kfree(*rsp);
3533 fail_rsp:
3534 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3535 sizeof(request_t), (*req)->ring, (*req)->dma);
3536 (*req)->ring = NULL;
3537 (*req)->dma = 0;
3538 fail_req_ring:
3539 kfree(*req);
3540 fail_req:
3541 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3542 ha->ct_sns, ha->ct_sns_dma);
3543 ha->ct_sns = NULL;
3544 ha->ct_sns_dma = 0;
3545 fail_free_ms_iocb:
3546 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3547 ha->ms_iocb = NULL;
3548 ha->ms_iocb_dma = 0;
3549 fail_dma_pool:
3550 if (IS_QLA82XX(ha) || ql2xenabledif) {
3551 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3552 ha->fcp_cmnd_dma_pool = NULL;
3553 }
3554 fail_dl_dma_pool:
3555 if (IS_QLA82XX(ha) || ql2xenabledif) {
3556 dma_pool_destroy(ha->dl_dma_pool);
3557 ha->dl_dma_pool = NULL;
3558 }
3559 fail_s_dma_pool:
3560 dma_pool_destroy(ha->s_dma_pool);
3561 ha->s_dma_pool = NULL;
3562 fail_free_nvram:
3563 kfree(ha->nvram);
3564 ha->nvram = NULL;
3565 fail_free_ctx_mempool:
3566 mempool_destroy(ha->ctx_mempool);
3567 ha->ctx_mempool = NULL;
3568 fail_free_srb_mempool:
3569 mempool_destroy(ha->srb_mempool);
3570 ha->srb_mempool = NULL;
3571 fail_free_gid_list:
3572 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3573 ha->gid_list,
3574 ha->gid_list_dma);
3575 ha->gid_list = NULL;
3576 ha->gid_list_dma = 0;
3577 fail_free_tgt_mem:
3578 qlt_mem_free(ha);
3579 fail_free_init_cb:
3580 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3581 ha->init_cb_dma);
3582 ha->init_cb = NULL;
3583 ha->init_cb_dma = 0;
3584 fail:
3585 ql_log(ql_log_fatal, NULL, 0x0030,
3586 "Memory allocation failure.\n");
3587 return -ENOMEM;
3588 }
3589
3590 /*
3591 * qla2x00_free_fw_dump
3592 * Frees fw dump stuff.
3593 *
3594 * Input:
3595 * ha = adapter block pointer
3596 */
3597 static void
3598 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3599 {
3600 if (ha->fce)
3601 dma_free_coherent(&ha->pdev->dev,
3602 FCE_SIZE, ha->fce, ha->fce_dma);
3603
3604 if (ha->eft)
3605 dma_free_coherent(&ha->pdev->dev,
3606 EFT_SIZE, ha->eft, ha->eft_dma);
3607
3608 if (ha->fw_dump)
3609 vfree(ha->fw_dump);
3610 if (ha->fw_dump_template)
3611 vfree(ha->fw_dump_template);
3612
3613 ha->fce = NULL;
3614 ha->fce_dma = 0;
3615 ha->eft = NULL;
3616 ha->eft_dma = 0;
3617 ha->fw_dumped = 0;
3618 ha->fw_dump_cap_flags = 0;
3619 ha->fw_dump_reading = 0;
3620 ha->fw_dump = NULL;
3621 ha->fw_dump_len = 0;
3622 ha->fw_dump_template = NULL;
3623 ha->fw_dump_template_len = 0;
3624 }
3625
3626 /*
3627 * qla2x00_mem_free
3628 * Frees all adapter allocated memory.
3629 *
3630 * Input:
3631 * ha = adapter block pointer.
3632 */
3633 static void
3634 qla2x00_mem_free(struct qla_hw_data *ha)
3635 {
3636 qla2x00_free_fw_dump(ha);
3637
3638 if (ha->mctp_dump)
3639 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3640 ha->mctp_dump_dma);
3641
3642 if (ha->srb_mempool)
3643 mempool_destroy(ha->srb_mempool);
3644
3645 if (ha->dcbx_tlv)
3646 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3647 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3648
3649 if (ha->xgmac_data)
3650 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3651 ha->xgmac_data, ha->xgmac_data_dma);
3652
3653 if (ha->sns_cmd)
3654 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3655 ha->sns_cmd, ha->sns_cmd_dma);
3656
3657 if (ha->ct_sns)
3658 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3659 ha->ct_sns, ha->ct_sns_dma);
3660
3661 if (ha->sfp_data)
3662 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3663
3664 if (ha->ms_iocb)
3665 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3666
3667 if (ha->ex_init_cb)
3668 dma_pool_free(ha->s_dma_pool,
3669 ha->ex_init_cb, ha->ex_init_cb_dma);
3670
3671 if (ha->async_pd)
3672 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3673
3674 if (ha->s_dma_pool)
3675 dma_pool_destroy(ha->s_dma_pool);
3676
3677 if (ha->gid_list)
3678 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3679 ha->gid_list, ha->gid_list_dma);
3680
3681 if (IS_QLA82XX(ha)) {
3682 if (!list_empty(&ha->gbl_dsd_list)) {
3683 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3684
3685 /* clean up allocated prev pool */
3686 list_for_each_entry_safe(dsd_ptr,
3687 tdsd_ptr, &ha->gbl_dsd_list, list) {
3688 dma_pool_free(ha->dl_dma_pool,
3689 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3690 list_del(&dsd_ptr->list);
3691 kfree(dsd_ptr);
3692 }
3693 }
3694 }
3695
3696 if (ha->dl_dma_pool)
3697 dma_pool_destroy(ha->dl_dma_pool);
3698
3699 if (ha->fcp_cmnd_dma_pool)
3700 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3701
3702 if (ha->ctx_mempool)
3703 mempool_destroy(ha->ctx_mempool);
3704
3705 qlt_mem_free(ha);
3706
3707 if (ha->init_cb)
3708 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3709 ha->init_cb, ha->init_cb_dma);
3710 vfree(ha->optrom_buffer);
3711 kfree(ha->nvram);
3712 kfree(ha->npiv_info);
3713 kfree(ha->swl);
3714 kfree(ha->loop_id_map);
3715
3716 ha->srb_mempool = NULL;
3717 ha->ctx_mempool = NULL;
3718 ha->sns_cmd = NULL;
3719 ha->sns_cmd_dma = 0;
3720 ha->ct_sns = NULL;
3721 ha->ct_sns_dma = 0;
3722 ha->ms_iocb = NULL;
3723 ha->ms_iocb_dma = 0;
3724 ha->init_cb = NULL;
3725 ha->init_cb_dma = 0;
3726 ha->ex_init_cb = NULL;
3727 ha->ex_init_cb_dma = 0;
3728 ha->async_pd = NULL;
3729 ha->async_pd_dma = 0;
3730
3731 ha->s_dma_pool = NULL;
3732 ha->dl_dma_pool = NULL;
3733 ha->fcp_cmnd_dma_pool = NULL;
3734
3735 ha->gid_list = NULL;
3736 ha->gid_list_dma = 0;
3737
3738 ha->tgt.atio_ring = NULL;
3739 ha->tgt.atio_dma = 0;
3740 ha->tgt.tgt_vp_map = NULL;
3741 }
3742
3743 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3744 struct qla_hw_data *ha)
3745 {
3746 struct Scsi_Host *host;
3747 struct scsi_qla_host *vha = NULL;
3748
3749 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3750 if (host == NULL) {
3751 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3752 "Failed to allocate host from the scsi layer, aborting.\n");
3753 goto fail;
3754 }
3755
3756 /* Clear our data area */
3757 vha = shost_priv(host);
3758 memset(vha, 0, sizeof(scsi_qla_host_t));
3759
3760 vha->host = host;
3761 vha->host_no = host->host_no;
3762 vha->hw = ha;
3763
3764 INIT_LIST_HEAD(&vha->vp_fcports);
3765 INIT_LIST_HEAD(&vha->work_list);
3766 INIT_LIST_HEAD(&vha->list);
3767 INIT_LIST_HEAD(&vha->qla_cmd_list);
3768 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
3769
3770 spin_lock_init(&vha->work_lock);
3771 spin_lock_init(&vha->cmd_list_lock);
3772
3773 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3774 ql_dbg(ql_dbg_init, vha, 0x0041,
3775 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3776 vha->host, vha->hw, vha,
3777 dev_name(&(ha->pdev->dev)));
3778
3779 return vha;
3780
3781 fail:
3782 return vha;
3783 }
3784
3785 static struct qla_work_evt *
3786 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3787 {
3788 struct qla_work_evt *e;
3789 uint8_t bail;
3790
3791 QLA_VHA_MARK_BUSY(vha, bail);
3792 if (bail)
3793 return NULL;
3794
3795 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3796 if (!e) {
3797 QLA_VHA_MARK_NOT_BUSY(vha);
3798 return NULL;
3799 }
3800
3801 INIT_LIST_HEAD(&e->list);
3802 e->type = type;
3803 e->flags = QLA_EVT_FLAG_FREE;
3804 return e;
3805 }
3806
3807 static int
3808 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3809 {
3810 unsigned long flags;
3811
3812 spin_lock_irqsave(&vha->work_lock, flags);
3813 list_add_tail(&e->list, &vha->work_list);
3814 spin_unlock_irqrestore(&vha->work_lock, flags);
3815 qla2xxx_wake_dpc(vha);
3816
3817 return QLA_SUCCESS;
3818 }
3819
3820 int
3821 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3822 u32 data)
3823 {
3824 struct qla_work_evt *e;
3825
3826 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3827 if (!e)
3828 return QLA_FUNCTION_FAILED;
3829
3830 e->u.aen.code = code;
3831 e->u.aen.data = data;
3832 return qla2x00_post_work(vha, e);
3833 }
3834
3835 int
3836 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3837 {
3838 struct qla_work_evt *e;
3839
3840 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3841 if (!e)
3842 return QLA_FUNCTION_FAILED;
3843
3844 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3845 return qla2x00_post_work(vha, e);
3846 }
3847
3848 #define qla2x00_post_async_work(name, type) \
3849 int qla2x00_post_async_##name##_work( \
3850 struct scsi_qla_host *vha, \
3851 fc_port_t *fcport, uint16_t *data) \
3852 { \
3853 struct qla_work_evt *e; \
3854 \
3855 e = qla2x00_alloc_work(vha, type); \
3856 if (!e) \
3857 return QLA_FUNCTION_FAILED; \
3858 \
3859 e->u.logio.fcport = fcport; \
3860 if (data) { \
3861 e->u.logio.data[0] = data[0]; \
3862 e->u.logio.data[1] = data[1]; \
3863 } \
3864 return qla2x00_post_work(vha, e); \
3865 }
3866
3867 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3868 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3869 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3870 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3871 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3872 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3873
3874 int
3875 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3876 {
3877 struct qla_work_evt *e;
3878
3879 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3880 if (!e)
3881 return QLA_FUNCTION_FAILED;
3882
3883 e->u.uevent.code = code;
3884 return qla2x00_post_work(vha, e);
3885 }
3886
3887 static void
3888 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3889 {
3890 char event_string[40];
3891 char *envp[] = { event_string, NULL };
3892
3893 switch (code) {
3894 case QLA_UEVENT_CODE_FW_DUMP:
3895 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3896 vha->host_no);
3897 break;
3898 default:
3899 /* do nothing */
3900 break;
3901 }
3902 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3903 }
3904
3905 int
3906 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3907 uint32_t *data, int cnt)
3908 {
3909 struct qla_work_evt *e;
3910
3911 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3912 if (!e)
3913 return QLA_FUNCTION_FAILED;
3914
3915 e->u.aenfx.evtcode = evtcode;
3916 e->u.aenfx.count = cnt;
3917 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3918 return qla2x00_post_work(vha, e);
3919 }
3920
3921 void
3922 qla2x00_do_work(struct scsi_qla_host *vha)
3923 {
3924 struct qla_work_evt *e, *tmp;
3925 unsigned long flags;
3926 LIST_HEAD(work);
3927
3928 spin_lock_irqsave(&vha->work_lock, flags);
3929 list_splice_init(&vha->work_list, &work);
3930 spin_unlock_irqrestore(&vha->work_lock, flags);
3931
3932 list_for_each_entry_safe(e, tmp, &work, list) {
3933 list_del_init(&e->list);
3934
3935 switch (e->type) {
3936 case QLA_EVT_AEN:
3937 fc_host_post_event(vha->host, fc_get_event_number(),
3938 e->u.aen.code, e->u.aen.data);
3939 break;
3940 case QLA_EVT_IDC_ACK:
3941 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3942 break;
3943 case QLA_EVT_ASYNC_LOGIN:
3944 qla2x00_async_login(vha, e->u.logio.fcport,
3945 e->u.logio.data);
3946 break;
3947 case QLA_EVT_ASYNC_LOGIN_DONE:
3948 qla2x00_async_login_done(vha, e->u.logio.fcport,
3949 e->u.logio.data);
3950 break;
3951 case QLA_EVT_ASYNC_LOGOUT:
3952 qla2x00_async_logout(vha, e->u.logio.fcport);
3953 break;
3954 case QLA_EVT_ASYNC_LOGOUT_DONE:
3955 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3956 e->u.logio.data);
3957 break;
3958 case QLA_EVT_ASYNC_ADISC:
3959 qla2x00_async_adisc(vha, e->u.logio.fcport,
3960 e->u.logio.data);
3961 break;
3962 case QLA_EVT_ASYNC_ADISC_DONE:
3963 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3964 e->u.logio.data);
3965 break;
3966 case QLA_EVT_UEVENT:
3967 qla2x00_uevent_emit(vha, e->u.uevent.code);
3968 break;
3969 case QLA_EVT_AENFX:
3970 qlafx00_process_aen(vha, e);
3971 break;
3972 }
3973 if (e->flags & QLA_EVT_FLAG_FREE)
3974 kfree(e);
3975
3976 /* For each work completed decrement vha ref count */
3977 QLA_VHA_MARK_NOT_BUSY(vha);
3978 }
3979 }
3980
3981 /* Relogins all the fcports of a vport
3982 * Context: dpc thread
3983 */
3984 void qla2x00_relogin(struct scsi_qla_host *vha)
3985 {
3986 fc_port_t *fcport;
3987 int status;
3988 uint16_t next_loopid = 0;
3989 struct qla_hw_data *ha = vha->hw;
3990 uint16_t data[2];
3991
3992 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3993 /*
3994 * If the port is not ONLINE then try to login
3995 * to it if we haven't run out of retries.
3996 */
3997 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3998 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
3999 fcport->login_retry--;
4000 if (fcport->flags & FCF_FABRIC_DEVICE) {
4001 if (fcport->flags & FCF_FCP2_DEVICE)
4002 ha->isp_ops->fabric_logout(vha,
4003 fcport->loop_id,
4004 fcport->d_id.b.domain,
4005 fcport->d_id.b.area,
4006 fcport->d_id.b.al_pa);
4007
4008 if (fcport->loop_id == FC_NO_LOOP_ID) {
4009 fcport->loop_id = next_loopid =
4010 ha->min_external_loopid;
4011 status = qla2x00_find_new_loop_id(
4012 vha, fcport);
4013 if (status != QLA_SUCCESS) {
4014 /* Ran out of IDs to use */
4015 break;
4016 }
4017 }
4018
4019 if (IS_ALOGIO_CAPABLE(ha)) {
4020 fcport->flags |= FCF_ASYNC_SENT;
4021 data[0] = 0;
4022 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4023 status = qla2x00_post_async_login_work(
4024 vha, fcport, data);
4025 if (status == QLA_SUCCESS)
4026 continue;
4027 /* Attempt a retry. */
4028 status = 1;
4029 } else {
4030 status = qla2x00_fabric_login(vha,
4031 fcport, &next_loopid);
4032 if (status == QLA_SUCCESS) {
4033 int status2;
4034 uint8_t opts;
4035
4036 opts = 0;
4037 if (fcport->flags &
4038 FCF_FCP2_DEVICE)
4039 opts |= BIT_1;
4040 status2 =
4041 qla2x00_get_port_database(
4042 vha, fcport, opts);
4043 if (status2 != QLA_SUCCESS)
4044 status = 1;
4045 }
4046 }
4047 } else
4048 status = qla2x00_local_device_login(vha,
4049 fcport);
4050
4051 if (status == QLA_SUCCESS) {
4052 fcport->old_loop_id = fcport->loop_id;
4053
4054 ql_dbg(ql_dbg_disc, vha, 0x2003,
4055 "Port login OK: logged in ID 0x%x.\n",
4056 fcport->loop_id);
4057
4058 qla2x00_update_fcport(vha, fcport);
4059
4060 } else if (status == 1) {
4061 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4062 /* retry the login again */
4063 ql_dbg(ql_dbg_disc, vha, 0x2007,
4064 "Retrying %d login again loop_id 0x%x.\n",
4065 fcport->login_retry, fcport->loop_id);
4066 } else {
4067 fcport->login_retry = 0;
4068 }
4069
4070 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4071 qla2x00_clear_loop_id(fcport);
4072 }
4073 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4074 break;
4075 }
4076 }
4077
4078 /* Schedule work on any of the dpc-workqueues */
4079 void
4080 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4081 {
4082 struct qla_hw_data *ha = base_vha->hw;
4083
4084 switch (work_code) {
4085 case MBA_IDC_AEN: /* 0x8200 */
4086 if (ha->dpc_lp_wq)
4087 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4088 break;
4089
4090 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4091 if (!ha->flags.nic_core_reset_hdlr_active) {
4092 if (ha->dpc_hp_wq)
4093 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4094 } else
4095 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4096 "NIC Core reset is already active. Skip "
4097 "scheduling it again.\n");
4098 break;
4099 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4100 if (ha->dpc_hp_wq)
4101 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4102 break;
4103 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4104 if (ha->dpc_hp_wq)
4105 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4106 break;
4107 default:
4108 ql_log(ql_log_warn, base_vha, 0xb05f,
4109 "Unknown work-code=0x%x.\n", work_code);
4110 }
4111
4112 return;
4113 }
4114
4115 /* Work: Perform NIC Core Unrecoverable state handling */
4116 void
4117 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4118 {
4119 struct qla_hw_data *ha =
4120 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4121 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4122 uint32_t dev_state = 0;
4123
4124 qla83xx_idc_lock(base_vha, 0);
4125 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4126 qla83xx_reset_ownership(base_vha);
4127 if (ha->flags.nic_core_reset_owner) {
4128 ha->flags.nic_core_reset_owner = 0;
4129 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4130 QLA8XXX_DEV_FAILED);
4131 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4132 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4133 }
4134 qla83xx_idc_unlock(base_vha, 0);
4135 }
4136
4137 /* Work: Execute IDC state handler */
4138 void
4139 qla83xx_idc_state_handler_work(struct work_struct *work)
4140 {
4141 struct qla_hw_data *ha =
4142 container_of(work, struct qla_hw_data, idc_state_handler);
4143 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4144 uint32_t dev_state = 0;
4145
4146 qla83xx_idc_lock(base_vha, 0);
4147 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4148 if (dev_state == QLA8XXX_DEV_FAILED ||
4149 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4150 qla83xx_idc_state_handler(base_vha);
4151 qla83xx_idc_unlock(base_vha, 0);
4152 }
4153
4154 static int
4155 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4156 {
4157 int rval = QLA_SUCCESS;
4158 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4159 uint32_t heart_beat_counter1, heart_beat_counter2;
4160
4161 do {
4162 if (time_after(jiffies, heart_beat_wait)) {
4163 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4164 "Nic Core f/w is not alive.\n");
4165 rval = QLA_FUNCTION_FAILED;
4166 break;
4167 }
4168
4169 qla83xx_idc_lock(base_vha, 0);
4170 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4171 &heart_beat_counter1);
4172 qla83xx_idc_unlock(base_vha, 0);
4173 msleep(100);
4174 qla83xx_idc_lock(base_vha, 0);
4175 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4176 &heart_beat_counter2);
4177 qla83xx_idc_unlock(base_vha, 0);
4178 } while (heart_beat_counter1 == heart_beat_counter2);
4179
4180 return rval;
4181 }
4182
4183 /* Work: Perform NIC Core Reset handling */
4184 void
4185 qla83xx_nic_core_reset_work(struct work_struct *work)
4186 {
4187 struct qla_hw_data *ha =
4188 container_of(work, struct qla_hw_data, nic_core_reset);
4189 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4190 uint32_t dev_state = 0;
4191
4192 if (IS_QLA2031(ha)) {
4193 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4194 ql_log(ql_log_warn, base_vha, 0xb081,
4195 "Failed to dump mctp\n");
4196 return;
4197 }
4198
4199 if (!ha->flags.nic_core_reset_hdlr_active) {
4200 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4201 qla83xx_idc_lock(base_vha, 0);
4202 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4203 &dev_state);
4204 qla83xx_idc_unlock(base_vha, 0);
4205 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4206 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4207 "Nic Core f/w is alive.\n");
4208 return;
4209 }
4210 }
4211
4212 ha->flags.nic_core_reset_hdlr_active = 1;
4213 if (qla83xx_nic_core_reset(base_vha)) {
4214 /* NIC Core reset failed. */
4215 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4216 "NIC Core reset failed.\n");
4217 }
4218 ha->flags.nic_core_reset_hdlr_active = 0;
4219 }
4220 }
4221
4222 /* Work: Handle 8200 IDC aens */
4223 void
4224 qla83xx_service_idc_aen(struct work_struct *work)
4225 {
4226 struct qla_hw_data *ha =
4227 container_of(work, struct qla_hw_data, idc_aen);
4228 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4229 uint32_t dev_state, idc_control;
4230
4231 qla83xx_idc_lock(base_vha, 0);
4232 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4233 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4234 qla83xx_idc_unlock(base_vha, 0);
4235 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4236 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4237 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4238 "Application requested NIC Core Reset.\n");
4239 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4240 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4241 QLA_SUCCESS) {
4242 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4243 "Other protocol driver requested NIC Core Reset.\n");
4244 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4245 }
4246 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4247 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4248 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4249 }
4250 }
4251
4252 static void
4253 qla83xx_wait_logic(void)
4254 {
4255 int i;
4256
4257 /* Yield CPU */
4258 if (!in_interrupt()) {
4259 /*
4260 * Wait about 200ms before retrying again.
4261 * This controls the number of retries for single
4262 * lock operation.
4263 */
4264 msleep(100);
4265 schedule();
4266 } else {
4267 for (i = 0; i < 20; i++)
4268 cpu_relax(); /* This a nop instr on i386 */
4269 }
4270 }
4271
4272 static int
4273 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4274 {
4275 int rval;
4276 uint32_t data;
4277 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4278 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4279 struct qla_hw_data *ha = base_vha->hw;
4280 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4281 "Trying force recovery of the IDC lock.\n");
4282
4283 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4284 if (rval)
4285 return rval;
4286
4287 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4288 return QLA_SUCCESS;
4289 } else {
4290 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4291 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4292 data);
4293 if (rval)
4294 return rval;
4295
4296 msleep(200);
4297
4298 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4299 &data);
4300 if (rval)
4301 return rval;
4302
4303 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4304 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4305 ~(idc_lck_rcvry_stage_mask));
4306 rval = qla83xx_wr_reg(base_vha,
4307 QLA83XX_IDC_LOCK_RECOVERY, data);
4308 if (rval)
4309 return rval;
4310
4311 /* Forcefully perform IDC UnLock */
4312 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4313 &data);
4314 if (rval)
4315 return rval;
4316 /* Clear lock-id by setting 0xff */
4317 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4318 0xff);
4319 if (rval)
4320 return rval;
4321 /* Clear lock-recovery by setting 0x0 */
4322 rval = qla83xx_wr_reg(base_vha,
4323 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4324 if (rval)
4325 return rval;
4326 } else
4327 return QLA_SUCCESS;
4328 }
4329
4330 return rval;
4331 }
4332
4333 static int
4334 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4335 {
4336 int rval = QLA_SUCCESS;
4337 uint32_t o_drv_lockid, n_drv_lockid;
4338 unsigned long lock_recovery_timeout;
4339
4340 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4341 retry_lockid:
4342 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4343 if (rval)
4344 goto exit;
4345
4346 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4347 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4348 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4349 return QLA_SUCCESS;
4350 else
4351 return QLA_FUNCTION_FAILED;
4352 }
4353
4354 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4355 if (rval)
4356 goto exit;
4357
4358 if (o_drv_lockid == n_drv_lockid) {
4359 qla83xx_wait_logic();
4360 goto retry_lockid;
4361 } else
4362 return QLA_SUCCESS;
4363
4364 exit:
4365 return rval;
4366 }
4367
4368 void
4369 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4370 {
4371 uint16_t options = (requester_id << 15) | BIT_6;
4372 uint32_t data;
4373 uint32_t lock_owner;
4374 struct qla_hw_data *ha = base_vha->hw;
4375
4376 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4377 retry_lock:
4378 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4379 == QLA_SUCCESS) {
4380 if (data) {
4381 /* Setting lock-id to our function-number */
4382 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4383 ha->portnum);
4384 } else {
4385 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4386 &lock_owner);
4387 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4388 "Failed to acquire IDC lock, acquired by %d, "
4389 "retrying...\n", lock_owner);
4390
4391 /* Retry/Perform IDC-Lock recovery */
4392 if (qla83xx_idc_lock_recovery(base_vha)
4393 == QLA_SUCCESS) {
4394 qla83xx_wait_logic();
4395 goto retry_lock;
4396 } else
4397 ql_log(ql_log_warn, base_vha, 0xb075,
4398 "IDC Lock recovery FAILED.\n");
4399 }
4400
4401 }
4402
4403 return;
4404
4405 /* XXX: IDC-lock implementation using access-control mbx */
4406 retry_lock2:
4407 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4408 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4409 "Failed to acquire IDC lock. retrying...\n");
4410 /* Retry/Perform IDC-Lock recovery */
4411 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4412 qla83xx_wait_logic();
4413 goto retry_lock2;
4414 } else
4415 ql_log(ql_log_warn, base_vha, 0xb076,
4416 "IDC Lock recovery FAILED.\n");
4417 }
4418
4419 return;
4420 }
4421
4422 void
4423 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4424 {
4425 #if 0
4426 uint16_t options = (requester_id << 15) | BIT_7;
4427 #endif
4428 uint16_t retry;
4429 uint32_t data;
4430 struct qla_hw_data *ha = base_vha->hw;
4431
4432 /* IDC-unlock implementation using driver-unlock/lock-id
4433 * remote registers
4434 */
4435 retry = 0;
4436 retry_unlock:
4437 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4438 == QLA_SUCCESS) {
4439 if (data == ha->portnum) {
4440 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4441 /* Clearing lock-id by setting 0xff */
4442 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4443 } else if (retry < 10) {
4444 /* SV: XXX: IDC unlock retrying needed here? */
4445
4446 /* Retry for IDC-unlock */
4447 qla83xx_wait_logic();
4448 retry++;
4449 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4450 "Failed to release IDC lock, retyring=%d\n", retry);
4451 goto retry_unlock;
4452 }
4453 } else if (retry < 10) {
4454 /* Retry for IDC-unlock */
4455 qla83xx_wait_logic();
4456 retry++;
4457 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4458 "Failed to read drv-lockid, retyring=%d\n", retry);
4459 goto retry_unlock;
4460 }
4461
4462 return;
4463
4464 #if 0
4465 /* XXX: IDC-unlock implementation using access-control mbx */
4466 retry = 0;
4467 retry_unlock2:
4468 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4469 if (retry < 10) {
4470 /* Retry for IDC-unlock */
4471 qla83xx_wait_logic();
4472 retry++;
4473 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4474 "Failed to release IDC lock, retyring=%d\n", retry);
4475 goto retry_unlock2;
4476 }
4477 }
4478
4479 return;
4480 #endif
4481 }
4482
4483 int
4484 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4485 {
4486 int rval = QLA_SUCCESS;
4487 struct qla_hw_data *ha = vha->hw;
4488 uint32_t drv_presence;
4489
4490 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4491 if (rval == QLA_SUCCESS) {
4492 drv_presence |= (1 << ha->portnum);
4493 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4494 drv_presence);
4495 }
4496
4497 return rval;
4498 }
4499
4500 int
4501 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4502 {
4503 int rval = QLA_SUCCESS;
4504
4505 qla83xx_idc_lock(vha, 0);
4506 rval = __qla83xx_set_drv_presence(vha);
4507 qla83xx_idc_unlock(vha, 0);
4508
4509 return rval;
4510 }
4511
4512 int
4513 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4514 {
4515 int rval = QLA_SUCCESS;
4516 struct qla_hw_data *ha = vha->hw;
4517 uint32_t drv_presence;
4518
4519 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4520 if (rval == QLA_SUCCESS) {
4521 drv_presence &= ~(1 << ha->portnum);
4522 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4523 drv_presence);
4524 }
4525
4526 return rval;
4527 }
4528
4529 int
4530 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4531 {
4532 int rval = QLA_SUCCESS;
4533
4534 qla83xx_idc_lock(vha, 0);
4535 rval = __qla83xx_clear_drv_presence(vha);
4536 qla83xx_idc_unlock(vha, 0);
4537
4538 return rval;
4539 }
4540
4541 static void
4542 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4543 {
4544 struct qla_hw_data *ha = vha->hw;
4545 uint32_t drv_ack, drv_presence;
4546 unsigned long ack_timeout;
4547
4548 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4549 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4550 while (1) {
4551 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4552 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4553 if ((drv_ack & drv_presence) == drv_presence)
4554 break;
4555
4556 if (time_after_eq(jiffies, ack_timeout)) {
4557 ql_log(ql_log_warn, vha, 0xb067,
4558 "RESET ACK TIMEOUT! drv_presence=0x%x "
4559 "drv_ack=0x%x\n", drv_presence, drv_ack);
4560 /*
4561 * The function(s) which did not ack in time are forced
4562 * to withdraw any further participation in the IDC
4563 * reset.
4564 */
4565 if (drv_ack != drv_presence)
4566 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4567 drv_ack);
4568 break;
4569 }
4570
4571 qla83xx_idc_unlock(vha, 0);
4572 msleep(1000);
4573 qla83xx_idc_lock(vha, 0);
4574 }
4575
4576 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4577 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4578 }
4579
4580 static int
4581 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4582 {
4583 int rval = QLA_SUCCESS;
4584 uint32_t idc_control;
4585
4586 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4587 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4588
4589 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4590 __qla83xx_get_idc_control(vha, &idc_control);
4591 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4592 __qla83xx_set_idc_control(vha, 0);
4593
4594 qla83xx_idc_unlock(vha, 0);
4595 rval = qla83xx_restart_nic_firmware(vha);
4596 qla83xx_idc_lock(vha, 0);
4597
4598 if (rval != QLA_SUCCESS) {
4599 ql_log(ql_log_fatal, vha, 0xb06a,
4600 "Failed to restart NIC f/w.\n");
4601 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4602 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4603 } else {
4604 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4605 "Success in restarting nic f/w.\n");
4606 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4607 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4608 }
4609
4610 return rval;
4611 }
4612
4613 /* Assumes idc_lock always held on entry */
4614 int
4615 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4616 {
4617 struct qla_hw_data *ha = base_vha->hw;
4618 int rval = QLA_SUCCESS;
4619 unsigned long dev_init_timeout;
4620 uint32_t dev_state;
4621
4622 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4623 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4624
4625 while (1) {
4626
4627 if (time_after_eq(jiffies, dev_init_timeout)) {
4628 ql_log(ql_log_warn, base_vha, 0xb06e,
4629 "Initialization TIMEOUT!\n");
4630 /* Init timeout. Disable further NIC Core
4631 * communication.
4632 */
4633 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4634 QLA8XXX_DEV_FAILED);
4635 ql_log(ql_log_info, base_vha, 0xb06f,
4636 "HW State: FAILED.\n");
4637 }
4638
4639 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4640 switch (dev_state) {
4641 case QLA8XXX_DEV_READY:
4642 if (ha->flags.nic_core_reset_owner)
4643 qla83xx_idc_audit(base_vha,
4644 IDC_AUDIT_COMPLETION);
4645 ha->flags.nic_core_reset_owner = 0;
4646 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4647 "Reset_owner reset by 0x%x.\n",
4648 ha->portnum);
4649 goto exit;
4650 case QLA8XXX_DEV_COLD:
4651 if (ha->flags.nic_core_reset_owner)
4652 rval = qla83xx_device_bootstrap(base_vha);
4653 else {
4654 /* Wait for AEN to change device-state */
4655 qla83xx_idc_unlock(base_vha, 0);
4656 msleep(1000);
4657 qla83xx_idc_lock(base_vha, 0);
4658 }
4659 break;
4660 case QLA8XXX_DEV_INITIALIZING:
4661 /* Wait for AEN to change device-state */
4662 qla83xx_idc_unlock(base_vha, 0);
4663 msleep(1000);
4664 qla83xx_idc_lock(base_vha, 0);
4665 break;
4666 case QLA8XXX_DEV_NEED_RESET:
4667 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4668 qla83xx_need_reset_handler(base_vha);
4669 else {
4670 /* Wait for AEN to change device-state */
4671 qla83xx_idc_unlock(base_vha, 0);
4672 msleep(1000);
4673 qla83xx_idc_lock(base_vha, 0);
4674 }
4675 /* reset timeout value after need reset handler */
4676 dev_init_timeout = jiffies +
4677 (ha->fcoe_dev_init_timeout * HZ);
4678 break;
4679 case QLA8XXX_DEV_NEED_QUIESCENT:
4680 /* XXX: DEBUG for now */
4681 qla83xx_idc_unlock(base_vha, 0);
4682 msleep(1000);
4683 qla83xx_idc_lock(base_vha, 0);
4684 break;
4685 case QLA8XXX_DEV_QUIESCENT:
4686 /* XXX: DEBUG for now */
4687 if (ha->flags.quiesce_owner)
4688 goto exit;
4689
4690 qla83xx_idc_unlock(base_vha, 0);
4691 msleep(1000);
4692 qla83xx_idc_lock(base_vha, 0);
4693 dev_init_timeout = jiffies +
4694 (ha->fcoe_dev_init_timeout * HZ);
4695 break;
4696 case QLA8XXX_DEV_FAILED:
4697 if (ha->flags.nic_core_reset_owner)
4698 qla83xx_idc_audit(base_vha,
4699 IDC_AUDIT_COMPLETION);
4700 ha->flags.nic_core_reset_owner = 0;
4701 __qla83xx_clear_drv_presence(base_vha);
4702 qla83xx_idc_unlock(base_vha, 0);
4703 qla8xxx_dev_failed_handler(base_vha);
4704 rval = QLA_FUNCTION_FAILED;
4705 qla83xx_idc_lock(base_vha, 0);
4706 goto exit;
4707 case QLA8XXX_BAD_VALUE:
4708 qla83xx_idc_unlock(base_vha, 0);
4709 msleep(1000);
4710 qla83xx_idc_lock(base_vha, 0);
4711 break;
4712 default:
4713 ql_log(ql_log_warn, base_vha, 0xb071,
4714 "Unknown Device State: %x.\n", dev_state);
4715 qla83xx_idc_unlock(base_vha, 0);
4716 qla8xxx_dev_failed_handler(base_vha);
4717 rval = QLA_FUNCTION_FAILED;
4718 qla83xx_idc_lock(base_vha, 0);
4719 goto exit;
4720 }
4721 }
4722
4723 exit:
4724 return rval;
4725 }
4726
4727 void
4728 qla2x00_disable_board_on_pci_error(struct work_struct *work)
4729 {
4730 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4731 board_disable);
4732 struct pci_dev *pdev = ha->pdev;
4733 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4734
4735 ql_log(ql_log_warn, base_vha, 0x015b,
4736 "Disabling adapter.\n");
4737
4738 set_bit(UNLOADING, &base_vha->dpc_flags);
4739
4740 qla2x00_delete_all_vps(ha, base_vha);
4741
4742 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4743
4744 qla2x00_dfs_remove(base_vha);
4745
4746 qla84xx_put_chip(base_vha);
4747
4748 if (base_vha->timer_active)
4749 qla2x00_stop_timer(base_vha);
4750
4751 base_vha->flags.online = 0;
4752
4753 qla2x00_destroy_deferred_work(ha);
4754
4755 /*
4756 * Do not try to stop beacon blink as it will issue a mailbox
4757 * command.
4758 */
4759 qla2x00_free_sysfs_attr(base_vha, false);
4760
4761 fc_remove_host(base_vha->host);
4762
4763 scsi_remove_host(base_vha->host);
4764
4765 base_vha->flags.init_done = 0;
4766 qla25xx_delete_queues(base_vha);
4767 qla2x00_free_irqs(base_vha);
4768 qla2x00_free_fcports(base_vha);
4769 qla2x00_mem_free(ha);
4770 qla82xx_md_free(base_vha);
4771 qla2x00_free_queues(ha);
4772
4773 qla2x00_unmap_iobases(ha);
4774
4775 pci_release_selected_regions(ha->pdev, ha->bars);
4776 pci_disable_pcie_error_reporting(pdev);
4777 pci_disable_device(pdev);
4778
4779 /*
4780 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4781 */
4782 }
4783
4784 /**************************************************************************
4785 * qla2x00_do_dpc
4786 * This kernel thread is a task that is schedule by the interrupt handler
4787 * to perform the background processing for interrupts.
4788 *
4789 * Notes:
4790 * This task always run in the context of a kernel thread. It
4791 * is kick-off by the driver's detect code and starts up
4792 * up one per adapter. It immediately goes to sleep and waits for
4793 * some fibre event. When either the interrupt handler or
4794 * the timer routine detects a event it will one of the task
4795 * bits then wake us up.
4796 **************************************************************************/
4797 static int
4798 qla2x00_do_dpc(void *data)
4799 {
4800 scsi_qla_host_t *base_vha;
4801 struct qla_hw_data *ha;
4802
4803 ha = (struct qla_hw_data *)data;
4804 base_vha = pci_get_drvdata(ha->pdev);
4805
4806 set_user_nice(current, MIN_NICE);
4807
4808 set_current_state(TASK_INTERRUPTIBLE);
4809 while (!kthread_should_stop()) {
4810 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4811 "DPC handler sleeping.\n");
4812
4813 schedule();
4814
4815 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4816 goto end_loop;
4817
4818 if (ha->flags.eeh_busy) {
4819 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4820 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4821 goto end_loop;
4822 }
4823
4824 ha->dpc_active = 1;
4825
4826 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4827 "DPC handler waking up, dpc_flags=0x%lx.\n",
4828 base_vha->dpc_flags);
4829
4830 qla2x00_do_work(base_vha);
4831
4832 if (IS_P3P_TYPE(ha)) {
4833 if (IS_QLA8044(ha)) {
4834 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4835 &base_vha->dpc_flags)) {
4836 qla8044_idc_lock(ha);
4837 qla8044_wr_direct(base_vha,
4838 QLA8044_CRB_DEV_STATE_INDEX,
4839 QLA8XXX_DEV_FAILED);
4840 qla8044_idc_unlock(ha);
4841 ql_log(ql_log_info, base_vha, 0x4004,
4842 "HW State: FAILED.\n");
4843 qla8044_device_state_handler(base_vha);
4844 continue;
4845 }
4846
4847 } else {
4848 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4849 &base_vha->dpc_flags)) {
4850 qla82xx_idc_lock(ha);
4851 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4852 QLA8XXX_DEV_FAILED);
4853 qla82xx_idc_unlock(ha);
4854 ql_log(ql_log_info, base_vha, 0x0151,
4855 "HW State: FAILED.\n");
4856 qla82xx_device_state_handler(base_vha);
4857 continue;
4858 }
4859 }
4860
4861 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4862 &base_vha->dpc_flags)) {
4863
4864 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4865 "FCoE context reset scheduled.\n");
4866 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4867 &base_vha->dpc_flags))) {
4868 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4869 /* FCoE-ctx reset failed.
4870 * Escalate to chip-reset
4871 */
4872 set_bit(ISP_ABORT_NEEDED,
4873 &base_vha->dpc_flags);
4874 }
4875 clear_bit(ABORT_ISP_ACTIVE,
4876 &base_vha->dpc_flags);
4877 }
4878
4879 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4880 "FCoE context reset end.\n");
4881 }
4882 } else if (IS_QLAFX00(ha)) {
4883 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4884 &base_vha->dpc_flags)) {
4885 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4886 "Firmware Reset Recovery\n");
4887 if (qlafx00_reset_initialize(base_vha)) {
4888 /* Failed. Abort isp later. */
4889 if (!test_bit(UNLOADING,
4890 &base_vha->dpc_flags)) {
4891 set_bit(ISP_UNRECOVERABLE,
4892 &base_vha->dpc_flags);
4893 ql_dbg(ql_dbg_dpc, base_vha,
4894 0x4021,
4895 "Reset Recovery Failed\n");
4896 }
4897 }
4898 }
4899
4900 if (test_and_clear_bit(FX00_TARGET_SCAN,
4901 &base_vha->dpc_flags)) {
4902 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4903 "ISPFx00 Target Scan scheduled\n");
4904 if (qlafx00_rescan_isp(base_vha)) {
4905 if (!test_bit(UNLOADING,
4906 &base_vha->dpc_flags))
4907 set_bit(ISP_UNRECOVERABLE,
4908 &base_vha->dpc_flags);
4909 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4910 "ISPFx00 Target Scan Failed\n");
4911 }
4912 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4913 "ISPFx00 Target Scan End\n");
4914 }
4915 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4916 &base_vha->dpc_flags)) {
4917 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4918 "ISPFx00 Host Info resend scheduled\n");
4919 qlafx00_fx_disc(base_vha,
4920 &base_vha->hw->mr.fcport,
4921 FXDISC_REG_HOST_INFO);
4922 }
4923 }
4924
4925 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4926 &base_vha->dpc_flags)) {
4927
4928 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4929 "ISP abort scheduled.\n");
4930 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4931 &base_vha->dpc_flags))) {
4932
4933 if (ha->isp_ops->abort_isp(base_vha)) {
4934 /* failed. retry later */
4935 set_bit(ISP_ABORT_NEEDED,
4936 &base_vha->dpc_flags);
4937 }
4938 clear_bit(ABORT_ISP_ACTIVE,
4939 &base_vha->dpc_flags);
4940 }
4941
4942 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4943 "ISP abort end.\n");
4944 }
4945
4946 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4947 &base_vha->dpc_flags)) {
4948 qla2x00_update_fcports(base_vha);
4949 }
4950
4951 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4952 int ret;
4953 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4954 if (ret != QLA_SUCCESS)
4955 ql_log(ql_log_warn, base_vha, 0x121,
4956 "Failed to enable receiving of RSCN "
4957 "requests: 0x%x.\n", ret);
4958 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4959 }
4960
4961 if (IS_QLAFX00(ha))
4962 goto loop_resync_check;
4963
4964 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4965 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4966 "Quiescence mode scheduled.\n");
4967 if (IS_P3P_TYPE(ha)) {
4968 if (IS_QLA82XX(ha))
4969 qla82xx_device_state_handler(base_vha);
4970 if (IS_QLA8044(ha))
4971 qla8044_device_state_handler(base_vha);
4972 clear_bit(ISP_QUIESCE_NEEDED,
4973 &base_vha->dpc_flags);
4974 if (!ha->flags.quiesce_owner) {
4975 qla2x00_perform_loop_resync(base_vha);
4976 if (IS_QLA82XX(ha)) {
4977 qla82xx_idc_lock(ha);
4978 qla82xx_clear_qsnt_ready(
4979 base_vha);
4980 qla82xx_idc_unlock(ha);
4981 } else if (IS_QLA8044(ha)) {
4982 qla8044_idc_lock(ha);
4983 qla8044_clear_qsnt_ready(
4984 base_vha);
4985 qla8044_idc_unlock(ha);
4986 }
4987 }
4988 } else {
4989 clear_bit(ISP_QUIESCE_NEEDED,
4990 &base_vha->dpc_flags);
4991 qla2x00_quiesce_io(base_vha);
4992 }
4993 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4994 "Quiescence mode end.\n");
4995 }
4996
4997 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4998 &base_vha->dpc_flags) &&
4999 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
5000
5001 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5002 "Reset marker scheduled.\n");
5003 qla2x00_rst_aen(base_vha);
5004 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
5005 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5006 "Reset marker end.\n");
5007 }
5008
5009 /* Retry each device up to login retry count */
5010 if ((test_and_clear_bit(RELOGIN_NEEDED,
5011 &base_vha->dpc_flags)) &&
5012 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5013 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
5014
5015 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5016 "Relogin scheduled.\n");
5017 qla2x00_relogin(base_vha);
5018 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5019 "Relogin end.\n");
5020 }
5021 loop_resync_check:
5022 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
5023 &base_vha->dpc_flags)) {
5024
5025 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5026 "Loop resync scheduled.\n");
5027
5028 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
5029 &base_vha->dpc_flags))) {
5030
5031 qla2x00_loop_resync(base_vha);
5032
5033 clear_bit(LOOP_RESYNC_ACTIVE,
5034 &base_vha->dpc_flags);
5035 }
5036
5037 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5038 "Loop resync end.\n");
5039 }
5040
5041 if (IS_QLAFX00(ha))
5042 goto intr_on_check;
5043
5044 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5045 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5046 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5047 qla2xxx_flash_npiv_conf(base_vha);
5048 }
5049
5050 intr_on_check:
5051 if (!ha->interrupts_on)
5052 ha->isp_ops->enable_intrs(ha);
5053
5054 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5055 &base_vha->dpc_flags)) {
5056 if (ha->beacon_blink_led == 1)
5057 ha->isp_ops->beacon_blink(base_vha);
5058 }
5059
5060 if (!IS_QLAFX00(ha))
5061 qla2x00_do_dpc_all_vps(base_vha);
5062
5063 ha->dpc_active = 0;
5064 end_loop:
5065 set_current_state(TASK_INTERRUPTIBLE);
5066 } /* End of while(1) */
5067 __set_current_state(TASK_RUNNING);
5068
5069 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5070 "DPC handler exiting.\n");
5071
5072 /*
5073 * Make sure that nobody tries to wake us up again.
5074 */
5075 ha->dpc_active = 0;
5076
5077 /* Cleanup any residual CTX SRBs. */
5078 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5079
5080 return 0;
5081 }
5082
5083 void
5084 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5085 {
5086 struct qla_hw_data *ha = vha->hw;
5087 struct task_struct *t = ha->dpc_thread;
5088
5089 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5090 wake_up_process(t);
5091 }
5092
5093 /*
5094 * qla2x00_rst_aen
5095 * Processes asynchronous reset.
5096 *
5097 * Input:
5098 * ha = adapter block pointer.
5099 */
5100 static void
5101 qla2x00_rst_aen(scsi_qla_host_t *vha)
5102 {
5103 if (vha->flags.online && !vha->flags.reset_active &&
5104 !atomic_read(&vha->loop_down_timer) &&
5105 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5106 do {
5107 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5108
5109 /*
5110 * Issue marker command only when we are going to start
5111 * the I/O.
5112 */
5113 vha->marker_needed = 1;
5114 } while (!atomic_read(&vha->loop_down_timer) &&
5115 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5116 }
5117 }
5118
5119 /**************************************************************************
5120 * qla2x00_timer
5121 *
5122 * Description:
5123 * One second timer
5124 *
5125 * Context: Interrupt
5126 ***************************************************************************/
5127 void
5128 qla2x00_timer(scsi_qla_host_t *vha)
5129 {
5130 unsigned long cpu_flags = 0;
5131 int start_dpc = 0;
5132 int index;
5133 srb_t *sp;
5134 uint16_t w;
5135 struct qla_hw_data *ha = vha->hw;
5136 struct req_que *req;
5137
5138 if (ha->flags.eeh_busy) {
5139 ql_dbg(ql_dbg_timer, vha, 0x6000,
5140 "EEH = %d, restarting timer.\n",
5141 ha->flags.eeh_busy);
5142 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5143 return;
5144 }
5145
5146 /*
5147 * Hardware read to raise pending EEH errors during mailbox waits. If
5148 * the read returns -1 then disable the board.
5149 */
5150 if (!pci_channel_offline(ha->pdev)) {
5151 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5152 qla2x00_check_reg16_for_disconnect(vha, w);
5153 }
5154
5155 /* Make sure qla82xx_watchdog is run only for physical port */
5156 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5157 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5158 start_dpc++;
5159 if (IS_QLA82XX(ha))
5160 qla82xx_watchdog(vha);
5161 else if (IS_QLA8044(ha))
5162 qla8044_watchdog(vha);
5163 }
5164
5165 if (!vha->vp_idx && IS_QLAFX00(ha))
5166 qlafx00_timer_routine(vha);
5167
5168 /* Loop down handler. */
5169 if (atomic_read(&vha->loop_down_timer) > 0 &&
5170 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5171 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5172 && vha->flags.online) {
5173
5174 if (atomic_read(&vha->loop_down_timer) ==
5175 vha->loop_down_abort_time) {
5176
5177 ql_log(ql_log_info, vha, 0x6008,
5178 "Loop down - aborting the queues before time expires.\n");
5179
5180 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5181 atomic_set(&vha->loop_state, LOOP_DEAD);
5182
5183 /*
5184 * Schedule an ISP abort to return any FCP2-device
5185 * commands.
5186 */
5187 /* NPIV - scan physical port only */
5188 if (!vha->vp_idx) {
5189 spin_lock_irqsave(&ha->hardware_lock,
5190 cpu_flags);
5191 req = ha->req_q_map[0];
5192 for (index = 1;
5193 index < req->num_outstanding_cmds;
5194 index++) {
5195 fc_port_t *sfcp;
5196
5197 sp = req->outstanding_cmds[index];
5198 if (!sp)
5199 continue;
5200 if (sp->type != SRB_SCSI_CMD)
5201 continue;
5202 sfcp = sp->fcport;
5203 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5204 continue;
5205
5206 if (IS_QLA82XX(ha))
5207 set_bit(FCOE_CTX_RESET_NEEDED,
5208 &vha->dpc_flags);
5209 else
5210 set_bit(ISP_ABORT_NEEDED,
5211 &vha->dpc_flags);
5212 break;
5213 }
5214 spin_unlock_irqrestore(&ha->hardware_lock,
5215 cpu_flags);
5216 }
5217 start_dpc++;
5218 }
5219
5220 /* if the loop has been down for 4 minutes, reinit adapter */
5221 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5222 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5223 ql_log(ql_log_warn, vha, 0x6009,
5224 "Loop down - aborting ISP.\n");
5225
5226 if (IS_QLA82XX(ha))
5227 set_bit(FCOE_CTX_RESET_NEEDED,
5228 &vha->dpc_flags);
5229 else
5230 set_bit(ISP_ABORT_NEEDED,
5231 &vha->dpc_flags);
5232 }
5233 }
5234 ql_dbg(ql_dbg_timer, vha, 0x600a,
5235 "Loop down - seconds remaining %d.\n",
5236 atomic_read(&vha->loop_down_timer));
5237 }
5238 /* Check if beacon LED needs to be blinked for physical host only */
5239 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5240 /* There is no beacon_blink function for ISP82xx */
5241 if (!IS_P3P_TYPE(ha)) {
5242 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5243 start_dpc++;
5244 }
5245 }
5246
5247 /* Process any deferred work. */
5248 if (!list_empty(&vha->work_list))
5249 start_dpc++;
5250
5251 /* Schedule the DPC routine if needed */
5252 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5253 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5254 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5255 start_dpc ||
5256 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5257 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5258 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5259 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5260 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5261 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
5262 ql_dbg(ql_dbg_timer, vha, 0x600b,
5263 "isp_abort_needed=%d loop_resync_needed=%d "
5264 "fcport_update_needed=%d start_dpc=%d "
5265 "reset_marker_needed=%d",
5266 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5267 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5268 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5269 start_dpc,
5270 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5271 ql_dbg(ql_dbg_timer, vha, 0x600c,
5272 "beacon_blink_needed=%d isp_unrecoverable=%d "
5273 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5274 "relogin_needed=%d.\n",
5275 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5276 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5277 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5278 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5279 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
5280 qla2xxx_wake_dpc(vha);
5281 }
5282
5283 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5284 }
5285
5286 /* Firmware interface routines. */
5287
5288 #define FW_BLOBS 11
5289 #define FW_ISP21XX 0
5290 #define FW_ISP22XX 1
5291 #define FW_ISP2300 2
5292 #define FW_ISP2322 3
5293 #define FW_ISP24XX 4
5294 #define FW_ISP25XX 5
5295 #define FW_ISP81XX 6
5296 #define FW_ISP82XX 7
5297 #define FW_ISP2031 8
5298 #define FW_ISP8031 9
5299 #define FW_ISP27XX 10
5300
5301 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5302 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5303 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5304 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5305 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5306 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5307 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5308 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5309 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5310 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5311 #define FW_FILE_ISP27XX "ql2700_fw.bin"
5312
5313
5314 static DEFINE_MUTEX(qla_fw_lock);
5315
5316 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5317 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5318 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5319 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5320 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5321 { .name = FW_FILE_ISP24XX, },
5322 { .name = FW_FILE_ISP25XX, },
5323 { .name = FW_FILE_ISP81XX, },
5324 { .name = FW_FILE_ISP82XX, },
5325 { .name = FW_FILE_ISP2031, },
5326 { .name = FW_FILE_ISP8031, },
5327 { .name = FW_FILE_ISP27XX, },
5328 };
5329
5330 struct fw_blob *
5331 qla2x00_request_firmware(scsi_qla_host_t *vha)
5332 {
5333 struct qla_hw_data *ha = vha->hw;
5334 struct fw_blob *blob;
5335
5336 if (IS_QLA2100(ha)) {
5337 blob = &qla_fw_blobs[FW_ISP21XX];
5338 } else if (IS_QLA2200(ha)) {
5339 blob = &qla_fw_blobs[FW_ISP22XX];
5340 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5341 blob = &qla_fw_blobs[FW_ISP2300];
5342 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5343 blob = &qla_fw_blobs[FW_ISP2322];
5344 } else if (IS_QLA24XX_TYPE(ha)) {
5345 blob = &qla_fw_blobs[FW_ISP24XX];
5346 } else if (IS_QLA25XX(ha)) {
5347 blob = &qla_fw_blobs[FW_ISP25XX];
5348 } else if (IS_QLA81XX(ha)) {
5349 blob = &qla_fw_blobs[FW_ISP81XX];
5350 } else if (IS_QLA82XX(ha)) {
5351 blob = &qla_fw_blobs[FW_ISP82XX];
5352 } else if (IS_QLA2031(ha)) {
5353 blob = &qla_fw_blobs[FW_ISP2031];
5354 } else if (IS_QLA8031(ha)) {
5355 blob = &qla_fw_blobs[FW_ISP8031];
5356 } else if (IS_QLA27XX(ha)) {
5357 blob = &qla_fw_blobs[FW_ISP27XX];
5358 } else {
5359 return NULL;
5360 }
5361
5362 mutex_lock(&qla_fw_lock);
5363 if (blob->fw)
5364 goto out;
5365
5366 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5367 ql_log(ql_log_warn, vha, 0x0063,
5368 "Failed to load firmware image (%s).\n", blob->name);
5369 blob->fw = NULL;
5370 blob = NULL;
5371 goto out;
5372 }
5373
5374 out:
5375 mutex_unlock(&qla_fw_lock);
5376 return blob;
5377 }
5378
5379 static void
5380 qla2x00_release_firmware(void)
5381 {
5382 int idx;
5383
5384 mutex_lock(&qla_fw_lock);
5385 for (idx = 0; idx < FW_BLOBS; idx++)
5386 release_firmware(qla_fw_blobs[idx].fw);
5387 mutex_unlock(&qla_fw_lock);
5388 }
5389
5390 static pci_ers_result_t
5391 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5392 {
5393 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5394 struct qla_hw_data *ha = vha->hw;
5395
5396 ql_dbg(ql_dbg_aer, vha, 0x9000,
5397 "PCI error detected, state %x.\n", state);
5398
5399 switch (state) {
5400 case pci_channel_io_normal:
5401 ha->flags.eeh_busy = 0;
5402 return PCI_ERS_RESULT_CAN_RECOVER;
5403 case pci_channel_io_frozen:
5404 ha->flags.eeh_busy = 1;
5405 /* For ISP82XX complete any pending mailbox cmd */
5406 if (IS_QLA82XX(ha)) {
5407 ha->flags.isp82xx_fw_hung = 1;
5408 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5409 qla82xx_clear_pending_mbx(vha);
5410 }
5411 qla2x00_free_irqs(vha);
5412 pci_disable_device(pdev);
5413 /* Return back all IOs */
5414 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5415 return PCI_ERS_RESULT_NEED_RESET;
5416 case pci_channel_io_perm_failure:
5417 ha->flags.pci_channel_io_perm_failure = 1;
5418 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5419 return PCI_ERS_RESULT_DISCONNECT;
5420 }
5421 return PCI_ERS_RESULT_NEED_RESET;
5422 }
5423
5424 static pci_ers_result_t
5425 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5426 {
5427 int risc_paused = 0;
5428 uint32_t stat;
5429 unsigned long flags;
5430 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5431 struct qla_hw_data *ha = base_vha->hw;
5432 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5433 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5434
5435 if (IS_QLA82XX(ha))
5436 return PCI_ERS_RESULT_RECOVERED;
5437
5438 spin_lock_irqsave(&ha->hardware_lock, flags);
5439 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5440 stat = RD_REG_DWORD(&reg->hccr);
5441 if (stat & HCCR_RISC_PAUSE)
5442 risc_paused = 1;
5443 } else if (IS_QLA23XX(ha)) {
5444 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5445 if (stat & HSR_RISC_PAUSED)
5446 risc_paused = 1;
5447 } else if (IS_FWI2_CAPABLE(ha)) {
5448 stat = RD_REG_DWORD(&reg24->host_status);
5449 if (stat & HSRX_RISC_PAUSED)
5450 risc_paused = 1;
5451 }
5452 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5453
5454 if (risc_paused) {
5455 ql_log(ql_log_info, base_vha, 0x9003,
5456 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5457 ha->isp_ops->fw_dump(base_vha, 0);
5458
5459 return PCI_ERS_RESULT_NEED_RESET;
5460 } else
5461 return PCI_ERS_RESULT_RECOVERED;
5462 }
5463
5464 static uint32_t
5465 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5466 {
5467 uint32_t rval = QLA_FUNCTION_FAILED;
5468 uint32_t drv_active = 0;
5469 struct qla_hw_data *ha = base_vha->hw;
5470 int fn;
5471 struct pci_dev *other_pdev = NULL;
5472
5473 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5474 "Entered %s.\n", __func__);
5475
5476 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5477
5478 if (base_vha->flags.online) {
5479 /* Abort all outstanding commands,
5480 * so as to be requeued later */
5481 qla2x00_abort_isp_cleanup(base_vha);
5482 }
5483
5484
5485 fn = PCI_FUNC(ha->pdev->devfn);
5486 while (fn > 0) {
5487 fn--;
5488 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5489 "Finding pci device at function = 0x%x.\n", fn);
5490 other_pdev =
5491 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5492 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5493 fn));
5494
5495 if (!other_pdev)
5496 continue;
5497 if (atomic_read(&other_pdev->enable_cnt)) {
5498 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5499 "Found PCI func available and enable at 0x%x.\n",
5500 fn);
5501 pci_dev_put(other_pdev);
5502 break;
5503 }
5504 pci_dev_put(other_pdev);
5505 }
5506
5507 if (!fn) {
5508 /* Reset owner */
5509 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5510 "This devfn is reset owner = 0x%x.\n",
5511 ha->pdev->devfn);
5512 qla82xx_idc_lock(ha);
5513
5514 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5515 QLA8XXX_DEV_INITIALIZING);
5516
5517 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5518 QLA82XX_IDC_VERSION);
5519
5520 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5521 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5522 "drv_active = 0x%x.\n", drv_active);
5523
5524 qla82xx_idc_unlock(ha);
5525 /* Reset if device is not already reset
5526 * drv_active would be 0 if a reset has already been done
5527 */
5528 if (drv_active)
5529 rval = qla82xx_start_firmware(base_vha);
5530 else
5531 rval = QLA_SUCCESS;
5532 qla82xx_idc_lock(ha);
5533
5534 if (rval != QLA_SUCCESS) {
5535 ql_log(ql_log_info, base_vha, 0x900b,
5536 "HW State: FAILED.\n");
5537 qla82xx_clear_drv_active(ha);
5538 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5539 QLA8XXX_DEV_FAILED);
5540 } else {
5541 ql_log(ql_log_info, base_vha, 0x900c,
5542 "HW State: READY.\n");
5543 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5544 QLA8XXX_DEV_READY);
5545 qla82xx_idc_unlock(ha);
5546 ha->flags.isp82xx_fw_hung = 0;
5547 rval = qla82xx_restart_isp(base_vha);
5548 qla82xx_idc_lock(ha);
5549 /* Clear driver state register */
5550 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5551 qla82xx_set_drv_active(base_vha);
5552 }
5553 qla82xx_idc_unlock(ha);
5554 } else {
5555 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5556 "This devfn is not reset owner = 0x%x.\n",
5557 ha->pdev->devfn);
5558 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5559 QLA8XXX_DEV_READY)) {
5560 ha->flags.isp82xx_fw_hung = 0;
5561 rval = qla82xx_restart_isp(base_vha);
5562 qla82xx_idc_lock(ha);
5563 qla82xx_set_drv_active(base_vha);
5564 qla82xx_idc_unlock(ha);
5565 }
5566 }
5567 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5568
5569 return rval;
5570 }
5571
5572 static pci_ers_result_t
5573 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5574 {
5575 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5576 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5577 struct qla_hw_data *ha = base_vha->hw;
5578 struct rsp_que *rsp;
5579 int rc, retries = 10;
5580
5581 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5582 "Slot Reset.\n");
5583
5584 /* Workaround: qla2xxx driver which access hardware earlier
5585 * needs error state to be pci_channel_io_online.
5586 * Otherwise mailbox command timesout.
5587 */
5588 pdev->error_state = pci_channel_io_normal;
5589
5590 pci_restore_state(pdev);
5591
5592 /* pci_restore_state() clears the saved_state flag of the device
5593 * save restored state which resets saved_state flag
5594 */
5595 pci_save_state(pdev);
5596
5597 if (ha->mem_only)
5598 rc = pci_enable_device_mem(pdev);
5599 else
5600 rc = pci_enable_device(pdev);
5601
5602 if (rc) {
5603 ql_log(ql_log_warn, base_vha, 0x9005,
5604 "Can't re-enable PCI device after reset.\n");
5605 goto exit_slot_reset;
5606 }
5607
5608 rsp = ha->rsp_q_map[0];
5609 if (qla2x00_request_irqs(ha, rsp))
5610 goto exit_slot_reset;
5611
5612 if (ha->isp_ops->pci_config(base_vha))
5613 goto exit_slot_reset;
5614
5615 if (IS_QLA82XX(ha)) {
5616 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5617 ret = PCI_ERS_RESULT_RECOVERED;
5618 goto exit_slot_reset;
5619 } else
5620 goto exit_slot_reset;
5621 }
5622
5623 while (ha->flags.mbox_busy && retries--)
5624 msleep(1000);
5625
5626 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5627 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5628 ret = PCI_ERS_RESULT_RECOVERED;
5629 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5630
5631
5632 exit_slot_reset:
5633 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5634 "slot_reset return %x.\n", ret);
5635
5636 return ret;
5637 }
5638
5639 static void
5640 qla2xxx_pci_resume(struct pci_dev *pdev)
5641 {
5642 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5643 struct qla_hw_data *ha = base_vha->hw;
5644 int ret;
5645
5646 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5647 "pci_resume.\n");
5648
5649 ret = qla2x00_wait_for_hba_online(base_vha);
5650 if (ret != QLA_SUCCESS) {
5651 ql_log(ql_log_fatal, base_vha, 0x9002,
5652 "The device failed to resume I/O from slot/link_reset.\n");
5653 }
5654
5655 pci_cleanup_aer_uncorrect_error_status(pdev);
5656
5657 ha->flags.eeh_busy = 0;
5658 }
5659
5660 static void
5661 qla83xx_disable_laser(scsi_qla_host_t *vha)
5662 {
5663 uint32_t reg, data, fn;
5664 struct qla_hw_data *ha = vha->hw;
5665 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5666
5667 /* pci func #/port # */
5668 ql_dbg(ql_dbg_init, vha, 0x004b,
5669 "Disabling Laser for hba: %p\n", vha);
5670
5671 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5672 (BIT_15|BIT_14|BIT_13|BIT_12));
5673
5674 fn = (fn >> 12);
5675
5676 if (fn & 1)
5677 reg = PORT_1_2031;
5678 else
5679 reg = PORT_0_2031;
5680
5681 data = LASER_OFF_2031;
5682
5683 qla83xx_wr_reg(vha, reg, data);
5684 }
5685
5686 static const struct pci_error_handlers qla2xxx_err_handler = {
5687 .error_detected = qla2xxx_pci_error_detected,
5688 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5689 .slot_reset = qla2xxx_pci_slot_reset,
5690 .resume = qla2xxx_pci_resume,
5691 };
5692
5693 static struct pci_device_id qla2xxx_pci_tbl[] = {
5694 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5695 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5696 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5697 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5698 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5716 { 0 },
5717 };
5718 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5719
5720 static struct pci_driver qla2xxx_pci_driver = {
5721 .name = QLA2XXX_DRIVER_NAME,
5722 .driver = {
5723 .owner = THIS_MODULE,
5724 },
5725 .id_table = qla2xxx_pci_tbl,
5726 .probe = qla2x00_probe_one,
5727 .remove = qla2x00_remove_one,
5728 .shutdown = qla2x00_shutdown,
5729 .err_handler = &qla2xxx_err_handler,
5730 };
5731
5732 static const struct file_operations apidev_fops = {
5733 .owner = THIS_MODULE,
5734 .llseek = noop_llseek,
5735 };
5736
5737 /**
5738 * qla2x00_module_init - Module initialization.
5739 **/
5740 static int __init
5741 qla2x00_module_init(void)
5742 {
5743 int ret = 0;
5744
5745 /* Allocate cache for SRBs. */
5746 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5747 SLAB_HWCACHE_ALIGN, NULL);
5748 if (srb_cachep == NULL) {
5749 ql_log(ql_log_fatal, NULL, 0x0001,
5750 "Unable to allocate SRB cache...Failing load!.\n");
5751 return -ENOMEM;
5752 }
5753
5754 /* Initialize target kmem_cache and mem_pools */
5755 ret = qlt_init();
5756 if (ret < 0) {
5757 kmem_cache_destroy(srb_cachep);
5758 return ret;
5759 } else if (ret > 0) {
5760 /*
5761 * If initiator mode is explictly disabled by qlt_init(),
5762 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5763 * performing scsi_scan_target() during LOOP UP event.
5764 */
5765 qla2xxx_transport_functions.disable_target_scan = 1;
5766 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5767 }
5768
5769 /* Derive version string. */
5770 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5771 if (ql2xextended_error_logging)
5772 strcat(qla2x00_version_str, "-debug");
5773
5774 qla2xxx_transport_template =
5775 fc_attach_transport(&qla2xxx_transport_functions);
5776 if (!qla2xxx_transport_template) {
5777 kmem_cache_destroy(srb_cachep);
5778 ql_log(ql_log_fatal, NULL, 0x0002,
5779 "fc_attach_transport failed...Failing load!.\n");
5780 qlt_exit();
5781 return -ENODEV;
5782 }
5783
5784 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5785 if (apidev_major < 0) {
5786 ql_log(ql_log_fatal, NULL, 0x0003,
5787 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5788 }
5789
5790 qla2xxx_transport_vport_template =
5791 fc_attach_transport(&qla2xxx_transport_vport_functions);
5792 if (!qla2xxx_transport_vport_template) {
5793 kmem_cache_destroy(srb_cachep);
5794 qlt_exit();
5795 fc_release_transport(qla2xxx_transport_template);
5796 ql_log(ql_log_fatal, NULL, 0x0004,
5797 "fc_attach_transport vport failed...Failing load!.\n");
5798 return -ENODEV;
5799 }
5800 ql_log(ql_log_info, NULL, 0x0005,
5801 "QLogic Fibre Channel HBA Driver: %s.\n",
5802 qla2x00_version_str);
5803 ret = pci_register_driver(&qla2xxx_pci_driver);
5804 if (ret) {
5805 kmem_cache_destroy(srb_cachep);
5806 qlt_exit();
5807 fc_release_transport(qla2xxx_transport_template);
5808 fc_release_transport(qla2xxx_transport_vport_template);
5809 ql_log(ql_log_fatal, NULL, 0x0006,
5810 "pci_register_driver failed...ret=%d Failing load!.\n",
5811 ret);
5812 }
5813 return ret;
5814 }
5815
5816 /**
5817 * qla2x00_module_exit - Module cleanup.
5818 **/
5819 static void __exit
5820 qla2x00_module_exit(void)
5821 {
5822 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5823 pci_unregister_driver(&qla2xxx_pci_driver);
5824 qla2x00_release_firmware();
5825 kmem_cache_destroy(srb_cachep);
5826 qlt_exit();
5827 if (ctx_cachep)
5828 kmem_cache_destroy(ctx_cachep);
5829 fc_release_transport(qla2xxx_transport_template);
5830 fc_release_transport(qla2xxx_transport_vport_template);
5831 }
5832
5833 module_init(qla2x00_module_init);
5834 module_exit(qla2x00_module_exit);
5835
5836 MODULE_AUTHOR("QLogic Corporation");
5837 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5838 MODULE_LICENSE("GPL");
5839 MODULE_VERSION(QLA2XXX_VERSION);
5840 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5841 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5842 MODULE_FIRMWARE(FW_FILE_ISP2300);
5843 MODULE_FIRMWARE(FW_FILE_ISP2322);
5844 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5845 MODULE_FIRMWARE(FW_FILE_ISP25XX);
5846 MODULE_FIRMWARE(FW_FILE_ISP2031);
5847 MODULE_FIRMWARE(FW_FILE_ISP8031);
5848 MODULE_FIRMWARE(FW_FILE_ISP27XX);
Linux with added FPC-III support