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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / soc / tegra / pmc.c
blobbc34cf7482fb559c6fcfdece56a5b4d88c24266b
1 /*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
21
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
30 #include <linux/io.h>
31 #include <linux/of.h>
32 #include <linux/of_address.h>
33 #include <linux/platform_device.h>
34 #include <linux/reboot.h>
35 #include <linux/reset.h>
36 #include <linux/seq_file.h>
37 #include <linux/spinlock.h>
38
39 #include <soc/tegra/common.h>
40 #include <soc/tegra/fuse.h>
41 #include <soc/tegra/pmc.h>
42
43 #define PMC_CNTRL 0x0
44 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
45 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
46 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
47 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
48 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
49 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
50
51 #define DPD_SAMPLE 0x020
52 #define DPD_SAMPLE_ENABLE (1 << 0)
53 #define DPD_SAMPLE_DISABLE (0 << 0)
54
55 #define PWRGATE_TOGGLE 0x30
56 #define PWRGATE_TOGGLE_START (1 << 8)
57
58 #define REMOVE_CLAMPING 0x34
59
60 #define PWRGATE_STATUS 0x38
61
62 #define PMC_SCRATCH0 0x50
63 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
64 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
65 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
66 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
67 PMC_SCRATCH0_MODE_BOOTLOADER | \
68 PMC_SCRATCH0_MODE_RCM)
69
70 #define PMC_CPUPWRGOOD_TIMER 0xc8
71 #define PMC_CPUPWROFF_TIMER 0xcc
72
73 #define PMC_SCRATCH41 0x140
74
75 #define PMC_SENSOR_CTRL 0x1b0
76 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
77 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
78
79 #define IO_DPD_REQ 0x1b8
80 #define IO_DPD_REQ_CODE_IDLE (0 << 30)
81 #define IO_DPD_REQ_CODE_OFF (1 << 30)
82 #define IO_DPD_REQ_CODE_ON (2 << 30)
83 #define IO_DPD_REQ_CODE_MASK (3 << 30)
84
85 #define IO_DPD_STATUS 0x1bc
86 #define IO_DPD2_REQ 0x1c0
87 #define IO_DPD2_STATUS 0x1c4
88 #define SEL_DPD_TIM 0x1c8
89
90 #define PMC_SCRATCH54 0x258
91 #define PMC_SCRATCH54_DATA_SHIFT 8
92 #define PMC_SCRATCH54_ADDR_SHIFT 0
93
94 #define PMC_SCRATCH55 0x25c
95 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
96 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
97 #define PMC_SCRATCH55_PINMUX_SHIFT 24
98 #define PMC_SCRATCH55_16BITOP (1 << 15)
99 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
100 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
101
102 #define GPU_RG_CNTRL 0x2d4
103
104 struct tegra_pmc_soc {
105 unsigned int num_powergates;
106 const char *const *powergates;
107 unsigned int num_cpu_powergates;
108 const u8 *cpu_powergates;
109
110 bool has_tsense_reset;
111 bool has_gpu_clamps;
112 };
113
114 /**
115 * struct tegra_pmc - NVIDIA Tegra PMC
116 * @base: pointer to I/O remapped register region
117 * @clk: pointer to pclk clock
118 * @rate: currently configured rate of pclk
119 * @suspend_mode: lowest suspend mode available
120 * @cpu_good_time: CPU power good time (in microseconds)
121 * @cpu_off_time: CPU power off time (in microsecends)
122 * @core_osc_time: core power good OSC time (in microseconds)
123 * @core_pmu_time: core power good PMU time (in microseconds)
124 * @core_off_time: core power off time (in microseconds)
125 * @corereq_high: core power request is active-high
126 * @sysclkreq_high: system clock request is active-high
127 * @combined_req: combined power request for CPU & core
128 * @cpu_pwr_good_en: CPU power good signal is enabled
129 * @lp0_vec_phys: physical base address of the LP0 warm boot code
130 * @lp0_vec_size: size of the LP0 warm boot code
131 * @powergates_lock: mutex for power gate register access
132 */
133 struct tegra_pmc {
134 struct device *dev;
135 void __iomem *base;
136 struct clk *clk;
137
138 const struct tegra_pmc_soc *soc;
139
140 unsigned long rate;
141
142 enum tegra_suspend_mode suspend_mode;
143 u32 cpu_good_time;
144 u32 cpu_off_time;
145 u32 core_osc_time;
146 u32 core_pmu_time;
147 u32 core_off_time;
148 bool corereq_high;
149 bool sysclkreq_high;
150 bool combined_req;
151 bool cpu_pwr_good_en;
152 u32 lp0_vec_phys;
153 u32 lp0_vec_size;
154
155 struct mutex powergates_lock;
156 };
157
158 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
159 .base = NULL,
160 .suspend_mode = TEGRA_SUSPEND_NONE,
161 };
162
163 static u32 tegra_pmc_readl(unsigned long offset)
164 {
165 return readl(pmc->base + offset);
166 }
167
168 static void tegra_pmc_writel(u32 value, unsigned long offset)
169 {
170 writel(value, pmc->base + offset);
171 }
172
173 /**
174 * tegra_powergate_set() - set the state of a partition
175 * @id: partition ID
176 * @new_state: new state of the partition
177 */
178 static int tegra_powergate_set(int id, bool new_state)
179 {
180 bool status;
181
182 mutex_lock(&pmc->powergates_lock);
183
184 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
185
186 if (status == new_state) {
187 mutex_unlock(&pmc->powergates_lock);
188 return 0;
189 }
190
191 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
192
193 mutex_unlock(&pmc->powergates_lock);
194
195 return 0;
196 }
197
198 /**
199 * tegra_powergate_power_on() - power on partition
200 * @id: partition ID
201 */
202 int tegra_powergate_power_on(int id)
203 {
204 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
205 return -EINVAL;
206
207 return tegra_powergate_set(id, true);
208 }
209
210 /**
211 * tegra_powergate_power_off() - power off partition
212 * @id: partition ID
213 */
214 int tegra_powergate_power_off(int id)
215 {
216 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
217 return -EINVAL;
218
219 return tegra_powergate_set(id, false);
220 }
221 EXPORT_SYMBOL(tegra_powergate_power_off);
222
223 /**
224 * tegra_powergate_is_powered() - check if partition is powered
225 * @id: partition ID
226 */
227 int tegra_powergate_is_powered(int id)
228 {
229 u32 status;
230
231 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
232 return -EINVAL;
233
234 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
235 return !!status;
236 }
237
238 /**
239 * tegra_powergate_remove_clamping() - remove power clamps for partition
240 * @id: partition ID
241 */
242 int tegra_powergate_remove_clamping(int id)
243 {
244 u32 mask;
245
246 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
247 return -EINVAL;
248
249 /*
250 * On Tegra124 and later, the clamps for the GPU are controlled by a
251 * separate register (with different semantics).
252 */
253 if (id == TEGRA_POWERGATE_3D) {
254 if (pmc->soc->has_gpu_clamps) {
255 tegra_pmc_writel(0, GPU_RG_CNTRL);
256 return 0;
257 }
258 }
259
260 /*
261 * Tegra 2 has a bug where PCIE and VDE clamping masks are
262 * swapped relatively to the partition ids
263 */
264 if (id == TEGRA_POWERGATE_VDEC)
265 mask = (1 << TEGRA_POWERGATE_PCIE);
266 else if (id == TEGRA_POWERGATE_PCIE)
267 mask = (1 << TEGRA_POWERGATE_VDEC);
268 else
269 mask = (1 << id);
270
271 tegra_pmc_writel(mask, REMOVE_CLAMPING);
272
273 return 0;
274 }
275 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
276
277 /**
278 * tegra_powergate_sequence_power_up() - power up partition
279 * @id: partition ID
280 * @clk: clock for partition
281 * @rst: reset for partition
282 *
283 * Must be called with clk disabled, and returns with clk enabled.
284 */
285 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
286 struct reset_control *rst)
287 {
288 int ret;
289
290 reset_control_assert(rst);
291
292 ret = tegra_powergate_power_on(id);
293 if (ret)
294 goto err_power;
295
296 ret = clk_prepare_enable(clk);
297 if (ret)
298 goto err_clk;
299
300 usleep_range(10, 20);
301
302 ret = tegra_powergate_remove_clamping(id);
303 if (ret)
304 goto err_clamp;
305
306 usleep_range(10, 20);
307 reset_control_deassert(rst);
308
309 return 0;
310
311 err_clamp:
312 clk_disable_unprepare(clk);
313 err_clk:
314 tegra_powergate_power_off(id);
315 err_power:
316 return ret;
317 }
318 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
319
320 #ifdef CONFIG_SMP
321 /**
322 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
323 * @cpuid: CPU partition ID
324 *
325 * Returns the partition ID corresponding to the CPU partition ID or a
326 * negative error code on failure.
327 */
328 static int tegra_get_cpu_powergate_id(int cpuid)
329 {
330 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates)
331 return pmc->soc->cpu_powergates[cpuid];
332
333 return -EINVAL;
334 }
335
336 /**
337 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
338 * @cpuid: CPU partition ID
339 */
340 bool tegra_pmc_cpu_is_powered(int cpuid)
341 {
342 int id;
343
344 id = tegra_get_cpu_powergate_id(cpuid);
345 if (id < 0)
346 return false;
347
348 return tegra_powergate_is_powered(id);
349 }
350
351 /**
352 * tegra_pmc_cpu_power_on() - power on CPU partition
353 * @cpuid: CPU partition ID
354 */
355 int tegra_pmc_cpu_power_on(int cpuid)
356 {
357 int id;
358
359 id = tegra_get_cpu_powergate_id(cpuid);
360 if (id < 0)
361 return id;
362
363 return tegra_powergate_set(id, true);
364 }
365
366 /**
367 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
368 * @cpuid: CPU partition ID
369 */
370 int tegra_pmc_cpu_remove_clamping(int cpuid)
371 {
372 int id;
373
374 id = tegra_get_cpu_powergate_id(cpuid);
375 if (id < 0)
376 return id;
377
378 return tegra_powergate_remove_clamping(id);
379 }
380 #endif /* CONFIG_SMP */
381
382 static int tegra_pmc_restart_notify(struct notifier_block *this,
383 unsigned long action, void *data)
384 {
385 const char *cmd = data;
386 u32 value;
387
388 value = tegra_pmc_readl(PMC_SCRATCH0);
389 value &= ~PMC_SCRATCH0_MODE_MASK;
390
391 if (cmd) {
392 if (strcmp(cmd, "recovery") == 0)
393 value |= PMC_SCRATCH0_MODE_RECOVERY;
394
395 if (strcmp(cmd, "bootloader") == 0)
396 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
397
398 if (strcmp(cmd, "forced-recovery") == 0)
399 value |= PMC_SCRATCH0_MODE_RCM;
400 }
401
402 tegra_pmc_writel(value, PMC_SCRATCH0);
403
404 value = tegra_pmc_readl(0);
405 value |= 0x10;
406 tegra_pmc_writel(value, 0);
407
408 return NOTIFY_DONE;
409 }
410
411 static struct notifier_block tegra_pmc_restart_handler = {
412 .notifier_call = tegra_pmc_restart_notify,
413 .priority = 128,
414 };
415
416 static int powergate_show(struct seq_file *s, void *data)
417 {
418 unsigned int i;
419
420 seq_printf(s, " powergate powered\n");
421 seq_printf(s, "------------------\n");
422
423 for (i = 0; i < pmc->soc->num_powergates; i++) {
424 if (!pmc->soc->powergates[i])
425 continue;
426
427 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
428 tegra_powergate_is_powered(i) ? "yes" : "no");
429 }
430
431 return 0;
432 }
433
434 static int powergate_open(struct inode *inode, struct file *file)
435 {
436 return single_open(file, powergate_show, inode->i_private);
437 }
438
439 static const struct file_operations powergate_fops = {
440 .open = powergate_open,
441 .read = seq_read,
442 .llseek = seq_lseek,
443 .release = single_release,
444 };
445
446 static int tegra_powergate_debugfs_init(void)
447 {
448 struct dentry *d;
449
450 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
451 &powergate_fops);
452 if (!d)
453 return -ENOMEM;
454
455 return 0;
456 }
457
458 static int tegra_io_rail_prepare(int id, unsigned long *request,
459 unsigned long *status, unsigned int *bit)
460 {
461 unsigned long rate, value;
462
463 *bit = id % 32;
464
465 /*
466 * There are two sets of 30 bits to select IO rails, but bits 30 and
467 * 31 are control bits rather than IO rail selection bits.
468 */
469 if (id > 63 || *bit == 30 || *bit == 31)
470 return -EINVAL;
471
472 if (id < 32) {
473 *status = IO_DPD_STATUS;
474 *request = IO_DPD_REQ;
475 } else {
476 *status = IO_DPD2_STATUS;
477 *request = IO_DPD2_REQ;
478 }
479
480 rate = clk_get_rate(pmc->clk);
481
482 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
483
484 /* must be at least 200 ns, in APB (PCLK) clock cycles */
485 value = DIV_ROUND_UP(1000000000, rate);
486 value = DIV_ROUND_UP(200, value);
487 tegra_pmc_writel(value, SEL_DPD_TIM);
488
489 return 0;
490 }
491
492 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
493 unsigned long val, unsigned long timeout)
494 {
495 unsigned long value;
496
497 timeout = jiffies + msecs_to_jiffies(timeout);
498
499 while (time_after(timeout, jiffies)) {
500 value = tegra_pmc_readl(offset);
501 if ((value & mask) == val)
502 return 0;
503
504 usleep_range(250, 1000);
505 }
506
507 return -ETIMEDOUT;
508 }
509
510 static void tegra_io_rail_unprepare(void)
511 {
512 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
513 }
514
515 int tegra_io_rail_power_on(int id)
516 {
517 unsigned long request, status, value;
518 unsigned int bit, mask;
519 int err;
520
521 err = tegra_io_rail_prepare(id, &request, &status, &bit);
522 if (err < 0)
523 return err;
524
525 mask = 1 << bit;
526
527 value = tegra_pmc_readl(request);
528 value |= mask;
529 value &= ~IO_DPD_REQ_CODE_MASK;
530 value |= IO_DPD_REQ_CODE_OFF;
531 tegra_pmc_writel(value, request);
532
533 err = tegra_io_rail_poll(status, mask, 0, 250);
534 if (err < 0) {
535 pr_info("tegra_io_rail_poll() failed: %d\n", err);
536 return err;
537 }
538
539 tegra_io_rail_unprepare();
540
541 return 0;
542 }
543 EXPORT_SYMBOL(tegra_io_rail_power_on);
544
545 int tegra_io_rail_power_off(int id)
546 {
547 unsigned long request, status, value;
548 unsigned int bit, mask;
549 int err;
550
551 err = tegra_io_rail_prepare(id, &request, &status, &bit);
552 if (err < 0) {
553 pr_info("tegra_io_rail_prepare() failed: %d\n", err);
554 return err;
555 }
556
557 mask = 1 << bit;
558
559 value = tegra_pmc_readl(request);
560 value |= mask;
561 value &= ~IO_DPD_REQ_CODE_MASK;
562 value |= IO_DPD_REQ_CODE_ON;
563 tegra_pmc_writel(value, request);
564
565 err = tegra_io_rail_poll(status, mask, mask, 250);
566 if (err < 0)
567 return err;
568
569 tegra_io_rail_unprepare();
570
571 return 0;
572 }
573 EXPORT_SYMBOL(tegra_io_rail_power_off);
574
575 #ifdef CONFIG_PM_SLEEP
576 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
577 {
578 return pmc->suspend_mode;
579 }
580
581 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
582 {
583 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
584 return;
585
586 pmc->suspend_mode = mode;
587 }
588
589 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
590 {
591 unsigned long long rate = 0;
592 u32 value;
593
594 switch (mode) {
595 case TEGRA_SUSPEND_LP1:
596 rate = 32768;
597 break;
598
599 case TEGRA_SUSPEND_LP2:
600 rate = clk_get_rate(pmc->clk);
601 break;
602
603 default:
604 break;
605 }
606
607 if (WARN_ON_ONCE(rate == 0))
608 rate = 100000000;
609
610 if (rate != pmc->rate) {
611 u64 ticks;
612
613 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
614 do_div(ticks, USEC_PER_SEC);
615 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
616
617 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
618 do_div(ticks, USEC_PER_SEC);
619 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
620
621 wmb();
622
623 pmc->rate = rate;
624 }
625
626 value = tegra_pmc_readl(PMC_CNTRL);
627 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
628 value |= PMC_CNTRL_CPU_PWRREQ_OE;
629 tegra_pmc_writel(value, PMC_CNTRL);
630 }
631 #endif
632
633 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
634 {
635 u32 value, values[2];
636
637 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
638 } else {
639 switch (value) {
640 case 0:
641 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
642 break;
643
644 case 1:
645 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
646 break;
647
648 case 2:
649 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
650 break;
651
652 default:
653 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
654 break;
655 }
656 }
657
658 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
659
660 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
661 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
662
663 pmc->cpu_good_time = value;
664
665 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
666 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
667
668 pmc->cpu_off_time = value;
669
670 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
671 values, ARRAY_SIZE(values)))
672 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
673
674 pmc->core_osc_time = values[0];
675 pmc->core_pmu_time = values[1];
676
677 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
678 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
679
680 pmc->core_off_time = value;
681
682 pmc->corereq_high = of_property_read_bool(np,
683 "nvidia,core-power-req-active-high");
684
685 pmc->sysclkreq_high = of_property_read_bool(np,
686 "nvidia,sys-clock-req-active-high");
687
688 pmc->combined_req = of_property_read_bool(np,
689 "nvidia,combined-power-req");
690
691 pmc->cpu_pwr_good_en = of_property_read_bool(np,
692 "nvidia,cpu-pwr-good-en");
693
694 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
695 ARRAY_SIZE(values)))
696 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
697 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
698
699 pmc->lp0_vec_phys = values[0];
700 pmc->lp0_vec_size = values[1];
701
702 return 0;
703 }
704
705 static void tegra_pmc_init(struct tegra_pmc *pmc)
706 {
707 u32 value;
708
709 /* Always enable CPU power request */
710 value = tegra_pmc_readl(PMC_CNTRL);
711 value |= PMC_CNTRL_CPU_PWRREQ_OE;
712 tegra_pmc_writel(value, PMC_CNTRL);
713
714 value = tegra_pmc_readl(PMC_CNTRL);
715
716 if (pmc->sysclkreq_high)
717 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
718 else
719 value |= PMC_CNTRL_SYSCLK_POLARITY;
720
721 /* configure the output polarity while the request is tristated */
722 tegra_pmc_writel(value, PMC_CNTRL);
723
724 /* now enable the request */
725 value = tegra_pmc_readl(PMC_CNTRL);
726 value |= PMC_CNTRL_SYSCLK_OE;
727 tegra_pmc_writel(value, PMC_CNTRL);
728 }
729
730 void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
731 {
732 static const char disabled[] = "emergency thermal reset disabled";
733 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
734 struct device *dev = pmc->dev;
735 struct device_node *np;
736 u32 value, checksum;
737
738 if (!pmc->soc->has_tsense_reset)
739 return;
740
741 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
742 if (!np) {
743 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
744 return;
745 }
746
747 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
748 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
749 goto out;
750 }
751
752 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
753 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
754 goto out;
755 }
756
757 if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
758 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
759 goto out;
760 }
761
762 if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
763 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
764 goto out;
765 }
766
767 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
768 pinmux = 0;
769
770 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
771 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
772 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
773
774 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
775 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
776 tegra_pmc_writel(value, PMC_SCRATCH54);
777
778 value = PMC_SCRATCH55_RESET_TEGRA;
779 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
780 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
781 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
782
783 /*
784 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
785 * contain the checksum and are currently zero, so they are not added.
786 */
787 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
788 + ((value >> 24) & 0xff);
789 checksum &= 0xff;
790 checksum = 0x100 - checksum;
791
792 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
793
794 tegra_pmc_writel(value, PMC_SCRATCH55);
795
796 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
797 value |= PMC_SENSOR_CTRL_ENABLE_RST;
798 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
799
800 dev_info(pmc->dev, "emergency thermal reset enabled\n");
801
802 out:
803 of_node_put(np);
804 }
805
806 static int tegra_pmc_probe(struct platform_device *pdev)
807 {
808 void __iomem *base = pmc->base;
809 struct resource *res;
810 int err;
811
812 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
813 if (err < 0)
814 return err;
815
816 /* take over the memory region from the early initialization */
817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 pmc->base = devm_ioremap_resource(&pdev->dev, res);
819 if (IS_ERR(pmc->base))
820 return PTR_ERR(pmc->base);
821
822 iounmap(base);
823
824 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
825 if (IS_ERR(pmc->clk)) {
826 err = PTR_ERR(pmc->clk);
827 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
828 return err;
829 }
830
831 pmc->dev = &pdev->dev;
832
833 tegra_pmc_init(pmc);
834
835 tegra_pmc_init_tsense_reset(pmc);
836
837 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
838 err = tegra_powergate_debugfs_init();
839 if (err < 0)
840 return err;
841 }
842
843 err = register_restart_handler(&tegra_pmc_restart_handler);
844 if (err) {
845 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
846 err);
847 return err;
848 }
849
850 return 0;
851 }
852
853 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
854 static int tegra_pmc_suspend(struct device *dev)
855 {
856 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
857
858 return 0;
859 }
860
861 static int tegra_pmc_resume(struct device *dev)
862 {
863 tegra_pmc_writel(0x0, PMC_SCRATCH41);
864
865 return 0;
866 }
867
868 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
869
870 #endif
871
872 static const char * const tegra20_powergates[] = {
873 [TEGRA_POWERGATE_CPU] = "cpu",
874 [TEGRA_POWERGATE_3D] = "3d",
875 [TEGRA_POWERGATE_VENC] = "venc",
876 [TEGRA_POWERGATE_VDEC] = "vdec",
877 [TEGRA_POWERGATE_PCIE] = "pcie",
878 [TEGRA_POWERGATE_L2] = "l2",
879 [TEGRA_POWERGATE_MPE] = "mpe",
880 };
881
882 static const struct tegra_pmc_soc tegra20_pmc_soc = {
883 .num_powergates = ARRAY_SIZE(tegra20_powergates),
884 .powergates = tegra20_powergates,
885 .num_cpu_powergates = 0,
886 .cpu_powergates = NULL,
887 .has_tsense_reset = false,
888 .has_gpu_clamps = false,
889 };
890
891 static const char * const tegra30_powergates[] = {
892 [TEGRA_POWERGATE_CPU] = "cpu0",
893 [TEGRA_POWERGATE_3D] = "3d0",
894 [TEGRA_POWERGATE_VENC] = "venc",
895 [TEGRA_POWERGATE_VDEC] = "vdec",
896 [TEGRA_POWERGATE_PCIE] = "pcie",
897 [TEGRA_POWERGATE_L2] = "l2",
898 [TEGRA_POWERGATE_MPE] = "mpe",
899 [TEGRA_POWERGATE_HEG] = "heg",
900 [TEGRA_POWERGATE_SATA] = "sata",
901 [TEGRA_POWERGATE_CPU1] = "cpu1",
902 [TEGRA_POWERGATE_CPU2] = "cpu2",
903 [TEGRA_POWERGATE_CPU3] = "cpu3",
904 [TEGRA_POWERGATE_CELP] = "celp",
905 [TEGRA_POWERGATE_3D1] = "3d1",
906 };
907
908 static const u8 tegra30_cpu_powergates[] = {
909 TEGRA_POWERGATE_CPU,
910 TEGRA_POWERGATE_CPU1,
911 TEGRA_POWERGATE_CPU2,
912 TEGRA_POWERGATE_CPU3,
913 };
914
915 static const struct tegra_pmc_soc tegra30_pmc_soc = {
916 .num_powergates = ARRAY_SIZE(tegra30_powergates),
917 .powergates = tegra30_powergates,
918 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
919 .cpu_powergates = tegra30_cpu_powergates,
920 .has_tsense_reset = true,
921 .has_gpu_clamps = false,
922 };
923
924 static const char * const tegra114_powergates[] = {
925 [TEGRA_POWERGATE_CPU] = "crail",
926 [TEGRA_POWERGATE_3D] = "3d",
927 [TEGRA_POWERGATE_VENC] = "venc",
928 [TEGRA_POWERGATE_VDEC] = "vdec",
929 [TEGRA_POWERGATE_MPE] = "mpe",
930 [TEGRA_POWERGATE_HEG] = "heg",
931 [TEGRA_POWERGATE_CPU1] = "cpu1",
932 [TEGRA_POWERGATE_CPU2] = "cpu2",
933 [TEGRA_POWERGATE_CPU3] = "cpu3",
934 [TEGRA_POWERGATE_CELP] = "celp",
935 [TEGRA_POWERGATE_CPU0] = "cpu0",
936 [TEGRA_POWERGATE_C0NC] = "c0nc",
937 [TEGRA_POWERGATE_C1NC] = "c1nc",
938 [TEGRA_POWERGATE_DIS] = "dis",
939 [TEGRA_POWERGATE_DISB] = "disb",
940 [TEGRA_POWERGATE_XUSBA] = "xusba",
941 [TEGRA_POWERGATE_XUSBB] = "xusbb",
942 [TEGRA_POWERGATE_XUSBC] = "xusbc",
943 };
944
945 static const u8 tegra114_cpu_powergates[] = {
946 TEGRA_POWERGATE_CPU0,
947 TEGRA_POWERGATE_CPU1,
948 TEGRA_POWERGATE_CPU2,
949 TEGRA_POWERGATE_CPU3,
950 };
951
952 static const struct tegra_pmc_soc tegra114_pmc_soc = {
953 .num_powergates = ARRAY_SIZE(tegra114_powergates),
954 .powergates = tegra114_powergates,
955 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
956 .cpu_powergates = tegra114_cpu_powergates,
957 .has_tsense_reset = true,
958 .has_gpu_clamps = false,
959 };
960
961 static const char * const tegra124_powergates[] = {
962 [TEGRA_POWERGATE_CPU] = "crail",
963 [TEGRA_POWERGATE_3D] = "3d",
964 [TEGRA_POWERGATE_VENC] = "venc",
965 [TEGRA_POWERGATE_PCIE] = "pcie",
966 [TEGRA_POWERGATE_VDEC] = "vdec",
967 [TEGRA_POWERGATE_L2] = "l2",
968 [TEGRA_POWERGATE_MPE] = "mpe",
969 [TEGRA_POWERGATE_HEG] = "heg",
970 [TEGRA_POWERGATE_SATA] = "sata",
971 [TEGRA_POWERGATE_CPU1] = "cpu1",
972 [TEGRA_POWERGATE_CPU2] = "cpu2",
973 [TEGRA_POWERGATE_CPU3] = "cpu3",
974 [TEGRA_POWERGATE_CELP] = "celp",
975 [TEGRA_POWERGATE_CPU0] = "cpu0",
976 [TEGRA_POWERGATE_C0NC] = "c0nc",
977 [TEGRA_POWERGATE_C1NC] = "c1nc",
978 [TEGRA_POWERGATE_SOR] = "sor",
979 [TEGRA_POWERGATE_DIS] = "dis",
980 [TEGRA_POWERGATE_DISB] = "disb",
981 [TEGRA_POWERGATE_XUSBA] = "xusba",
982 [TEGRA_POWERGATE_XUSBB] = "xusbb",
983 [TEGRA_POWERGATE_XUSBC] = "xusbc",
984 [TEGRA_POWERGATE_VIC] = "vic",
985 [TEGRA_POWERGATE_IRAM] = "iram",
986 };
987
988 static const u8 tegra124_cpu_powergates[] = {
989 TEGRA_POWERGATE_CPU0,
990 TEGRA_POWERGATE_CPU1,
991 TEGRA_POWERGATE_CPU2,
992 TEGRA_POWERGATE_CPU3,
993 };
994
995 static const struct tegra_pmc_soc tegra124_pmc_soc = {
996 .num_powergates = ARRAY_SIZE(tegra124_powergates),
997 .powergates = tegra124_powergates,
998 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
999 .cpu_powergates = tegra124_cpu_powergates,
1000 .has_tsense_reset = true,
1001 .has_gpu_clamps = true,
1002 };
1003
1004 static const char * const tegra210_powergates[] = {
1005 [TEGRA_POWERGATE_CPU] = "crail",
1006 [TEGRA_POWERGATE_3D] = "3d",
1007 [TEGRA_POWERGATE_VENC] = "venc",
1008 [TEGRA_POWERGATE_PCIE] = "pcie",
1009 [TEGRA_POWERGATE_L2] = "l2",
1010 [TEGRA_POWERGATE_MPE] = "mpe",
1011 [TEGRA_POWERGATE_HEG] = "heg",
1012 [TEGRA_POWERGATE_SATA] = "sata",
1013 [TEGRA_POWERGATE_CPU1] = "cpu1",
1014 [TEGRA_POWERGATE_CPU2] = "cpu2",
1015 [TEGRA_POWERGATE_CPU3] = "cpu3",
1016 [TEGRA_POWERGATE_CELP] = "celp",
1017 [TEGRA_POWERGATE_CPU0] = "cpu0",
1018 [TEGRA_POWERGATE_C0NC] = "c0nc",
1019 [TEGRA_POWERGATE_C1NC] = "c1nc",
1020 [TEGRA_POWERGATE_SOR] = "sor",
1021 [TEGRA_POWERGATE_DIS] = "dis",
1022 [TEGRA_POWERGATE_DISB] = "disb",
1023 [TEGRA_POWERGATE_XUSBA] = "xusba",
1024 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1025 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1026 [TEGRA_POWERGATE_VIC] = "vic",
1027 [TEGRA_POWERGATE_IRAM] = "iram",
1028 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1029 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1030 [TEGRA_POWERGATE_AUD] = "aud",
1031 [TEGRA_POWERGATE_DFD] = "dfd",
1032 [TEGRA_POWERGATE_VE2] = "ve2",
1033 };
1034
1035 static const u8 tegra210_cpu_powergates[] = {
1036 TEGRA_POWERGATE_CPU0,
1037 TEGRA_POWERGATE_CPU1,
1038 TEGRA_POWERGATE_CPU2,
1039 TEGRA_POWERGATE_CPU3,
1040 };
1041
1042 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1043 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1044 .powergates = tegra210_powergates,
1045 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1046 .cpu_powergates = tegra210_cpu_powergates,
1047 .has_tsense_reset = true,
1048 .has_gpu_clamps = true,
1049 };
1050
1051 static const struct of_device_id tegra_pmc_match[] = {
1052 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1053 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1054 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1055 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1056 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1057 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1058 { }
1059 };
1060
1061 static struct platform_driver tegra_pmc_driver = {
1062 .driver = {
1063 .name = "tegra-pmc",
1064 .suppress_bind_attrs = true,
1065 .of_match_table = tegra_pmc_match,
1066 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1067 .pm = &tegra_pmc_pm_ops,
1068 #endif
1069 },
1070 .probe = tegra_pmc_probe,
1071 };
1072 builtin_platform_driver(tegra_pmc_driver);
1073
1074 /*
1075 * Early initialization to allow access to registers in the very early boot
1076 * process.
1077 */
1078 static int __init tegra_pmc_early_init(void)
1079 {
1080 const struct of_device_id *match;
1081 struct device_node *np;
1082 struct resource regs;
1083 bool invert;
1084 u32 value;
1085
1086 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1087 if (!np) {
1088 /*
1089 * Fall back to legacy initialization for 32-bit ARM only. All
1090 * 64-bit ARM device tree files for Tegra are required to have
1091 * a PMC node.
1092 *
1093 * This is for backwards-compatibility with old device trees
1094 * that didn't contain a PMC node. Note that in this case the
1095 * SoC data can't be matched and therefore powergating is
1096 * disabled.
1097 */
1098 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1099 pr_warn("DT node not found, powergating disabled\n");
1100
1101 regs.start = 0x7000e400;
1102 regs.end = 0x7000e7ff;
1103 regs.flags = IORESOURCE_MEM;
1104
1105 pr_warn("Using memory region %pR\n", &regs);
1106 } else {
1107 /*
1108 * At this point we're not running on Tegra, so play
1109 * nice with multi-platform kernels.
1110 */
1111 return 0;
1112 }
1113 } else {
1114 /*
1115 * Extract information from the device tree if we've found a
1116 * matching node.
1117 */
1118 if (of_address_to_resource(np, 0, &regs) < 0) {
1119 pr_err("failed to get PMC registers\n");
1120 return -ENXIO;
1121 }
1122
1123 pmc->soc = match->data;
1124 }
1125
1126 pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
1127 if (!pmc->base) {
1128 pr_err("failed to map PMC registers\n");
1129 return -ENXIO;
1130 }
1131
1132 mutex_init(&pmc->powergates_lock);
1133
1134 /*
1135 * Invert the interrupt polarity if a PMC device tree node exists and
1136 * contains the nvidia,invert-interrupt property.
1137 */
1138 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1139
1140 value = tegra_pmc_readl(PMC_CNTRL);
1141
1142 if (invert)
1143 value |= PMC_CNTRL_INTR_POLARITY;
1144 else
1145 value &= ~PMC_CNTRL_INTR_POLARITY;
1146
1147 tegra_pmc_writel(value, PMC_CNTRL);
1148
1149 return 0;
1150 }
1151 early_initcall(tegra_pmc_early_init);
Linux with added FPC-III support