2 * SPI bus via the Blackfin SPORT peripheral
4 * Enter bugs at http://blackfin.uclinux.org/
6 * Copyright 2009-2011 Analog Devices Inc.
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/gpio.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/workqueue.h>
24 #include <asm/portmux.h>
25 #include <asm/bfin5xx_spi.h>
26 #include <asm/blackfin.h>
27 #include <asm/bfin_sport.h>
28 #include <asm/cacheflush.h>
30 #define DRV_NAME "bfin-sport-spi"
31 #define DRV_DESC "SPI bus via the Blackfin SPORT"
33 MODULE_AUTHOR("Cliff Cai");
34 MODULE_DESCRIPTION(DRV_DESC
);
35 MODULE_LICENSE("GPL");
36 MODULE_ALIAS("platform:bfin-sport-spi");
38 enum bfin_sport_spi_state
{
45 struct bfin_sport_spi_master_data
;
47 struct bfin_sport_transfer_ops
{
48 void (*write
) (struct bfin_sport_spi_master_data
*);
49 void (*read
) (struct bfin_sport_spi_master_data
*);
50 void (*duplex
) (struct bfin_sport_spi_master_data
*);
53 struct bfin_sport_spi_master_data
{
54 /* Driver model hookup */
57 /* SPI framework hookup */
58 struct spi_master
*master
;
60 /* Regs base of SPI controller */
61 struct sport_register __iomem
*regs
;
64 /* Pin request list */
67 /* Driver message queue */
68 struct workqueue_struct
*workqueue
;
69 struct work_struct pump_messages
;
71 struct list_head queue
;
75 /* Message Transfer pump */
76 struct tasklet_struct pump_transfers
;
78 /* Current message transfer state info */
79 enum bfin_sport_spi_state state
;
80 struct spi_message
*cur_msg
;
81 struct spi_transfer
*cur_transfer
;
82 struct bfin_sport_spi_slave_data
*cur_chip
;
97 struct bfin_sport_transfer_ops
*ops
;
100 struct bfin_sport_spi_slave_data
{
103 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
106 struct bfin_sport_transfer_ops
*ops
;
110 bfin_sport_spi_enable(struct bfin_sport_spi_master_data
*drv_data
)
112 bfin_write_or(&drv_data
->regs
->tcr1
, TSPEN
);
113 bfin_write_or(&drv_data
->regs
->rcr1
, TSPEN
);
118 bfin_sport_spi_disable(struct bfin_sport_spi_master_data
*drv_data
)
120 bfin_write_and(&drv_data
->regs
->tcr1
, ~TSPEN
);
121 bfin_write_and(&drv_data
->regs
->rcr1
, ~TSPEN
);
125 /* Caculate the SPI_BAUD register value based on input HZ */
127 bfin_sport_hz_to_spi_baud(u32 speed_hz
)
129 u_long clk
, sclk
= get_sclk();
130 int div
= (sclk
/ (2 * speed_hz
)) - 1;
135 clk
= sclk
/ (2 * (div
+ 1));
143 /* Chip select operation functions for cs_change flag */
145 bfin_sport_spi_cs_active(struct bfin_sport_spi_slave_data
*chip
)
147 gpio_direction_output(chip
->cs_gpio
, 0);
151 bfin_sport_spi_cs_deactive(struct bfin_sport_spi_slave_data
*chip
)
153 gpio_direction_output(chip
->cs_gpio
, 1);
154 /* Move delay here for consistency */
155 if (chip
->cs_chg_udelay
)
156 udelay(chip
->cs_chg_udelay
);
160 bfin_sport_spi_stat_poll_complete(struct bfin_sport_spi_master_data
*drv_data
)
162 unsigned long timeout
= jiffies
+ HZ
;
163 while (!(bfin_read(&drv_data
->regs
->stat
) & RXNE
)) {
164 if (!time_before(jiffies
, timeout
))
170 bfin_sport_spi_u8_writer(struct bfin_sport_spi_master_data
*drv_data
)
174 while (drv_data
->tx
< drv_data
->tx_end
) {
175 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx8
++);
176 bfin_sport_spi_stat_poll_complete(drv_data
);
177 dummy
= bfin_read(&drv_data
->regs
->rx16
);
182 bfin_sport_spi_u8_reader(struct bfin_sport_spi_master_data
*drv_data
)
184 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
186 while (drv_data
->rx
< drv_data
->rx_end
) {
187 bfin_write(&drv_data
->regs
->tx16
, tx_val
);
188 bfin_sport_spi_stat_poll_complete(drv_data
);
189 *drv_data
->rx8
++ = bfin_read(&drv_data
->regs
->rx16
);
194 bfin_sport_spi_u8_duplex(struct bfin_sport_spi_master_data
*drv_data
)
196 while (drv_data
->rx
< drv_data
->rx_end
) {
197 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx8
++);
198 bfin_sport_spi_stat_poll_complete(drv_data
);
199 *drv_data
->rx8
++ = bfin_read(&drv_data
->regs
->rx16
);
203 static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u8
= {
204 .write
= bfin_sport_spi_u8_writer
,
205 .read
= bfin_sport_spi_u8_reader
,
206 .duplex
= bfin_sport_spi_u8_duplex
,
210 bfin_sport_spi_u16_writer(struct bfin_sport_spi_master_data
*drv_data
)
214 while (drv_data
->tx
< drv_data
->tx_end
) {
215 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx16
++);
216 bfin_sport_spi_stat_poll_complete(drv_data
);
217 dummy
= bfin_read(&drv_data
->regs
->rx16
);
222 bfin_sport_spi_u16_reader(struct bfin_sport_spi_master_data
*drv_data
)
224 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
226 while (drv_data
->rx
< drv_data
->rx_end
) {
227 bfin_write(&drv_data
->regs
->tx16
, tx_val
);
228 bfin_sport_spi_stat_poll_complete(drv_data
);
229 *drv_data
->rx16
++ = bfin_read(&drv_data
->regs
->rx16
);
234 bfin_sport_spi_u16_duplex(struct bfin_sport_spi_master_data
*drv_data
)
236 while (drv_data
->rx
< drv_data
->rx_end
) {
237 bfin_write(&drv_data
->regs
->tx16
, *drv_data
->tx16
++);
238 bfin_sport_spi_stat_poll_complete(drv_data
);
239 *drv_data
->rx16
++ = bfin_read(&drv_data
->regs
->rx16
);
243 static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u16
= {
244 .write
= bfin_sport_spi_u16_writer
,
245 .read
= bfin_sport_spi_u16_reader
,
246 .duplex
= bfin_sport_spi_u16_duplex
,
249 /* stop controller and re-config current chip */
251 bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data
*drv_data
)
253 struct bfin_sport_spi_slave_data
*chip
= drv_data
->cur_chip
;
255 bfin_sport_spi_disable(drv_data
);
256 dev_dbg(drv_data
->dev
, "restoring spi ctl state\n");
258 bfin_write(&drv_data
->regs
->tcr1
, chip
->ctl_reg
);
259 bfin_write(&drv_data
->regs
->tclkdiv
, chip
->baud
);
262 bfin_write(&drv_data
->regs
->rcr1
, chip
->ctl_reg
& ~(ITCLK
| ITFS
));
265 bfin_sport_spi_cs_active(chip
);
268 /* test if there is more transfer to be done */
269 static enum bfin_sport_spi_state
270 bfin_sport_spi_next_transfer(struct bfin_sport_spi_master_data
*drv_data
)
272 struct spi_message
*msg
= drv_data
->cur_msg
;
273 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
275 /* Move to next transfer */
276 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
277 drv_data
->cur_transfer
=
278 list_entry(trans
->transfer_list
.next
,
279 struct spi_transfer
, transfer_list
);
280 return RUNNING_STATE
;
287 * caller already set message->status;
288 * dma and pio irqs are blocked give finished message back
291 bfin_sport_spi_giveback(struct bfin_sport_spi_master_data
*drv_data
)
293 struct bfin_sport_spi_slave_data
*chip
= drv_data
->cur_chip
;
295 struct spi_message
*msg
;
297 spin_lock_irqsave(&drv_data
->lock
, flags
);
298 msg
= drv_data
->cur_msg
;
299 drv_data
->state
= START_STATE
;
300 drv_data
->cur_msg
= NULL
;
301 drv_data
->cur_transfer
= NULL
;
302 drv_data
->cur_chip
= NULL
;
303 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
304 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
306 if (!drv_data
->cs_change
)
307 bfin_sport_spi_cs_deactive(chip
);
310 msg
->complete(msg
->context
);
314 sport_err_handler(int irq
, void *dev_id
)
316 struct bfin_sport_spi_master_data
*drv_data
= dev_id
;
319 dev_dbg(drv_data
->dev
, "%s enter\n", __func__
);
320 status
= bfin_read(&drv_data
->regs
->stat
) & (TOVF
| TUVF
| ROVF
| RUVF
);
323 bfin_write(&drv_data
->regs
->stat
, status
);
326 bfin_sport_spi_disable(drv_data
);
327 dev_err(drv_data
->dev
, "status error:%s%s%s%s\n",
328 status
& TOVF
? " TOVF" : "",
329 status
& TUVF
? " TUVF" : "",
330 status
& ROVF
? " ROVF" : "",
331 status
& RUVF
? " RUVF" : "");
338 bfin_sport_spi_pump_transfers(unsigned long data
)
340 struct bfin_sport_spi_master_data
*drv_data
= (void *)data
;
341 struct spi_message
*message
= NULL
;
342 struct spi_transfer
*transfer
= NULL
;
343 struct spi_transfer
*previous
= NULL
;
344 struct bfin_sport_spi_slave_data
*chip
= NULL
;
345 unsigned int bits_per_word
;
346 u32 tranf_success
= 1;
350 /* Get current state information */
351 message
= drv_data
->cur_msg
;
352 transfer
= drv_data
->cur_transfer
;
353 chip
= drv_data
->cur_chip
;
355 transfer_speed
= bfin_sport_hz_to_spi_baud(transfer
->speed_hz
);
356 bfin_write(&drv_data
->regs
->tclkdiv
, transfer_speed
);
360 * if msg is error or done, report it back using complete() callback
363 /* Handle for abort */
364 if (drv_data
->state
== ERROR_STATE
) {
365 dev_dbg(drv_data
->dev
, "transfer: we've hit an error\n");
366 message
->status
= -EIO
;
367 bfin_sport_spi_giveback(drv_data
);
371 /* Handle end of message */
372 if (drv_data
->state
== DONE_STATE
) {
373 dev_dbg(drv_data
->dev
, "transfer: all done!\n");
375 bfin_sport_spi_giveback(drv_data
);
379 /* Delay if requested at end of transfer */
380 if (drv_data
->state
== RUNNING_STATE
) {
381 dev_dbg(drv_data
->dev
, "transfer: still running ...\n");
382 previous
= list_entry(transfer
->transfer_list
.prev
,
383 struct spi_transfer
, transfer_list
);
384 if (previous
->delay_usecs
)
385 udelay(previous
->delay_usecs
);
388 if (transfer
->len
== 0) {
389 /* Move to next transfer of this msg */
390 drv_data
->state
= bfin_sport_spi_next_transfer(drv_data
);
391 /* Schedule next transfer tasklet */
392 tasklet_schedule(&drv_data
->pump_transfers
);
395 if (transfer
->tx_buf
!= NULL
) {
396 drv_data
->tx
= (void *)transfer
->tx_buf
;
397 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
398 dev_dbg(drv_data
->dev
, "tx_buf is %p, tx_end is %p\n",
399 transfer
->tx_buf
, drv_data
->tx_end
);
403 if (transfer
->rx_buf
!= NULL
) {
404 full_duplex
= transfer
->tx_buf
!= NULL
;
405 drv_data
->rx
= transfer
->rx_buf
;
406 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
407 dev_dbg(drv_data
->dev
, "rx_buf is %p, rx_end is %p\n",
408 transfer
->rx_buf
, drv_data
->rx_end
);
412 drv_data
->cs_change
= transfer
->cs_change
;
414 /* Bits per word setup */
415 bits_per_word
= transfer
->bits_per_word
;
416 if (bits_per_word
== 16)
417 drv_data
->ops
= &bfin_sport_transfer_ops_u16
;
419 drv_data
->ops
= &bfin_sport_transfer_ops_u8
;
420 bfin_write(&drv_data
->regs
->tcr2
, bits_per_word
- 1);
421 bfin_write(&drv_data
->regs
->tfsdiv
, bits_per_word
- 1);
422 bfin_write(&drv_data
->regs
->rcr2
, bits_per_word
- 1);
424 drv_data
->state
= RUNNING_STATE
;
426 if (drv_data
->cs_change
)
427 bfin_sport_spi_cs_active(chip
);
429 dev_dbg(drv_data
->dev
,
430 "now pumping a transfer: width is %d, len is %d\n",
431 bits_per_word
, transfer
->len
);
433 /* PIO mode write then read */
434 dev_dbg(drv_data
->dev
, "doing IO transfer\n");
436 bfin_sport_spi_enable(drv_data
);
438 /* full duplex mode */
439 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
440 (drv_data
->rx_end
- drv_data
->rx
));
441 drv_data
->ops
->duplex(drv_data
);
443 if (drv_data
->tx
!= drv_data
->tx_end
)
445 } else if (drv_data
->tx
!= NULL
) {
446 /* write only half duplex */
448 drv_data
->ops
->write(drv_data
);
450 if (drv_data
->tx
!= drv_data
->tx_end
)
452 } else if (drv_data
->rx
!= NULL
) {
453 /* read only half duplex */
455 drv_data
->ops
->read(drv_data
);
456 if (drv_data
->rx
!= drv_data
->rx_end
)
459 bfin_sport_spi_disable(drv_data
);
461 if (!tranf_success
) {
462 dev_dbg(drv_data
->dev
, "IO write error!\n");
463 drv_data
->state
= ERROR_STATE
;
465 /* Update total byte transferred */
466 message
->actual_length
+= transfer
->len
;
467 /* Move to next transfer of this msg */
468 drv_data
->state
= bfin_sport_spi_next_transfer(drv_data
);
469 if (drv_data
->cs_change
)
470 bfin_sport_spi_cs_deactive(chip
);
473 /* Schedule next transfer tasklet */
474 tasklet_schedule(&drv_data
->pump_transfers
);
477 /* pop a msg from queue and kick off real transfer */
479 bfin_sport_spi_pump_messages(struct work_struct
*work
)
481 struct bfin_sport_spi_master_data
*drv_data
;
483 struct spi_message
*next_msg
;
485 drv_data
= container_of(work
, struct bfin_sport_spi_master_data
, pump_messages
);
487 /* Lock queue and check for queue work */
488 spin_lock_irqsave(&drv_data
->lock
, flags
);
489 if (list_empty(&drv_data
->queue
) || !drv_data
->run
) {
490 /* pumper kicked off but no work to do */
492 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
496 /* Make sure we are not already running a message */
497 if (drv_data
->cur_msg
) {
498 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
502 /* Extract head of queue */
503 next_msg
= list_entry(drv_data
->queue
.next
,
504 struct spi_message
, queue
);
506 drv_data
->cur_msg
= next_msg
;
508 /* Setup the SSP using the per chip configuration */
509 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
511 list_del_init(&drv_data
->cur_msg
->queue
);
513 /* Initialize message state */
514 drv_data
->cur_msg
->state
= START_STATE
;
515 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
516 struct spi_transfer
, transfer_list
);
517 bfin_sport_spi_restore_state(drv_data
);
518 dev_dbg(drv_data
->dev
, "got a message to pump, "
519 "state is set to: baud %d, cs_gpio %i, ctl 0x%x\n",
520 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->cs_gpio
,
521 drv_data
->cur_chip
->ctl_reg
);
523 dev_dbg(drv_data
->dev
,
524 "the first transfer len is %d\n",
525 drv_data
->cur_transfer
->len
);
527 /* Mark as busy and launch transfers */
528 tasklet_schedule(&drv_data
->pump_transfers
);
531 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
535 * got a msg to transfer, queue it in drv_data->queue.
536 * And kick off message pumper
539 bfin_sport_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
541 struct bfin_sport_spi_master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
544 spin_lock_irqsave(&drv_data
->lock
, flags
);
546 if (!drv_data
->run
) {
547 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
551 msg
->actual_length
= 0;
552 msg
->status
= -EINPROGRESS
;
553 msg
->state
= START_STATE
;
555 dev_dbg(&spi
->dev
, "adding an msg in transfer()\n");
556 list_add_tail(&msg
->queue
, &drv_data
->queue
);
558 if (drv_data
->run
&& !drv_data
->busy
)
559 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
561 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
566 /* Called every time common spi devices change state */
568 bfin_sport_spi_setup(struct spi_device
*spi
)
570 struct bfin_sport_spi_slave_data
*chip
, *first
= NULL
;
573 /* Only alloc (or use chip_info) on first setup */
574 chip
= spi_get_ctldata(spi
);
576 struct bfin5xx_spi_chip
*chip_info
;
578 chip
= first
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
582 /* platform chip_info isn't required */
583 chip_info
= spi
->controller_data
;
586 * DITFS and TDTYPE are only thing we don't set, but
587 * they probably shouldn't be changed by people.
589 if (chip_info
->ctl_reg
|| chip_info
->enable_dma
) {
591 dev_err(&spi
->dev
, "don't set ctl_reg/enable_dma fields\n");
594 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
595 chip
->idle_tx_val
= chip_info
->idle_tx_val
;
599 /* translate common spi framework into our register
600 * following configure contents are same for tx and rx.
603 if (spi
->mode
& SPI_CPHA
)
604 chip
->ctl_reg
&= ~TCKFE
;
606 chip
->ctl_reg
|= TCKFE
;
608 if (spi
->mode
& SPI_LSB_FIRST
)
609 chip
->ctl_reg
|= TLSBIT
;
611 chip
->ctl_reg
&= ~TLSBIT
;
613 /* Sport in master mode */
614 chip
->ctl_reg
|= ITCLK
| ITFS
| TFSR
| LATFS
| LTFS
;
616 chip
->baud
= bfin_sport_hz_to_spi_baud(spi
->max_speed_hz
);
618 chip
->cs_gpio
= spi
->chip_select
;
619 ret
= gpio_request(chip
->cs_gpio
, spi
->modalias
);
623 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d\n",
624 spi
->modalias
, spi
->bits_per_word
);
625 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, GPIO is %i\n",
626 chip
->ctl_reg
, spi
->chip_select
);
628 spi_set_ctldata(spi
, chip
);
630 bfin_sport_spi_cs_deactive(chip
);
640 * callback for spi framework.
641 * clean driver specific data
644 bfin_sport_spi_cleanup(struct spi_device
*spi
)
646 struct bfin_sport_spi_slave_data
*chip
= spi_get_ctldata(spi
);
651 gpio_free(chip
->cs_gpio
);
657 bfin_sport_spi_init_queue(struct bfin_sport_spi_master_data
*drv_data
)
659 INIT_LIST_HEAD(&drv_data
->queue
);
660 spin_lock_init(&drv_data
->lock
);
662 drv_data
->run
= false;
665 /* init transfer tasklet */
666 tasklet_init(&drv_data
->pump_transfers
,
667 bfin_sport_spi_pump_transfers
, (unsigned long)drv_data
);
669 /* init messages workqueue */
670 INIT_WORK(&drv_data
->pump_messages
, bfin_sport_spi_pump_messages
);
671 drv_data
->workqueue
=
672 create_singlethread_workqueue(dev_name(drv_data
->master
->dev
.parent
));
673 if (drv_data
->workqueue
== NULL
)
680 bfin_sport_spi_start_queue(struct bfin_sport_spi_master_data
*drv_data
)
684 spin_lock_irqsave(&drv_data
->lock
, flags
);
686 if (drv_data
->run
|| drv_data
->busy
) {
687 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
691 drv_data
->run
= true;
692 drv_data
->cur_msg
= NULL
;
693 drv_data
->cur_transfer
= NULL
;
694 drv_data
->cur_chip
= NULL
;
695 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
697 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
703 bfin_sport_spi_stop_queue(struct bfin_sport_spi_master_data
*drv_data
)
706 unsigned limit
= 500;
709 spin_lock_irqsave(&drv_data
->lock
, flags
);
712 * This is a bit lame, but is optimized for the common execution path.
713 * A wait_queue on the drv_data->busy could be used, but then the common
714 * execution path (pump_messages) would be required to call wake_up or
715 * friends on every SPI message. Do this instead
717 drv_data
->run
= false;
718 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
719 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
721 spin_lock_irqsave(&drv_data
->lock
, flags
);
724 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
727 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
733 bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data
*drv_data
)
737 status
= bfin_sport_spi_stop_queue(drv_data
);
741 destroy_workqueue(drv_data
->workqueue
);
746 static int bfin_sport_spi_probe(struct platform_device
*pdev
)
748 struct device
*dev
= &pdev
->dev
;
749 struct bfin5xx_spi_master
*platform_info
;
750 struct spi_master
*master
;
751 struct resource
*res
, *ires
;
752 struct bfin_sport_spi_master_data
*drv_data
;
755 platform_info
= dev_get_platdata(dev
);
757 /* Allocate master with space for drv_data */
758 master
= spi_alloc_master(dev
, sizeof(*master
) + 16);
760 dev_err(dev
, "cannot alloc spi_master\n");
764 drv_data
= spi_master_get_devdata(master
);
765 drv_data
->master
= master
;
767 drv_data
->pin_req
= platform_info
->pin_req
;
769 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
770 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
771 master
->bus_num
= pdev
->id
;
772 master
->num_chipselect
= platform_info
->num_chipselect
;
773 master
->cleanup
= bfin_sport_spi_cleanup
;
774 master
->setup
= bfin_sport_spi_setup
;
775 master
->transfer
= bfin_sport_spi_transfer
;
777 /* Find and map our resources */
778 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
780 dev_err(dev
, "cannot get IORESOURCE_MEM\n");
782 goto out_error_get_res
;
785 drv_data
->regs
= ioremap(res
->start
, resource_size(res
));
786 if (drv_data
->regs
== NULL
) {
787 dev_err(dev
, "cannot map registers\n");
789 goto out_error_ioremap
;
792 ires
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
794 dev_err(dev
, "cannot get IORESOURCE_IRQ\n");
796 goto out_error_get_ires
;
798 drv_data
->err_irq
= ires
->start
;
800 /* Initial and start queue */
801 status
= bfin_sport_spi_init_queue(drv_data
);
803 dev_err(dev
, "problem initializing queue\n");
804 goto out_error_queue_alloc
;
807 status
= bfin_sport_spi_start_queue(drv_data
);
809 dev_err(dev
, "problem starting queue\n");
810 goto out_error_queue_alloc
;
813 status
= request_irq(drv_data
->err_irq
, sport_err_handler
,
814 0, "sport_spi_err", drv_data
);
816 dev_err(dev
, "unable to request sport err irq\n");
820 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
822 dev_err(dev
, "requesting peripherals failed\n");
823 goto out_error_peripheral
;
826 /* Register with the SPI framework */
827 platform_set_drvdata(pdev
, drv_data
);
828 status
= spi_register_master(master
);
830 dev_err(dev
, "problem registering spi master\n");
831 goto out_error_master
;
834 dev_info(dev
, "%s, regs_base@%p\n", DRV_DESC
, drv_data
->regs
);
838 peripheral_free_list(drv_data
->pin_req
);
839 out_error_peripheral
:
840 free_irq(drv_data
->err_irq
, drv_data
);
842 out_error_queue_alloc
:
843 bfin_sport_spi_destroy_queue(drv_data
);
845 iounmap(drv_data
->regs
);
848 spi_master_put(master
);
853 /* stop hardware and remove the driver */
854 static int bfin_sport_spi_remove(struct platform_device
*pdev
)
856 struct bfin_sport_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
862 /* Remove the queue */
863 status
= bfin_sport_spi_destroy_queue(drv_data
);
867 /* Disable the SSP at the peripheral and SOC level */
868 bfin_sport_spi_disable(drv_data
);
870 /* Disconnect from the SPI framework */
871 spi_unregister_master(drv_data
->master
);
873 peripheral_free_list(drv_data
->pin_req
);
878 #ifdef CONFIG_PM_SLEEP
879 static int bfin_sport_spi_suspend(struct device
*dev
)
881 struct bfin_sport_spi_master_data
*drv_data
= dev_get_drvdata(dev
);
884 status
= bfin_sport_spi_stop_queue(drv_data
);
889 bfin_sport_spi_disable(drv_data
);
894 static int bfin_sport_spi_resume(struct device
*dev
)
896 struct bfin_sport_spi_master_data
*drv_data
= dev_get_drvdata(dev
);
899 /* Enable the SPI interface */
900 bfin_sport_spi_enable(drv_data
);
902 /* Start the queue running */
903 status
= bfin_sport_spi_start_queue(drv_data
);
905 dev_err(drv_data
->dev
, "problem resuming queue\n");
910 static SIMPLE_DEV_PM_OPS(bfin_sport_spi_pm_ops
, bfin_sport_spi_suspend
,
911 bfin_sport_spi_resume
);
913 #define BFIN_SPORT_SPI_PM_OPS (&bfin_sport_spi_pm_ops)
915 #define BFIN_SPORT_SPI_PM_OPS NULL
918 static struct platform_driver bfin_sport_spi_driver
= {
921 .pm
= BFIN_SPORT_SPI_PM_OPS
,
923 .probe
= bfin_sport_spi_probe
,
924 .remove
= bfin_sport_spi_remove
,
926 module_platform_driver(bfin_sport_spi_driver
);