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irqchip/s3c24xx: Mark init_eint as __maybe_unused
[linux/fpc-iii.git] / drivers / usb / phy / phy-msm-usb.c
blob0d19a6d61a71f7ccb7a55e1b90a7d5d5f27db535
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
28 #include <linux/io.h>
29 #include <linux/ioport.h>
30 #include <linux/uaccess.h>
31 #include <linux/debugfs.h>
32 #include <linux/seq_file.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/reboot.h>
37 #include <linux/reset.h>
38
39 #include <linux/usb.h>
40 #include <linux/usb/otg.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/ulpi.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/hcd.h>
45 #include <linux/usb/msm_hsusb.h>
46 #include <linux/usb/msm_hsusb_hw.h>
47 #include <linux/regulator/consumer.h>
48
49 #define MSM_USB_BASE (motg->regs)
50 #define DRIVER_NAME "msm_otg"
51
52 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
53 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
54
55 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
56 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
57 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
59
60 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
61 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
62 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
63 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
64
65 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
66 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
67 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
68
69 enum vdd_levels {
70 VDD_LEVEL_NONE = 0,
71 VDD_LEVEL_MIN,
72 VDD_LEVEL_MAX,
73 };
74
75 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
76 {
77 int ret = 0;
78
79 if (init) {
80 ret = regulator_set_voltage(motg->vddcx,
81 motg->vdd_levels[VDD_LEVEL_MIN],
82 motg->vdd_levels[VDD_LEVEL_MAX]);
83 if (ret) {
84 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
85 return ret;
86 }
87
88 ret = regulator_enable(motg->vddcx);
89 if (ret)
90 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
91 } else {
92 ret = regulator_set_voltage(motg->vddcx, 0,
93 motg->vdd_levels[VDD_LEVEL_MAX]);
94 if (ret)
95 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
96 ret = regulator_disable(motg->vddcx);
97 if (ret)
98 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
99 }
100
101 return ret;
102 }
103
104 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
105 {
106 int rc = 0;
107
108 if (init) {
109 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
110 USB_PHY_3P3_VOL_MAX);
111 if (rc) {
112 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
113 goto exit;
114 }
115 rc = regulator_enable(motg->v3p3);
116 if (rc) {
117 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
118 goto exit;
119 }
120 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
121 USB_PHY_1P8_VOL_MAX);
122 if (rc) {
123 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
124 goto disable_3p3;
125 }
126 rc = regulator_enable(motg->v1p8);
127 if (rc) {
128 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
129 goto disable_3p3;
130 }
131
132 return 0;
133 }
134
135 regulator_disable(motg->v1p8);
136 disable_3p3:
137 regulator_disable(motg->v3p3);
138 exit:
139 return rc;
140 }
141
142 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
143 {
144 int ret = 0;
145
146 if (on) {
147 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
148 if (ret < 0) {
149 pr_err("Could not set HPM for v1p8\n");
150 return ret;
151 }
152 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
153 if (ret < 0) {
154 pr_err("Could not set HPM for v3p3\n");
155 regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
156 return ret;
157 }
158 } else {
159 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
160 if (ret < 0)
161 pr_err("Could not set LPM for v1p8\n");
162 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
163 if (ret < 0)
164 pr_err("Could not set LPM for v3p3\n");
165 }
166
167 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
168 return ret < 0 ? ret : 0;
169 }
170
171 static int ulpi_read(struct usb_phy *phy, u32 reg)
172 {
173 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
174 int cnt = 0;
175
176 /* initiate read operation */
177 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
178 USB_ULPI_VIEWPORT);
179
180 /* wait for completion */
181 while (cnt < ULPI_IO_TIMEOUT_USEC) {
182 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
183 break;
184 udelay(1);
185 cnt++;
186 }
187
188 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
189 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
190 readl(USB_ULPI_VIEWPORT));
191 return -ETIMEDOUT;
192 }
193 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
194 }
195
196 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
197 {
198 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
199 int cnt = 0;
200
201 /* initiate write operation */
202 writel(ULPI_RUN | ULPI_WRITE |
203 ULPI_ADDR(reg) | ULPI_DATA(val),
204 USB_ULPI_VIEWPORT);
205
206 /* wait for completion */
207 while (cnt < ULPI_IO_TIMEOUT_USEC) {
208 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
209 break;
210 udelay(1);
211 cnt++;
212 }
213
214 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
215 dev_err(phy->dev, "ulpi_write: timeout\n");
216 return -ETIMEDOUT;
217 }
218 return 0;
219 }
220
221 static struct usb_phy_io_ops msm_otg_io_ops = {
222 .read = ulpi_read,
223 .write = ulpi_write,
224 };
225
226 static void ulpi_init(struct msm_otg *motg)
227 {
228 struct msm_otg_platform_data *pdata = motg->pdata;
229 int *seq = pdata->phy_init_seq, idx;
230 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
231
232 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
233 if (seq[idx] == -1)
234 continue;
235
236 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
237 seq[idx], addr + idx);
238 ulpi_write(&motg->phy, seq[idx], addr + idx);
239 }
240 }
241
242 static int msm_phy_notify_disconnect(struct usb_phy *phy,
243 enum usb_device_speed speed)
244 {
245 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
246 int val;
247
248 if (motg->manual_pullup) {
249 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
250 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
251 }
252
253 /*
254 * Put the transceiver in non-driving mode. Otherwise host
255 * may not detect soft-disconnection.
256 */
257 val = ulpi_read(phy, ULPI_FUNC_CTRL);
258 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
259 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
260 ulpi_write(phy, val, ULPI_FUNC_CTRL);
261
262 return 0;
263 }
264
265 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
266 {
267 int ret;
268
269 if (assert)
270 ret = reset_control_assert(motg->link_rst);
271 else
272 ret = reset_control_deassert(motg->link_rst);
273
274 if (ret)
275 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
276 assert ? "assert" : "deassert");
277
278 return ret;
279 }
280
281 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
282 {
283 int ret = 0;
284
285 if (motg->phy_rst)
286 ret = reset_control_reset(motg->phy_rst);
287
288 if (ret)
289 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
290
291 return ret;
292 }
293
294 static int msm_link_reset(struct msm_otg *motg)
295 {
296 u32 val;
297 int ret;
298
299 ret = msm_otg_link_clk_reset(motg, 1);
300 if (ret)
301 return ret;
302
303 /* wait for 1ms delay as suggested in HPG. */
304 usleep_range(1000, 1200);
305
306 ret = msm_otg_link_clk_reset(motg, 0);
307 if (ret)
308 return ret;
309
310 if (motg->phy_number)
311 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
312
313 /* put transceiver in serial mode as part of reset */
314 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
315 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
316
317 return 0;
318 }
319
320 static int msm_otg_reset(struct usb_phy *phy)
321 {
322 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
323 int cnt = 0;
324
325 writel(USBCMD_RESET, USB_USBCMD);
326 while (cnt < LINK_RESET_TIMEOUT_USEC) {
327 if (!(readl(USB_USBCMD) & USBCMD_RESET))
328 break;
329 udelay(1);
330 cnt++;
331 }
332 if (cnt >= LINK_RESET_TIMEOUT_USEC)
333 return -ETIMEDOUT;
334
335 /* select ULPI phy and clear other status/control bits in PORTSC */
336 writel(PORTSC_PTS_ULPI, USB_PORTSC);
337
338 writel(0x0, USB_AHBBURST);
339 writel(0x08, USB_AHBMODE);
340
341 if (motg->phy_number)
342 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
343 return 0;
344 }
345
346 static void msm_phy_reset(struct msm_otg *motg)
347 {
348 void __iomem *addr;
349
350 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
351 msm_otg_phy_clk_reset(motg);
352 return;
353 }
354
355 addr = USB_PHY_CTRL;
356 if (motg->phy_number)
357 addr = USB_PHY_CTRL2;
358
359 /* Assert USB PHY_POR */
360 writel(readl(addr) | PHY_POR_ASSERT, addr);
361
362 /*
363 * wait for minimum 10 microseconds as suggested in HPG.
364 * Use a slightly larger value since the exact value didn't
365 * work 100% of the time.
366 */
367 udelay(12);
368
369 /* Deassert USB PHY_POR */
370 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
371 }
372
373 static int msm_usb_reset(struct usb_phy *phy)
374 {
375 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
376 int ret;
377
378 if (!IS_ERR(motg->core_clk))
379 clk_prepare_enable(motg->core_clk);
380
381 ret = msm_link_reset(motg);
382 if (ret) {
383 dev_err(phy->dev, "phy_reset failed\n");
384 return ret;
385 }
386
387 ret = msm_otg_reset(&motg->phy);
388 if (ret) {
389 dev_err(phy->dev, "link reset failed\n");
390 return ret;
391 }
392
393 msleep(100);
394
395 /* Reset USB PHY after performing USB Link RESET */
396 msm_phy_reset(motg);
397
398 if (!IS_ERR(motg->core_clk))
399 clk_disable_unprepare(motg->core_clk);
400
401 return 0;
402 }
403
404 static int msm_phy_init(struct usb_phy *phy)
405 {
406 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
407 struct msm_otg_platform_data *pdata = motg->pdata;
408 u32 val, ulpi_val = 0;
409
410 /* Program USB PHY Override registers. */
411 ulpi_init(motg);
412
413 /*
414 * It is recommended in HPG to reset USB PHY after programming
415 * USB PHY Override registers.
416 */
417 msm_phy_reset(motg);
418
419 if (pdata->otg_control == OTG_PHY_CONTROL) {
420 val = readl(USB_OTGSC);
421 if (pdata->mode == USB_DR_MODE_OTG) {
422 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
423 val |= OTGSC_IDIE | OTGSC_BSVIE;
424 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
425 ulpi_val = ULPI_INT_SESS_VALID;
426 val |= OTGSC_BSVIE;
427 }
428 writel(val, USB_OTGSC);
429 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
430 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
431 }
432
433 if (motg->manual_pullup) {
434 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
435 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
436
437 val = readl(USB_GENCONFIG_2);
438 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
439 writel(val, USB_GENCONFIG_2);
440
441 val = readl(USB_USBCMD);
442 val |= USBCMD_SESS_VLD_CTRL;
443 writel(val, USB_USBCMD);
444
445 val = ulpi_read(phy, ULPI_FUNC_CTRL);
446 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
447 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
448 ulpi_write(phy, val, ULPI_FUNC_CTRL);
449 }
450
451 if (motg->phy_number)
452 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
453
454 return 0;
455 }
456
457 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
458 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
459
460 #ifdef CONFIG_PM
461
462 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
463 {
464 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
465 int min_vol;
466 int ret;
467
468 if (high)
469 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
470 else
471 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
472
473 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
474 if (ret) {
475 pr_err("Cannot set vddcx voltage\n");
476 return ret;
477 }
478
479 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
480
481 return ret;
482 }
483
484 static int msm_otg_suspend(struct msm_otg *motg)
485 {
486 struct usb_phy *phy = &motg->phy;
487 struct usb_bus *bus = phy->otg->host;
488 struct msm_otg_platform_data *pdata = motg->pdata;
489 void __iomem *addr;
490 int cnt = 0;
491
492 if (atomic_read(&motg->in_lpm))
493 return 0;
494
495 disable_irq(motg->irq);
496 /*
497 * Chipidea 45-nm PHY suspend sequence:
498 *
499 * Interrupt Latch Register auto-clear feature is not present
500 * in all PHY versions. Latch register is clear on read type.
501 * Clear latch register to avoid spurious wakeup from
502 * low power mode (LPM).
503 *
504 * PHY comparators are disabled when PHY enters into low power
505 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
506 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
507 * PHY comparators. This save significant amount of power.
508 *
509 * PLL is not turned off when PHY enters into low power mode (LPM).
510 * Disable PLL for maximum power savings.
511 */
512
513 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
514 ulpi_read(phy, 0x14);
515 if (pdata->otg_control == OTG_PHY_CONTROL)
516 ulpi_write(phy, 0x01, 0x30);
517 ulpi_write(phy, 0x08, 0x09);
518 }
519
520 /*
521 * PHY may take some time or even fail to enter into low power
522 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
523 * in failure case.
524 */
525 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
526 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
527 if (readl(USB_PORTSC) & PORTSC_PHCD)
528 break;
529 udelay(1);
530 cnt++;
531 }
532
533 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
534 dev_err(phy->dev, "Unable to suspend PHY\n");
535 msm_otg_reset(phy);
536 enable_irq(motg->irq);
537 return -ETIMEDOUT;
538 }
539
540 /*
541 * PHY has capability to generate interrupt asynchronously in low
542 * power mode (LPM). This interrupt is level triggered. So USB IRQ
543 * line must be disabled till async interrupt enable bit is cleared
544 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
545 * block data communication from PHY.
546 */
547 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
548
549 addr = USB_PHY_CTRL;
550 if (motg->phy_number)
551 addr = USB_PHY_CTRL2;
552
553 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
554 motg->pdata->otg_control == OTG_PMIC_CONTROL)
555 writel(readl(addr) | PHY_RETEN, addr);
556
557 clk_disable_unprepare(motg->pclk);
558 clk_disable_unprepare(motg->clk);
559 if (!IS_ERR(motg->core_clk))
560 clk_disable_unprepare(motg->core_clk);
561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564 msm_hsusb_ldo_set_mode(motg, 0);
565 msm_hsusb_config_vddcx(motg, 0);
566 }
567
568 if (device_may_wakeup(phy->dev))
569 enable_irq_wake(motg->irq);
570 if (bus)
571 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
572
573 atomic_set(&motg->in_lpm, 1);
574 enable_irq(motg->irq);
575
576 dev_info(phy->dev, "USB in low power mode\n");
577
578 return 0;
579 }
580
581 static int msm_otg_resume(struct msm_otg *motg)
582 {
583 struct usb_phy *phy = &motg->phy;
584 struct usb_bus *bus = phy->otg->host;
585 void __iomem *addr;
586 int cnt = 0;
587 unsigned temp;
588
589 if (!atomic_read(&motg->in_lpm))
590 return 0;
591
592 clk_prepare_enable(motg->pclk);
593 clk_prepare_enable(motg->clk);
594 if (!IS_ERR(motg->core_clk))
595 clk_prepare_enable(motg->core_clk);
596
597 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
598 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
599
600 addr = USB_PHY_CTRL;
601 if (motg->phy_number)
602 addr = USB_PHY_CTRL2;
603
604 msm_hsusb_ldo_set_mode(motg, 1);
605 msm_hsusb_config_vddcx(motg, 1);
606 writel(readl(addr) & ~PHY_RETEN, addr);
607 }
608
609 temp = readl(USB_USBCMD);
610 temp &= ~ASYNC_INTR_CTRL;
611 temp &= ~ULPI_STP_CTRL;
612 writel(temp, USB_USBCMD);
613
614 /*
615 * PHY comes out of low power mode (LPM) in case of wakeup
616 * from asynchronous interrupt.
617 */
618 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
619 goto skip_phy_resume;
620
621 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
622 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
623 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
624 break;
625 udelay(1);
626 cnt++;
627 }
628
629 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
630 /*
631 * This is a fatal error. Reset the link and
632 * PHY. USB state can not be restored. Re-insertion
633 * of USB cable is the only way to get USB working.
634 */
635 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
636 msm_otg_reset(phy);
637 }
638
639 skip_phy_resume:
640 if (device_may_wakeup(phy->dev))
641 disable_irq_wake(motg->irq);
642 if (bus)
643 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
644
645 atomic_set(&motg->in_lpm, 0);
646
647 if (motg->async_int) {
648 motg->async_int = 0;
649 pm_runtime_put(phy->dev);
650 enable_irq(motg->irq);
651 }
652
653 dev_info(phy->dev, "USB exited from low power mode\n");
654
655 return 0;
656 }
657 #endif
658
659 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
660 {
661 if (motg->cur_power == mA)
662 return;
663
664 /* TODO: Notify PMIC about available current */
665 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
666 motg->cur_power = mA;
667 }
668
669 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
670 {
671 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
672
673 /*
674 * Gadget driver uses set_power method to notify about the
675 * available current based on suspend/configured states.
676 *
677 * IDEV_CHG can be drawn irrespective of suspend/un-configured
678 * states when CDP/ACA is connected.
679 */
680 if (motg->chg_type == USB_SDP_CHARGER)
681 msm_otg_notify_charger(motg, mA);
682
683 return 0;
684 }
685
686 static void msm_otg_start_host(struct usb_phy *phy, int on)
687 {
688 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
689 struct msm_otg_platform_data *pdata = motg->pdata;
690 struct usb_hcd *hcd;
691
692 if (!phy->otg->host)
693 return;
694
695 hcd = bus_to_hcd(phy->otg->host);
696
697 if (on) {
698 dev_dbg(phy->dev, "host on\n");
699
700 if (pdata->vbus_power)
701 pdata->vbus_power(1);
702 /*
703 * Some boards have a switch cotrolled by gpio
704 * to enable/disable internal HUB. Enable internal
705 * HUB before kicking the host.
706 */
707 if (pdata->setup_gpio)
708 pdata->setup_gpio(OTG_STATE_A_HOST);
709 #ifdef CONFIG_USB
710 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
711 device_wakeup_enable(hcd->self.controller);
712 #endif
713 } else {
714 dev_dbg(phy->dev, "host off\n");
715
716 #ifdef CONFIG_USB
717 usb_remove_hcd(hcd);
718 #endif
719 if (pdata->setup_gpio)
720 pdata->setup_gpio(OTG_STATE_UNDEFINED);
721 if (pdata->vbus_power)
722 pdata->vbus_power(0);
723 }
724 }
725
726 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
727 {
728 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
729 struct usb_hcd *hcd;
730
731 /*
732 * Fail host registration if this board can support
733 * only peripheral configuration.
734 */
735 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
736 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
737 return -ENODEV;
738 }
739
740 if (!host) {
741 if (otg->state == OTG_STATE_A_HOST) {
742 pm_runtime_get_sync(otg->usb_phy->dev);
743 msm_otg_start_host(otg->usb_phy, 0);
744 otg->host = NULL;
745 otg->state = OTG_STATE_UNDEFINED;
746 schedule_work(&motg->sm_work);
747 } else {
748 otg->host = NULL;
749 }
750
751 return 0;
752 }
753
754 hcd = bus_to_hcd(host);
755 hcd->power_budget = motg->pdata->power_budget;
756
757 otg->host = host;
758 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
759
760 /*
761 * Kick the state machine work, if peripheral is not supported
762 * or peripheral is already registered with us.
763 */
764 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
765 pm_runtime_get_sync(otg->usb_phy->dev);
766 schedule_work(&motg->sm_work);
767 }
768
769 return 0;
770 }
771
772 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
773 {
774 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
775 struct msm_otg_platform_data *pdata = motg->pdata;
776
777 if (!phy->otg->gadget)
778 return;
779
780 if (on) {
781 dev_dbg(phy->dev, "gadget on\n");
782 /*
783 * Some boards have a switch cotrolled by gpio
784 * to enable/disable internal HUB. Disable internal
785 * HUB before kicking the gadget.
786 */
787 if (pdata->setup_gpio)
788 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
789 usb_gadget_vbus_connect(phy->otg->gadget);
790 } else {
791 dev_dbg(phy->dev, "gadget off\n");
792 usb_gadget_vbus_disconnect(phy->otg->gadget);
793 if (pdata->setup_gpio)
794 pdata->setup_gpio(OTG_STATE_UNDEFINED);
795 }
796
797 }
798
799 static int msm_otg_set_peripheral(struct usb_otg *otg,
800 struct usb_gadget *gadget)
801 {
802 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
803
804 /*
805 * Fail peripheral registration if this board can support
806 * only host configuration.
807 */
808 if (motg->pdata->mode == USB_DR_MODE_HOST) {
809 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
810 return -ENODEV;
811 }
812
813 if (!gadget) {
814 if (otg->state == OTG_STATE_B_PERIPHERAL) {
815 pm_runtime_get_sync(otg->usb_phy->dev);
816 msm_otg_start_peripheral(otg->usb_phy, 0);
817 otg->gadget = NULL;
818 otg->state = OTG_STATE_UNDEFINED;
819 schedule_work(&motg->sm_work);
820 } else {
821 otg->gadget = NULL;
822 }
823
824 return 0;
825 }
826 otg->gadget = gadget;
827 dev_dbg(otg->usb_phy->dev,
828 "peripheral driver registered w/ tranceiver\n");
829
830 /*
831 * Kick the state machine work, if host is not supported
832 * or host is already registered with us.
833 */
834 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
835 pm_runtime_get_sync(otg->usb_phy->dev);
836 schedule_work(&motg->sm_work);
837 }
838
839 return 0;
840 }
841
842 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
843 {
844 struct usb_phy *phy = &motg->phy;
845 u32 chg_det;
846 bool ret = false;
847
848 switch (motg->pdata->phy_type) {
849 case CI_45NM_INTEGRATED_PHY:
850 chg_det = ulpi_read(phy, 0x34);
851 ret = chg_det & (1 << 4);
852 break;
853 case SNPS_28NM_INTEGRATED_PHY:
854 chg_det = ulpi_read(phy, 0x87);
855 ret = chg_det & 1;
856 break;
857 default:
858 break;
859 }
860 return ret;
861 }
862
863 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
864 {
865 struct usb_phy *phy = &motg->phy;
866 u32 chg_det;
867
868 switch (motg->pdata->phy_type) {
869 case CI_45NM_INTEGRATED_PHY:
870 chg_det = ulpi_read(phy, 0x34);
871 /* Turn off charger block */
872 chg_det |= ~(1 << 1);
873 ulpi_write(phy, chg_det, 0x34);
874 udelay(20);
875 /* control chg block via ULPI */
876 chg_det &= ~(1 << 3);
877 ulpi_write(phy, chg_det, 0x34);
878 /* put it in host mode for enabling D- source */
879 chg_det &= ~(1 << 2);
880 ulpi_write(phy, chg_det, 0x34);
881 /* Turn on chg detect block */
882 chg_det &= ~(1 << 1);
883 ulpi_write(phy, chg_det, 0x34);
884 udelay(20);
885 /* enable chg detection */
886 chg_det &= ~(1 << 0);
887 ulpi_write(phy, chg_det, 0x34);
888 break;
889 case SNPS_28NM_INTEGRATED_PHY:
890 /*
891 * Configure DM as current source, DP as current sink
892 * and enable battery charging comparators.
893 */
894 ulpi_write(phy, 0x8, 0x85);
895 ulpi_write(phy, 0x2, 0x85);
896 ulpi_write(phy, 0x1, 0x85);
897 break;
898 default:
899 break;
900 }
901 }
902
903 static bool msm_chg_check_primary_det(struct msm_otg *motg)
904 {
905 struct usb_phy *phy = &motg->phy;
906 u32 chg_det;
907 bool ret = false;
908
909 switch (motg->pdata->phy_type) {
910 case CI_45NM_INTEGRATED_PHY:
911 chg_det = ulpi_read(phy, 0x34);
912 ret = chg_det & (1 << 4);
913 break;
914 case SNPS_28NM_INTEGRATED_PHY:
915 chg_det = ulpi_read(phy, 0x87);
916 ret = chg_det & 1;
917 break;
918 default:
919 break;
920 }
921 return ret;
922 }
923
924 static void msm_chg_enable_primary_det(struct msm_otg *motg)
925 {
926 struct usb_phy *phy = &motg->phy;
927 u32 chg_det;
928
929 switch (motg->pdata->phy_type) {
930 case CI_45NM_INTEGRATED_PHY:
931 chg_det = ulpi_read(phy, 0x34);
932 /* enable chg detection */
933 chg_det &= ~(1 << 0);
934 ulpi_write(phy, chg_det, 0x34);
935 break;
936 case SNPS_28NM_INTEGRATED_PHY:
937 /*
938 * Configure DP as current source, DM as current sink
939 * and enable battery charging comparators.
940 */
941 ulpi_write(phy, 0x2, 0x85);
942 ulpi_write(phy, 0x1, 0x85);
943 break;
944 default:
945 break;
946 }
947 }
948
949 static bool msm_chg_check_dcd(struct msm_otg *motg)
950 {
951 struct usb_phy *phy = &motg->phy;
952 u32 line_state;
953 bool ret = false;
954
955 switch (motg->pdata->phy_type) {
956 case CI_45NM_INTEGRATED_PHY:
957 line_state = ulpi_read(phy, 0x15);
958 ret = !(line_state & 1);
959 break;
960 case SNPS_28NM_INTEGRATED_PHY:
961 line_state = ulpi_read(phy, 0x87);
962 ret = line_state & 2;
963 break;
964 default:
965 break;
966 }
967 return ret;
968 }
969
970 static void msm_chg_disable_dcd(struct msm_otg *motg)
971 {
972 struct usb_phy *phy = &motg->phy;
973 u32 chg_det;
974
975 switch (motg->pdata->phy_type) {
976 case CI_45NM_INTEGRATED_PHY:
977 chg_det = ulpi_read(phy, 0x34);
978 chg_det &= ~(1 << 5);
979 ulpi_write(phy, chg_det, 0x34);
980 break;
981 case SNPS_28NM_INTEGRATED_PHY:
982 ulpi_write(phy, 0x10, 0x86);
983 break;
984 default:
985 break;
986 }
987 }
988
989 static void msm_chg_enable_dcd(struct msm_otg *motg)
990 {
991 struct usb_phy *phy = &motg->phy;
992 u32 chg_det;
993
994 switch (motg->pdata->phy_type) {
995 case CI_45NM_INTEGRATED_PHY:
996 chg_det = ulpi_read(phy, 0x34);
997 /* Turn on D+ current source */
998 chg_det |= (1 << 5);
999 ulpi_write(phy, chg_det, 0x34);
1000 break;
1001 case SNPS_28NM_INTEGRATED_PHY:
1002 /* Data contact detection enable */
1003 ulpi_write(phy, 0x10, 0x85);
1004 break;
1005 default:
1006 break;
1007 }
1008 }
1009
1010 static void msm_chg_block_on(struct msm_otg *motg)
1011 {
1012 struct usb_phy *phy = &motg->phy;
1013 u32 func_ctrl, chg_det;
1014
1015 /* put the controller in non-driving mode */
1016 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1017 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1018 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1019 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1020
1021 switch (motg->pdata->phy_type) {
1022 case CI_45NM_INTEGRATED_PHY:
1023 chg_det = ulpi_read(phy, 0x34);
1024 /* control chg block via ULPI */
1025 chg_det &= ~(1 << 3);
1026 ulpi_write(phy, chg_det, 0x34);
1027 /* Turn on chg detect block */
1028 chg_det &= ~(1 << 1);
1029 ulpi_write(phy, chg_det, 0x34);
1030 udelay(20);
1031 break;
1032 case SNPS_28NM_INTEGRATED_PHY:
1033 /* Clear charger detecting control bits */
1034 ulpi_write(phy, 0x3F, 0x86);
1035 /* Clear alt interrupt latch and enable bits */
1036 ulpi_write(phy, 0x1F, 0x92);
1037 ulpi_write(phy, 0x1F, 0x95);
1038 udelay(100);
1039 break;
1040 default:
1041 break;
1042 }
1043 }
1044
1045 static void msm_chg_block_off(struct msm_otg *motg)
1046 {
1047 struct usb_phy *phy = &motg->phy;
1048 u32 func_ctrl, chg_det;
1049
1050 switch (motg->pdata->phy_type) {
1051 case CI_45NM_INTEGRATED_PHY:
1052 chg_det = ulpi_read(phy, 0x34);
1053 /* Turn off charger block */
1054 chg_det |= ~(1 << 1);
1055 ulpi_write(phy, chg_det, 0x34);
1056 break;
1057 case SNPS_28NM_INTEGRATED_PHY:
1058 /* Clear charger detecting control bits */
1059 ulpi_write(phy, 0x3F, 0x86);
1060 /* Clear alt interrupt latch and enable bits */
1061 ulpi_write(phy, 0x1F, 0x92);
1062 ulpi_write(phy, 0x1F, 0x95);
1063 break;
1064 default:
1065 break;
1066 }
1067
1068 /* put the controller in normal mode */
1069 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1070 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1071 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1072 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1073 }
1074
1075 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1076 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1077 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1078 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1079 static void msm_chg_detect_work(struct work_struct *w)
1080 {
1081 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1082 struct usb_phy *phy = &motg->phy;
1083 bool is_dcd, tmout, vout;
1084 unsigned long delay;
1085
1086 dev_dbg(phy->dev, "chg detection work\n");
1087 switch (motg->chg_state) {
1088 case USB_CHG_STATE_UNDEFINED:
1089 pm_runtime_get_sync(phy->dev);
1090 msm_chg_block_on(motg);
1091 msm_chg_enable_dcd(motg);
1092 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1093 motg->dcd_retries = 0;
1094 delay = MSM_CHG_DCD_POLL_TIME;
1095 break;
1096 case USB_CHG_STATE_WAIT_FOR_DCD:
1097 is_dcd = msm_chg_check_dcd(motg);
1098 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1099 if (is_dcd || tmout) {
1100 msm_chg_disable_dcd(motg);
1101 msm_chg_enable_primary_det(motg);
1102 delay = MSM_CHG_PRIMARY_DET_TIME;
1103 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1104 } else {
1105 delay = MSM_CHG_DCD_POLL_TIME;
1106 }
1107 break;
1108 case USB_CHG_STATE_DCD_DONE:
1109 vout = msm_chg_check_primary_det(motg);
1110 if (vout) {
1111 msm_chg_enable_secondary_det(motg);
1112 delay = MSM_CHG_SECONDARY_DET_TIME;
1113 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1114 } else {
1115 motg->chg_type = USB_SDP_CHARGER;
1116 motg->chg_state = USB_CHG_STATE_DETECTED;
1117 delay = 0;
1118 }
1119 break;
1120 case USB_CHG_STATE_PRIMARY_DONE:
1121 vout = msm_chg_check_secondary_det(motg);
1122 if (vout)
1123 motg->chg_type = USB_DCP_CHARGER;
1124 else
1125 motg->chg_type = USB_CDP_CHARGER;
1126 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1127 /* fall through */
1128 case USB_CHG_STATE_SECONDARY_DONE:
1129 motg->chg_state = USB_CHG_STATE_DETECTED;
1130 case USB_CHG_STATE_DETECTED:
1131 msm_chg_block_off(motg);
1132 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1133 schedule_work(&motg->sm_work);
1134 return;
1135 default:
1136 return;
1137 }
1138
1139 schedule_delayed_work(&motg->chg_work, delay);
1140 }
1141
1142 /*
1143 * We support OTG, Peripheral only and Host only configurations. In case
1144 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1145 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1146 * enabled when switch is controlled by user and default mode is supplied
1147 * by board file, which can be changed by userspace later.
1148 */
1149 static void msm_otg_init_sm(struct msm_otg *motg)
1150 {
1151 struct msm_otg_platform_data *pdata = motg->pdata;
1152 u32 otgsc = readl(USB_OTGSC);
1153
1154 switch (pdata->mode) {
1155 case USB_DR_MODE_OTG:
1156 if (pdata->otg_control == OTG_PHY_CONTROL) {
1157 if (otgsc & OTGSC_ID)
1158 set_bit(ID, &motg->inputs);
1159 else
1160 clear_bit(ID, &motg->inputs);
1161
1162 if (otgsc & OTGSC_BSV)
1163 set_bit(B_SESS_VLD, &motg->inputs);
1164 else
1165 clear_bit(B_SESS_VLD, &motg->inputs);
1166 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1167 set_bit(ID, &motg->inputs);
1168 clear_bit(B_SESS_VLD, &motg->inputs);
1169 }
1170 break;
1171 case USB_DR_MODE_HOST:
1172 clear_bit(ID, &motg->inputs);
1173 break;
1174 case USB_DR_MODE_PERIPHERAL:
1175 set_bit(ID, &motg->inputs);
1176 if (otgsc & OTGSC_BSV)
1177 set_bit(B_SESS_VLD, &motg->inputs);
1178 else
1179 clear_bit(B_SESS_VLD, &motg->inputs);
1180 break;
1181 default:
1182 break;
1183 }
1184 }
1185
1186 static void msm_otg_sm_work(struct work_struct *w)
1187 {
1188 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1189 struct usb_otg *otg = motg->phy.otg;
1190
1191 switch (otg->state) {
1192 case OTG_STATE_UNDEFINED:
1193 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1194 msm_otg_reset(otg->usb_phy);
1195 msm_otg_init_sm(motg);
1196 otg->state = OTG_STATE_B_IDLE;
1197 /* FALL THROUGH */
1198 case OTG_STATE_B_IDLE:
1199 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1200 if (!test_bit(ID, &motg->inputs) && otg->host) {
1201 /* disable BSV bit */
1202 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1203 msm_otg_start_host(otg->usb_phy, 1);
1204 otg->state = OTG_STATE_A_HOST;
1205 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1206 switch (motg->chg_state) {
1207 case USB_CHG_STATE_UNDEFINED:
1208 msm_chg_detect_work(&motg->chg_work.work);
1209 break;
1210 case USB_CHG_STATE_DETECTED:
1211 switch (motg->chg_type) {
1212 case USB_DCP_CHARGER:
1213 msm_otg_notify_charger(motg,
1214 IDEV_CHG_MAX);
1215 break;
1216 case USB_CDP_CHARGER:
1217 msm_otg_notify_charger(motg,
1218 IDEV_CHG_MAX);
1219 msm_otg_start_peripheral(otg->usb_phy,
1220 1);
1221 otg->state
1222 = OTG_STATE_B_PERIPHERAL;
1223 break;
1224 case USB_SDP_CHARGER:
1225 msm_otg_notify_charger(motg, IUNIT);
1226 msm_otg_start_peripheral(otg->usb_phy,
1227 1);
1228 otg->state
1229 = OTG_STATE_B_PERIPHERAL;
1230 break;
1231 default:
1232 break;
1233 }
1234 break;
1235 default:
1236 break;
1237 }
1238 } else {
1239 /*
1240 * If charger detection work is pending, decrement
1241 * the pm usage counter to balance with the one that
1242 * is incremented in charger detection work.
1243 */
1244 if (cancel_delayed_work_sync(&motg->chg_work)) {
1245 pm_runtime_put_sync(otg->usb_phy->dev);
1246 msm_otg_reset(otg->usb_phy);
1247 }
1248 msm_otg_notify_charger(motg, 0);
1249 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1250 motg->chg_type = USB_INVALID_CHARGER;
1251 }
1252
1253 if (otg->state == OTG_STATE_B_IDLE)
1254 pm_runtime_put_sync(otg->usb_phy->dev);
1255 break;
1256 case OTG_STATE_B_PERIPHERAL:
1257 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1258 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1259 !test_bit(ID, &motg->inputs)) {
1260 msm_otg_notify_charger(motg, 0);
1261 msm_otg_start_peripheral(otg->usb_phy, 0);
1262 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1263 motg->chg_type = USB_INVALID_CHARGER;
1264 otg->state = OTG_STATE_B_IDLE;
1265 msm_otg_reset(otg->usb_phy);
1266 schedule_work(w);
1267 }
1268 break;
1269 case OTG_STATE_A_HOST:
1270 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1271 if (test_bit(ID, &motg->inputs)) {
1272 msm_otg_start_host(otg->usb_phy, 0);
1273 otg->state = OTG_STATE_B_IDLE;
1274 msm_otg_reset(otg->usb_phy);
1275 schedule_work(w);
1276 }
1277 break;
1278 default:
1279 break;
1280 }
1281 }
1282
1283 static irqreturn_t msm_otg_irq(int irq, void *data)
1284 {
1285 struct msm_otg *motg = data;
1286 struct usb_phy *phy = &motg->phy;
1287 u32 otgsc = 0;
1288
1289 if (atomic_read(&motg->in_lpm)) {
1290 disable_irq_nosync(irq);
1291 motg->async_int = 1;
1292 pm_runtime_get(phy->dev);
1293 return IRQ_HANDLED;
1294 }
1295
1296 otgsc = readl(USB_OTGSC);
1297 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1298 return IRQ_NONE;
1299
1300 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1301 if (otgsc & OTGSC_ID)
1302 set_bit(ID, &motg->inputs);
1303 else
1304 clear_bit(ID, &motg->inputs);
1305 dev_dbg(phy->dev, "ID set/clear\n");
1306 pm_runtime_get_noresume(phy->dev);
1307 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1308 if (otgsc & OTGSC_BSV)
1309 set_bit(B_SESS_VLD, &motg->inputs);
1310 else
1311 clear_bit(B_SESS_VLD, &motg->inputs);
1312 dev_dbg(phy->dev, "BSV set/clear\n");
1313 pm_runtime_get_noresume(phy->dev);
1314 }
1315
1316 writel(otgsc, USB_OTGSC);
1317 schedule_work(&motg->sm_work);
1318 return IRQ_HANDLED;
1319 }
1320
1321 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1322 {
1323 struct msm_otg *motg = s->private;
1324 struct usb_otg *otg = motg->phy.otg;
1325
1326 switch (otg->state) {
1327 case OTG_STATE_A_HOST:
1328 seq_puts(s, "host\n");
1329 break;
1330 case OTG_STATE_B_PERIPHERAL:
1331 seq_puts(s, "peripheral\n");
1332 break;
1333 default:
1334 seq_puts(s, "none\n");
1335 break;
1336 }
1337
1338 return 0;
1339 }
1340
1341 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1342 {
1343 return single_open(file, msm_otg_mode_show, inode->i_private);
1344 }
1345
1346 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1347 size_t count, loff_t *ppos)
1348 {
1349 struct seq_file *s = file->private_data;
1350 struct msm_otg *motg = s->private;
1351 char buf[16];
1352 struct usb_otg *otg = motg->phy.otg;
1353 int status = count;
1354 enum usb_dr_mode req_mode;
1355
1356 memset(buf, 0x00, sizeof(buf));
1357
1358 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1359 status = -EFAULT;
1360 goto out;
1361 }
1362
1363 if (!strncmp(buf, "host", 4)) {
1364 req_mode = USB_DR_MODE_HOST;
1365 } else if (!strncmp(buf, "peripheral", 10)) {
1366 req_mode = USB_DR_MODE_PERIPHERAL;
1367 } else if (!strncmp(buf, "none", 4)) {
1368 req_mode = USB_DR_MODE_UNKNOWN;
1369 } else {
1370 status = -EINVAL;
1371 goto out;
1372 }
1373
1374 switch (req_mode) {
1375 case USB_DR_MODE_UNKNOWN:
1376 switch (otg->state) {
1377 case OTG_STATE_A_HOST:
1378 case OTG_STATE_B_PERIPHERAL:
1379 set_bit(ID, &motg->inputs);
1380 clear_bit(B_SESS_VLD, &motg->inputs);
1381 break;
1382 default:
1383 goto out;
1384 }
1385 break;
1386 case USB_DR_MODE_PERIPHERAL:
1387 switch (otg->state) {
1388 case OTG_STATE_B_IDLE:
1389 case OTG_STATE_A_HOST:
1390 set_bit(ID, &motg->inputs);
1391 set_bit(B_SESS_VLD, &motg->inputs);
1392 break;
1393 default:
1394 goto out;
1395 }
1396 break;
1397 case USB_DR_MODE_HOST:
1398 switch (otg->state) {
1399 case OTG_STATE_B_IDLE:
1400 case OTG_STATE_B_PERIPHERAL:
1401 clear_bit(ID, &motg->inputs);
1402 break;
1403 default:
1404 goto out;
1405 }
1406 break;
1407 default:
1408 goto out;
1409 }
1410
1411 pm_runtime_get_sync(otg->usb_phy->dev);
1412 schedule_work(&motg->sm_work);
1413 out:
1414 return status;
1415 }
1416
1417 static const struct file_operations msm_otg_mode_fops = {
1418 .open = msm_otg_mode_open,
1419 .read = seq_read,
1420 .write = msm_otg_mode_write,
1421 .llseek = seq_lseek,
1422 .release = single_release,
1423 };
1424
1425 static struct dentry *msm_otg_dbg_root;
1426 static struct dentry *msm_otg_dbg_mode;
1427
1428 static int msm_otg_debugfs_init(struct msm_otg *motg)
1429 {
1430 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1431
1432 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1433 return -ENODEV;
1434
1435 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1436 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1437 if (!msm_otg_dbg_mode) {
1438 debugfs_remove(msm_otg_dbg_root);
1439 msm_otg_dbg_root = NULL;
1440 return -ENODEV;
1441 }
1442
1443 return 0;
1444 }
1445
1446 static void msm_otg_debugfs_cleanup(void)
1447 {
1448 debugfs_remove(msm_otg_dbg_mode);
1449 debugfs_remove(msm_otg_dbg_root);
1450 }
1451
1452 static const struct of_device_id msm_otg_dt_match[] = {
1453 {
1454 .compatible = "qcom,usb-otg-ci",
1455 .data = (void *) CI_45NM_INTEGRATED_PHY
1456 },
1457 {
1458 .compatible = "qcom,usb-otg-snps",
1459 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1460 },
1461 { }
1462 };
1463 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1464
1465 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1466 void *ptr)
1467 {
1468 struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb);
1469 struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus);
1470
1471 if (event)
1472 set_bit(B_SESS_VLD, &motg->inputs);
1473 else
1474 clear_bit(B_SESS_VLD, &motg->inputs);
1475
1476 if (test_bit(B_SESS_VLD, &motg->inputs)) {
1477 /* Switch D+/D- lines to Device connector */
1478 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1479 } else {
1480 /* Switch D+/D- lines to Hub */
1481 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1482 }
1483
1484 schedule_work(&motg->sm_work);
1485
1486 return NOTIFY_DONE;
1487 }
1488
1489 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1490 void *ptr)
1491 {
1492 struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb);
1493 struct msm_otg *motg = container_of(id, struct msm_otg, id);
1494
1495 if (event)
1496 clear_bit(ID, &motg->inputs);
1497 else
1498 set_bit(ID, &motg->inputs);
1499
1500 schedule_work(&motg->sm_work);
1501
1502 return NOTIFY_DONE;
1503 }
1504
1505 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1506 {
1507 struct msm_otg_platform_data *pdata;
1508 struct extcon_dev *ext_id, *ext_vbus;
1509 struct device_node *node = pdev->dev.of_node;
1510 struct property *prop;
1511 int len, ret, words;
1512 u32 val, tmp[3];
1513
1514 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1515 if (!pdata)
1516 return -ENOMEM;
1517
1518 motg->pdata = pdata;
1519
1520 pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1521 if (!pdata->phy_type)
1522 return 1;
1523
1524 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1525 if (IS_ERR(motg->link_rst))
1526 return PTR_ERR(motg->link_rst);
1527
1528 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1529 if (IS_ERR(motg->phy_rst))
1530 motg->phy_rst = NULL;
1531
1532 pdata->mode = usb_get_dr_mode(&pdev->dev);
1533 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1534 pdata->mode = USB_DR_MODE_OTG;
1535
1536 pdata->otg_control = OTG_PHY_CONTROL;
1537 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1538 if (val == OTG_PMIC_CONTROL)
1539 pdata->otg_control = val;
1540
1541 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1542 motg->phy_number = val;
1543
1544 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1545 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1546 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1547
1548 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1549 len == sizeof(tmp)) {
1550 of_property_read_u32_array(node, "qcom,vdd-levels",
1551 tmp, len / sizeof(*tmp));
1552 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1553 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1554 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1555 }
1556
1557 motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1558
1559 motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1560 GPIOD_OUT_LOW);
1561 if (IS_ERR(motg->switch_gpio))
1562 return PTR_ERR(motg->switch_gpio);
1563
1564 ext_id = ERR_PTR(-ENODEV);
1565 ext_vbus = ERR_PTR(-ENODEV);
1566 if (of_property_read_bool(node, "extcon")) {
1567
1568 /* Each one of them is not mandatory */
1569 ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0);
1570 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
1571 return PTR_ERR(ext_vbus);
1572
1573 ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1);
1574 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
1575 return PTR_ERR(ext_id);
1576 }
1577
1578 if (!IS_ERR(ext_vbus)) {
1579 motg->vbus.extcon = ext_vbus;
1580 motg->vbus.nb.notifier_call = msm_otg_vbus_notifier;
1581 ret = extcon_register_notifier(ext_vbus, EXTCON_USB,
1582 &motg->vbus.nb);
1583 if (ret < 0) {
1584 dev_err(&pdev->dev, "register VBUS notifier failed\n");
1585 return ret;
1586 }
1587
1588 ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB);
1589 if (ret)
1590 set_bit(B_SESS_VLD, &motg->inputs);
1591 else
1592 clear_bit(B_SESS_VLD, &motg->inputs);
1593 }
1594
1595 if (!IS_ERR(ext_id)) {
1596 motg->id.extcon = ext_id;
1597 motg->id.nb.notifier_call = msm_otg_id_notifier;
1598 ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST,
1599 &motg->id.nb);
1600 if (ret < 0) {
1601 dev_err(&pdev->dev, "register ID notifier failed\n");
1602 return ret;
1603 }
1604
1605 ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST);
1606 if (ret)
1607 clear_bit(ID, &motg->inputs);
1608 else
1609 set_bit(ID, &motg->inputs);
1610 }
1611
1612 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1613 if (!prop || !len)
1614 return 0;
1615
1616 words = len / sizeof(u32);
1617
1618 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1619 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1620 return 0;
1621 }
1622
1623 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1624 if (!pdata->phy_init_seq)
1625 return 0;
1626
1627 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1628 pdata->phy_init_seq, words);
1629 if (!ret)
1630 pdata->phy_init_sz = words;
1631
1632 return 0;
1633 }
1634
1635 static int msm_otg_reboot_notify(struct notifier_block *this,
1636 unsigned long code, void *unused)
1637 {
1638 struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1639
1640 /*
1641 * Ensure that D+/D- lines are routed to uB connector, so
1642 * we could load bootloader/kernel at next reboot
1643 */
1644 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1645 return NOTIFY_DONE;
1646 }
1647
1648 static int msm_otg_probe(struct platform_device *pdev)
1649 {
1650 struct regulator_bulk_data regs[3];
1651 int ret = 0;
1652 struct device_node *np = pdev->dev.of_node;
1653 struct msm_otg_platform_data *pdata;
1654 struct resource *res;
1655 struct msm_otg *motg;
1656 struct usb_phy *phy;
1657 void __iomem *phy_select;
1658
1659 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1660 if (!motg)
1661 return -ENOMEM;
1662
1663 pdata = dev_get_platdata(&pdev->dev);
1664 if (!pdata) {
1665 if (!np)
1666 return -ENXIO;
1667 ret = msm_otg_read_dt(pdev, motg);
1668 if (ret)
1669 return ret;
1670 }
1671
1672 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1673 GFP_KERNEL);
1674 if (!motg->phy.otg)
1675 return -ENOMEM;
1676
1677 phy = &motg->phy;
1678 phy->dev = &pdev->dev;
1679
1680 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1681 if (IS_ERR(motg->clk)) {
1682 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1683 return PTR_ERR(motg->clk);
1684 }
1685
1686 /*
1687 * If USB Core is running its protocol engine based on CORE CLK,
1688 * CORE CLK must be running at >55Mhz for correct HSUSB
1689 * operation and USB core cannot tolerate frequency changes on
1690 * CORE CLK.
1691 */
1692 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1693 if (IS_ERR(motg->pclk)) {
1694 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1695 return PTR_ERR(motg->pclk);
1696 }
1697
1698 /*
1699 * USB core clock is not present on all MSM chips. This
1700 * clock is introduced to remove the dependency on AXI
1701 * bus frequency.
1702 */
1703 motg->core_clk = devm_clk_get(&pdev->dev,
1704 np ? "alt_core" : "usb_hs_core_clk");
1705
1706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1707 if (!res)
1708 return -EINVAL;
1709 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1710 if (!motg->regs)
1711 return -ENOMEM;
1712
1713 /*
1714 * NOTE: The PHYs can be multiplexed between the chipidea controller
1715 * and the dwc3 controller, using a single bit. It is important that
1716 * the dwc3 driver does not set this bit in an incompatible way.
1717 */
1718 if (motg->phy_number) {
1719 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1720 if (!phy_select)
1721 return -ENOMEM;
1722 /* Enable second PHY with the OTG port */
1723 writel(0x1, phy_select);
1724 }
1725
1726 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1727
1728 motg->irq = platform_get_irq(pdev, 0);
1729 if (motg->irq < 0) {
1730 dev_err(&pdev->dev, "platform_get_irq failed\n");
1731 return motg->irq;
1732 }
1733
1734 regs[0].supply = "vddcx";
1735 regs[1].supply = "v3p3";
1736 regs[2].supply = "v1p8";
1737
1738 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1739 if (ret)
1740 return ret;
1741
1742 motg->vddcx = regs[0].consumer;
1743 motg->v3p3 = regs[1].consumer;
1744 motg->v1p8 = regs[2].consumer;
1745
1746 clk_set_rate(motg->clk, 60000000);
1747
1748 clk_prepare_enable(motg->clk);
1749 clk_prepare_enable(motg->pclk);
1750
1751 if (!IS_ERR(motg->core_clk))
1752 clk_prepare_enable(motg->core_clk);
1753
1754 ret = msm_hsusb_init_vddcx(motg, 1);
1755 if (ret) {
1756 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1757 goto disable_clks;
1758 }
1759
1760 ret = msm_hsusb_ldo_init(motg, 1);
1761 if (ret) {
1762 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1763 goto disable_vddcx;
1764 }
1765 ret = msm_hsusb_ldo_set_mode(motg, 1);
1766 if (ret) {
1767 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1768 goto disable_ldo;
1769 }
1770
1771 writel(0, USB_USBINTR);
1772 writel(0, USB_OTGSC);
1773
1774 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1775 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1776 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1777 "msm_otg", motg);
1778 if (ret) {
1779 dev_err(&pdev->dev, "request irq failed\n");
1780 goto disable_ldo;
1781 }
1782
1783 phy->init = msm_phy_init;
1784 phy->set_power = msm_otg_set_power;
1785 phy->notify_disconnect = msm_phy_notify_disconnect;
1786 phy->type = USB_PHY_TYPE_USB2;
1787
1788 phy->io_ops = &msm_otg_io_ops;
1789
1790 phy->otg->usb_phy = &motg->phy;
1791 phy->otg->set_host = msm_otg_set_host;
1792 phy->otg->set_peripheral = msm_otg_set_peripheral;
1793
1794 msm_usb_reset(phy);
1795
1796 ret = usb_add_phy_dev(&motg->phy);
1797 if (ret) {
1798 dev_err(&pdev->dev, "usb_add_phy failed\n");
1799 goto disable_ldo;
1800 }
1801
1802 platform_set_drvdata(pdev, motg);
1803 device_init_wakeup(&pdev->dev, 1);
1804
1805 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1806 motg->pdata->otg_control == OTG_USER_CONTROL) {
1807 ret = msm_otg_debugfs_init(motg);
1808 if (ret)
1809 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1810 }
1811
1812 if (test_bit(B_SESS_VLD, &motg->inputs)) {
1813 /* Switch D+/D- lines to Device connector */
1814 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1815 } else {
1816 /* Switch D+/D- lines to Hub */
1817 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1818 }
1819
1820 motg->reboot.notifier_call = msm_otg_reboot_notify;
1821 register_reboot_notifier(&motg->reboot);
1822
1823 pm_runtime_set_active(&pdev->dev);
1824 pm_runtime_enable(&pdev->dev);
1825
1826 return 0;
1827
1828 disable_ldo:
1829 msm_hsusb_ldo_init(motg, 0);
1830 disable_vddcx:
1831 msm_hsusb_init_vddcx(motg, 0);
1832 disable_clks:
1833 clk_disable_unprepare(motg->pclk);
1834 clk_disable_unprepare(motg->clk);
1835 if (!IS_ERR(motg->core_clk))
1836 clk_disable_unprepare(motg->core_clk);
1837 return ret;
1838 }
1839
1840 static int msm_otg_remove(struct platform_device *pdev)
1841 {
1842 struct msm_otg *motg = platform_get_drvdata(pdev);
1843 struct usb_phy *phy = &motg->phy;
1844 int cnt = 0;
1845
1846 if (phy->otg->host || phy->otg->gadget)
1847 return -EBUSY;
1848
1849 unregister_reboot_notifier(&motg->reboot);
1850
1851 /*
1852 * Ensure that D+/D- lines are routed to uB connector, so
1853 * we could load bootloader/kernel at next reboot
1854 */
1855 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1856
1857 extcon_unregister_notifier(motg->id.extcon, EXTCON_USB_HOST, &motg->id.nb);
1858 extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb);
1859
1860 msm_otg_debugfs_cleanup();
1861 cancel_delayed_work_sync(&motg->chg_work);
1862 cancel_work_sync(&motg->sm_work);
1863
1864 pm_runtime_resume(&pdev->dev);
1865
1866 device_init_wakeup(&pdev->dev, 0);
1867 pm_runtime_disable(&pdev->dev);
1868
1869 usb_remove_phy(phy);
1870 disable_irq(motg->irq);
1871
1872 /*
1873 * Put PHY in low power mode.
1874 */
1875 ulpi_read(phy, 0x14);
1876 ulpi_write(phy, 0x08, 0x09);
1877
1878 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1879 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1880 if (readl(USB_PORTSC) & PORTSC_PHCD)
1881 break;
1882 udelay(1);
1883 cnt++;
1884 }
1885 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1886 dev_err(phy->dev, "Unable to suspend PHY\n");
1887
1888 clk_disable_unprepare(motg->pclk);
1889 clk_disable_unprepare(motg->clk);
1890 if (!IS_ERR(motg->core_clk))
1891 clk_disable_unprepare(motg->core_clk);
1892 msm_hsusb_ldo_init(motg, 0);
1893
1894 pm_runtime_set_suspended(&pdev->dev);
1895
1896 return 0;
1897 }
1898
1899 #ifdef CONFIG_PM
1900 static int msm_otg_runtime_idle(struct device *dev)
1901 {
1902 struct msm_otg *motg = dev_get_drvdata(dev);
1903 struct usb_otg *otg = motg->phy.otg;
1904
1905 dev_dbg(dev, "OTG runtime idle\n");
1906
1907 /*
1908 * It is observed some times that a spurious interrupt
1909 * comes when PHY is put into LPM immediately after PHY reset.
1910 * This 1 sec delay also prevents entering into LPM immediately
1911 * after asynchronous interrupt.
1912 */
1913 if (otg->state != OTG_STATE_UNDEFINED)
1914 pm_schedule_suspend(dev, 1000);
1915
1916 return -EAGAIN;
1917 }
1918
1919 static int msm_otg_runtime_suspend(struct device *dev)
1920 {
1921 struct msm_otg *motg = dev_get_drvdata(dev);
1922
1923 dev_dbg(dev, "OTG runtime suspend\n");
1924 return msm_otg_suspend(motg);
1925 }
1926
1927 static int msm_otg_runtime_resume(struct device *dev)
1928 {
1929 struct msm_otg *motg = dev_get_drvdata(dev);
1930
1931 dev_dbg(dev, "OTG runtime resume\n");
1932 return msm_otg_resume(motg);
1933 }
1934 #endif
1935
1936 #ifdef CONFIG_PM_SLEEP
1937 static int msm_otg_pm_suspend(struct device *dev)
1938 {
1939 struct msm_otg *motg = dev_get_drvdata(dev);
1940
1941 dev_dbg(dev, "OTG PM suspend\n");
1942 return msm_otg_suspend(motg);
1943 }
1944
1945 static int msm_otg_pm_resume(struct device *dev)
1946 {
1947 struct msm_otg *motg = dev_get_drvdata(dev);
1948 int ret;
1949
1950 dev_dbg(dev, "OTG PM resume\n");
1951
1952 ret = msm_otg_resume(motg);
1953 if (ret)
1954 return ret;
1955
1956 /*
1957 * Runtime PM Documentation recommends bringing the
1958 * device to full powered state upon resume.
1959 */
1960 pm_runtime_disable(dev);
1961 pm_runtime_set_active(dev);
1962 pm_runtime_enable(dev);
1963
1964 return 0;
1965 }
1966 #endif
1967
1968 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1969 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1970 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1971 msm_otg_runtime_idle)
1972 };
1973
1974 static struct platform_driver msm_otg_driver = {
1975 .probe = msm_otg_probe,
1976 .remove = msm_otg_remove,
1977 .driver = {
1978 .name = DRIVER_NAME,
1979 .pm = &msm_otg_dev_pm_ops,
1980 .of_match_table = msm_otg_dt_match,
1981 },
1982 };
1983
1984 module_platform_driver(msm_otg_driver);
1985
1986 MODULE_LICENSE("GPL v2");
1987 MODULE_DESCRIPTION("MSM USB transceiver driver");
Linux with added FPC-III support